TargetInstrInfo.h revision f0e1b8942157f4344cce36e98c7dabb230d52bf8
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instruction set to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/Target/TargetInstrDesc.h" 18#include "llvm/CodeGen/MachineFunction.h" 19 20namespace llvm { 21 22class CalleeSavedInfo; 23class InstrItineraryData; 24class LiveVariables; 25class MCAsmInfo; 26class MachineMemOperand; 27class MDNode; 28class MCInst; 29class SDNode; 30class ScheduleHazardRecognizer; 31class SelectionDAG; 32class TargetRegisterClass; 33class TargetRegisterInfo; 34 35template<class T> class SmallVectorImpl; 36 37 38//--------------------------------------------------------------------------- 39/// 40/// TargetInstrInfo - Interface to description of machine instruction set 41/// 42class TargetInstrInfo { 43 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 44 unsigned NumOpcodes; // Number of entries in the desc array 45 46 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 47 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 48public: 49 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 50 virtual ~TargetInstrInfo(); 51 52 unsigned getNumOpcodes() const { return NumOpcodes; } 53 54 /// get - Return the machine instruction descriptor that corresponds to the 55 /// specified instruction opcode. 56 /// 57 const TargetInstrDesc &get(unsigned Opcode) const { 58 assert(Opcode < NumOpcodes && "Invalid opcode!"); 59 return Descriptors[Opcode]; 60 } 61 62 /// isTriviallyReMaterializable - Return true if the instruction is trivially 63 /// rematerializable, meaning it has no side effects and requires no operands 64 /// that aren't always available. 65 bool isTriviallyReMaterializable(const MachineInstr *MI, 66 AliasAnalysis *AA = 0) const { 67 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 68 (MI->getDesc().isRematerializable() && 69 (isReallyTriviallyReMaterializable(MI, AA) || 70 isReallyTriviallyReMaterializableGeneric(MI, AA))); 71 } 72 73protected: 74 /// isReallyTriviallyReMaterializable - For instructions with opcodes for 75 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 76 /// specify whether the instruction is actually trivially rematerializable, 77 /// taking into consideration its operands. This predicate must return false 78 /// if the instruction has any side effects other than producing a value, or 79 /// if it requres any address registers that are not always available. 80 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 81 AliasAnalysis *AA) const { 82 return false; 83 } 84 85private: 86 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 87 /// for which the M_REMATERIALIZABLE flag is set and the target hook 88 /// isReallyTriviallyReMaterializable returns false, this function does 89 /// target-independent tests to determine if the instruction is really 90 /// trivially rematerializable. 91 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 92 AliasAnalysis *AA) const; 93 94public: 95 /// isMoveInstr - Return true if the instruction is a register to register 96 /// move and return the source and dest operands and their sub-register 97 /// indices by reference. 98 virtual bool isMoveInstr(const MachineInstr& MI, 99 unsigned& SrcReg, unsigned& DstReg, 100 unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 101 return false; 102 } 103 104 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 105 /// extension instruction. That is, it's like a copy where it's legal for the 106 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 107 /// true, then it's expected the pre-extension value is available as a subreg 108 /// of the result register. This also returns the sub-register index in 109 /// SubIdx. 110 virtual bool isCoalescableExtInstr(const MachineInstr &MI, 111 unsigned &SrcReg, unsigned &DstReg, 112 unsigned &SubIdx) const { 113 return false; 114 } 115 116 /// isIdentityCopy - Return true if the instruction is a copy (or 117 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and 118 /// destination registers are the same. 119 bool isIdentityCopy(const MachineInstr &MI) const { 120 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; 121 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && 122 SrcReg == DstReg) 123 return true; 124 125 if (MI.getOpcode() == TargetOpcode::EXTRACT_SUBREG && 126 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) 127 return true; 128 129 if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG || 130 MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) && 131 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) 132 return true; 133 return false; 134 } 135 136 /// isLoadFromStackSlot - If the specified machine instruction is a direct 137 /// load from a stack slot, return the virtual or physical register number of 138 /// the destination along with the FrameIndex of the loaded stack slot. If 139 /// not, return 0. This predicate must return 0 if the instruction has 140 /// any side effects other than loading from the stack slot. 141 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 142 int &FrameIndex) const { 143 return 0; 144 } 145 146 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 147 /// stack locations as well. This uses a heuristic so it isn't 148 /// reliable for correctness. 149 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 150 int &FrameIndex) const { 151 return 0; 152 } 153 154 /// hasLoadFromStackSlot - If the specified machine instruction has 155 /// a load from a stack slot, return true along with the FrameIndex 156 /// of the loaded stack slot and the machine mem operand containing 157 /// the reference. If not, return false. Unlike 158 /// isLoadFromStackSlot, this returns true for any instructions that 159 /// loads from the stack. This is just a hint, as some cases may be 160 /// missed. 161 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 162 const MachineMemOperand *&MMO, 163 int &FrameIndex) const { 164 return 0; 165 } 166 167 /// isStoreToStackSlot - If the specified machine instruction is a direct 168 /// store to a stack slot, return the virtual or physical register number of 169 /// the source reg along with the FrameIndex of the loaded stack slot. If 170 /// not, return 0. This predicate must return 0 if the instruction has 171 /// any side effects other than storing to the stack slot. 172 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 173 int &FrameIndex) const { 174 return 0; 175 } 176 177 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 178 /// stack locations as well. This uses a heuristic so it isn't 179 /// reliable for correctness. 180 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 181 int &FrameIndex) const { 182 return 0; 183 } 184 185 /// hasStoreToStackSlot - If the specified machine instruction has a 186 /// store to a stack slot, return true along with the FrameIndex of 187 /// the loaded stack slot and the machine mem operand containing the 188 /// reference. If not, return false. Unlike isStoreToStackSlot, 189 /// this returns true for any instructions that stores to the 190 /// stack. This is just a hint, as some cases may be missed. 191 virtual bool hasStoreToStackSlot(const MachineInstr *MI, 192 const MachineMemOperand *&MMO, 193 int &FrameIndex) const { 194 return 0; 195 } 196 197 /// reMaterialize - Re-issue the specified 'original' instruction at the 198 /// specific location targeting a new destination register. 199 /// The register in Orig->getOperand(0).getReg() will be substituted by 200 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 201 /// SubIdx. 202 virtual void reMaterialize(MachineBasicBlock &MBB, 203 MachineBasicBlock::iterator MI, 204 unsigned DestReg, unsigned SubIdx, 205 const MachineInstr *Orig, 206 const TargetRegisterInfo &TRI) const = 0; 207 208 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 209 /// two-addrss instruction inserted by two-address pass. 210 virtual void scheduleTwoAddrSource(MachineInstr *SrcMI, 211 MachineInstr *UseMI, 212 const TargetRegisterInfo &TRI) const { 213 // Do nothing. 214 } 215 216 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 217 /// MachineFunction::CloneMachineInstr(), but the target may update operands 218 /// that are required to be unique. 219 /// 220 /// The instruction must be duplicable as indicated by isNotDuplicable(). 221 virtual MachineInstr *duplicate(MachineInstr *Orig, 222 MachineFunction &MF) const = 0; 223 224 /// convertToThreeAddress - This method must be implemented by targets that 225 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 226 /// may be able to convert a two-address instruction into one or more true 227 /// three-address instructions on demand. This allows the X86 target (for 228 /// example) to convert ADD and SHL instructions into LEA instructions if they 229 /// would require register copies due to two-addressness. 230 /// 231 /// This method returns a null pointer if the transformation cannot be 232 /// performed, otherwise it returns the last new instruction. 233 /// 234 virtual MachineInstr * 235 convertToThreeAddress(MachineFunction::iterator &MFI, 236 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 237 return 0; 238 } 239 240 /// commuteInstruction - If a target has any instructions that are 241 /// commutable but require converting to different instructions or making 242 /// non-trivial changes to commute them, this method can overloaded to do 243 /// that. The default implementation simply swaps the commutable operands. 244 /// If NewMI is false, MI is modified in place and returned; otherwise, a 245 /// new machine instruction is created and returned. Do not call this 246 /// method for a non-commutable instruction, but there may be some cases 247 /// where this method fails and returns null. 248 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 249 bool NewMI = false) const = 0; 250 251 /// findCommutedOpIndices - If specified MI is commutable, return the two 252 /// operand indices that would swap value. Return false if the instruction 253 /// is not in a form which this routine understands. 254 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 255 unsigned &SrcOpIdx2) const = 0; 256 257 /// produceSameValue - Return true if two machine instructions would produce 258 /// identical values. By default, this is only true when the two instructions 259 /// are deemed identical except for defs. 260 virtual bool produceSameValue(const MachineInstr *MI0, 261 const MachineInstr *MI1) const = 0; 262 263 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 264 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 265 /// implemented for a target). Upon success, this returns false and returns 266 /// with the following information in various cases: 267 /// 268 /// 1. If this block ends with no branches (it just falls through to its succ) 269 /// just return false, leaving TBB/FBB null. 270 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 271 /// the destination block. 272 /// 3. If this block ends with a conditional branch and it falls through to a 273 /// successor block, it sets TBB to be the branch destination block and a 274 /// list of operands that evaluate the condition. These operands can be 275 /// passed to other TargetInstrInfo methods to create new branches. 276 /// 4. If this block ends with a conditional branch followed by an 277 /// unconditional branch, it returns the 'true' destination in TBB, the 278 /// 'false' destination in FBB, and a list of operands that evaluate the 279 /// condition. These operands can be passed to other TargetInstrInfo 280 /// methods to create new branches. 281 /// 282 /// Note that RemoveBranch and InsertBranch must be implemented to support 283 /// cases where this method returns success. 284 /// 285 /// If AllowModify is true, then this routine is allowed to modify the basic 286 /// block (e.g. delete instructions after the unconditional branch). 287 /// 288 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 289 MachineBasicBlock *&FBB, 290 SmallVectorImpl<MachineOperand> &Cond, 291 bool AllowModify = false) const { 292 return true; 293 } 294 295 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 296 /// This is only invoked in cases where AnalyzeBranch returns success. It 297 /// returns the number of instructions that were removed. 298 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 299 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 300 return 0; 301 } 302 303 /// InsertBranch - Insert branch code into the end of the specified 304 /// MachineBasicBlock. The operands to this method are the same as those 305 /// returned by AnalyzeBranch. This is only invoked in cases where 306 /// AnalyzeBranch returns success. It returns the number of instructions 307 /// inserted. 308 /// 309 /// It is also invoked by tail merging to add unconditional branches in 310 /// cases where AnalyzeBranch doesn't apply because there was no original 311 /// branch to analyze. At least this much must be implemented, else tail 312 /// merging needs to be disabled. 313 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 314 MachineBasicBlock *FBB, 315 const SmallVectorImpl<MachineOperand> &Cond, 316 DebugLoc DL) const { 317 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 318 return 0; 319 } 320 321 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 322 /// after it, replacing it with an unconditional branch to NewDest. This is 323 /// used by the tail merging pass. 324 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 325 MachineBasicBlock *NewDest) const = 0; 326 327 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 328 /// block at the specified instruction (i.e. instruction would be the start 329 /// of a new basic block). 330 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 331 MachineBasicBlock::iterator MBBI) const { 332 return true; 333 } 334 335 /// copyRegToReg - Emit instructions to copy between a pair of registers. It 336 /// returns false if the target does not how to copy between the specified 337 /// registers. 338 virtual bool copyRegToReg(MachineBasicBlock &MBB, 339 MachineBasicBlock::iterator MI, 340 unsigned DestReg, unsigned SrcReg, 341 const TargetRegisterClass *DestRC, 342 const TargetRegisterClass *SrcRC, 343 DebugLoc DL) const { 344 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 345 return false; 346 } 347 348 /// storeRegToStackSlot - Store the specified register of the given register 349 /// class to the specified stack frame index. The store instruction is to be 350 /// added to the given machine basic block before the specified machine 351 /// instruction. If isKill is true, the register operand is the last use and 352 /// must be marked kill. 353 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 354 MachineBasicBlock::iterator MI, 355 unsigned SrcReg, bool isKill, int FrameIndex, 356 const TargetRegisterClass *RC, 357 const TargetRegisterInfo *TRI) const { 358 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 359 } 360 361 /// loadRegFromStackSlot - Load the specified register of the given register 362 /// class from the specified stack frame index. The load instruction is to be 363 /// added to the given machine basic block before the specified machine 364 /// instruction. 365 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 366 MachineBasicBlock::iterator MI, 367 unsigned DestReg, int FrameIndex, 368 const TargetRegisterClass *RC, 369 const TargetRegisterInfo *TRI) const { 370 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 371 } 372 373 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 374 /// saved registers and returns true if it isn't possible / profitable to do 375 /// so by issuing a series of store instructions via 376 /// storeRegToStackSlot(). Returns false otherwise. 377 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 378 MachineBasicBlock::iterator MI, 379 const std::vector<CalleeSavedInfo> &CSI, 380 const TargetRegisterInfo *TRI) const { 381 return false; 382 } 383 384 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 385 /// saved registers and returns true if it isn't possible / profitable to do 386 /// so by issuing a series of load instructions via loadRegToStackSlot(). 387 /// Returns false otherwise. 388 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 389 MachineBasicBlock::iterator MI, 390 const std::vector<CalleeSavedInfo> &CSI, 391 const TargetRegisterInfo *TRI) const { 392 return false; 393 } 394 395 /// emitFrameIndexDebugValue - Emit a target-dependent form of 396 /// DBG_VALUE encoding the address of a frame index. Addresses would 397 /// normally be lowered the same way as other addresses on the target, 398 /// e.g. in load instructions. For targets that do not support this 399 /// the debug info is simply lost. 400 /// If you add this for a target you should handle this DBG_VALUE in the 401 /// target-specific AsmPrinter code as well; you will probably get invalid 402 /// assembly output if you don't. 403 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 404 int FrameIx, 405 uint64_t Offset, 406 const MDNode *MDPtr, 407 DebugLoc dl) const { 408 return 0; 409 } 410 411 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 412 /// slot into the specified machine instruction for the specified operand(s). 413 /// If this is possible, a new instruction is returned with the specified 414 /// operand folded, otherwise NULL is returned. The client is responsible for 415 /// removing the old instruction and adding the new one in the instruction 416 /// stream. 417 MachineInstr* foldMemoryOperand(MachineFunction &MF, 418 MachineInstr* MI, 419 const SmallVectorImpl<unsigned> &Ops, 420 int FrameIndex) const; 421 422 /// foldMemoryOperand - Same as the previous version except it allows folding 423 /// of any load and store from / to any address, not just from a specific 424 /// stack slot. 425 MachineInstr* foldMemoryOperand(MachineFunction &MF, 426 MachineInstr* MI, 427 const SmallVectorImpl<unsigned> &Ops, 428 MachineInstr* LoadMI) const; 429 430protected: 431 /// foldMemoryOperandImpl - Target-dependent implementation for 432 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 433 /// take care of adding a MachineMemOperand to the newly created instruction. 434 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 435 MachineInstr* MI, 436 const SmallVectorImpl<unsigned> &Ops, 437 int FrameIndex) const { 438 return 0; 439 } 440 441 /// foldMemoryOperandImpl - Target-dependent implementation for 442 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 443 /// take care of adding a MachineMemOperand to the newly created instruction. 444 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 445 MachineInstr* MI, 446 const SmallVectorImpl<unsigned> &Ops, 447 MachineInstr* LoadMI) const { 448 return 0; 449 } 450 451public: 452 /// canFoldMemoryOperand - Returns true for the specified load / store if 453 /// folding is possible. 454 virtual 455 bool canFoldMemoryOperand(const MachineInstr *MI, 456 const SmallVectorImpl<unsigned> &Ops) const { 457 return false; 458 } 459 460 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 461 /// a store or a load and a store into two or more instruction. If this is 462 /// possible, returns true as well as the new instructions by reference. 463 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 464 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 465 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 466 return false; 467 } 468 469 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 470 SmallVectorImpl<SDNode*> &NewNodes) const { 471 return false; 472 } 473 474 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 475 /// instruction after load / store are unfolded from an instruction of the 476 /// specified opcode. It returns zero if the specified unfolding is not 477 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 478 /// index of the operand which will hold the register holding the loaded 479 /// value. 480 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 481 bool UnfoldLoad, bool UnfoldStore, 482 unsigned *LoadRegIndex = 0) const { 483 return 0; 484 } 485 486 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 487 /// to determine if two loads are loading from the same base address. It 488 /// should only return true if the base pointers are the same and the 489 /// only differences between the two addresses are the offset. It also returns 490 /// the offsets by reference. 491 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 492 int64_t &Offset1, int64_t &Offset2) const { 493 return false; 494 } 495 496 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 497 /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 498 /// be scheduled togther. On some targets if two loads are loading from 499 /// addresses in the same cache line, it's better if they are scheduled 500 /// together. This function takes two integers that represent the load offsets 501 /// from the common base address. It returns true if it decides it's desirable 502 /// to schedule the two loads together. "NumLoads" is the number of loads that 503 /// have already been scheduled after Load1. 504 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 505 int64_t Offset1, int64_t Offset2, 506 unsigned NumLoads) const { 507 return false; 508 } 509 510 /// ReverseBranchCondition - Reverses the branch condition of the specified 511 /// condition list, returning false on success and true if it cannot be 512 /// reversed. 513 virtual 514 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 515 return true; 516 } 517 518 /// insertNoop - Insert a noop into the instruction stream at the specified 519 /// point. 520 virtual void insertNoop(MachineBasicBlock &MBB, 521 MachineBasicBlock::iterator MI) const; 522 523 524 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 525 virtual void getNoopForMachoTarget(MCInst &NopInst) const { 526 // Default to just using 'nop' string. 527 } 528 529 530 /// isPredicated - Returns true if the instruction is already predicated. 531 /// 532 virtual bool isPredicated(const MachineInstr *MI) const { 533 return false; 534 } 535 536 /// isUnpredicatedTerminator - Returns true if the instruction is a 537 /// terminator instruction that has not been predicated. 538 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 539 540 /// PredicateInstruction - Convert the instruction into a predicated 541 /// instruction. It returns true if the operation was successful. 542 virtual 543 bool PredicateInstruction(MachineInstr *MI, 544 const SmallVectorImpl<MachineOperand> &Pred) const = 0; 545 546 /// SubsumesPredicate - Returns true if the first specified predicate 547 /// subsumes the second, e.g. GE subsumes GT. 548 virtual 549 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 550 const SmallVectorImpl<MachineOperand> &Pred2) const { 551 return false; 552 } 553 554 /// DefinesPredicate - If the specified instruction defines any predicate 555 /// or condition code register(s) used for predication, returns true as well 556 /// as the definition predicate(s) by reference. 557 virtual bool DefinesPredicate(MachineInstr *MI, 558 std::vector<MachineOperand> &Pred) const { 559 return false; 560 } 561 562 /// isPredicable - Return true if the specified instruction can be predicated. 563 /// By default, this returns true for every instruction with a 564 /// PredicateOperand. 565 virtual bool isPredicable(MachineInstr *MI) const { 566 return MI->getDesc().isPredicable(); 567 } 568 569 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 570 /// instruction that defines the specified register class. 571 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 572 return true; 573 } 574 575 /// isSchedulingBoundary - Test if the given instruction should be 576 /// considered a scheduling boundary. This primarily includes labels and 577 /// terminators. 578 virtual bool isSchedulingBoundary(const MachineInstr *MI, 579 const MachineBasicBlock *MBB, 580 const MachineFunction &MF) const = 0; 581 582 /// GetInstSize - Returns the size of the specified Instruction. 583 /// 584 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 585 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 586 return 0; 587 } 588 589 /// GetFunctionSizeInBytes - Returns the size of the specified 590 /// MachineFunction. 591 /// 592 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 593 594 /// Measure the specified inline asm to determine an approximation of its 595 /// length. 596 virtual unsigned getInlineAsmLength(const char *Str, 597 const MCAsmInfo &MAI) const; 598 599 /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer 600 /// to use for this target when scheduling the machine instructions after 601 /// register allocation. 602 virtual ScheduleHazardRecognizer* 603 CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const = 0; 604}; 605 606/// TargetInstrInfoImpl - This is the default implementation of 607/// TargetInstrInfo, which just provides a couple of default implementations 608/// for various methods. This separated out because it is implemented in 609/// libcodegen, not in libtarget. 610class TargetInstrInfoImpl : public TargetInstrInfo { 611protected: 612 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 613 : TargetInstrInfo(desc, NumOpcodes) {} 614public: 615 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, 616 MachineBasicBlock *NewDest) const; 617 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 618 bool NewMI = false) const; 619 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 620 unsigned &SrcOpIdx2) const; 621 virtual bool PredicateInstruction(MachineInstr *MI, 622 const SmallVectorImpl<MachineOperand> &Pred) const; 623 virtual void reMaterialize(MachineBasicBlock &MBB, 624 MachineBasicBlock::iterator MI, 625 unsigned DestReg, unsigned SubReg, 626 const MachineInstr *Orig, 627 const TargetRegisterInfo &TRI) const; 628 virtual MachineInstr *duplicate(MachineInstr *Orig, 629 MachineFunction &MF) const; 630 virtual bool produceSameValue(const MachineInstr *MI0, 631 const MachineInstr *MI1) const; 632 virtual bool isSchedulingBoundary(const MachineInstr *MI, 633 const MachineBasicBlock *MBB, 634 const MachineFunction &MF) const; 635 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 636 637 virtual ScheduleHazardRecognizer * 638 CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const; 639}; 640 641} // End llvm namespace 642 643#endif 644