TargetInstrInfo.h revision f2f6a1baf78f3bdf375b258996abd567c20496bc
1//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the target machine instructions to the code generator. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETINSTRINFO_H 15#define LLVM_TARGET_TARGETINSTRINFO_H 16 17#include "llvm/CodeGen/MachineBasicBlock.h" 18#include "llvm/CodeGen/MachineFunction.h" 19#include "llvm/Support/DataTypes.h" 20#include <vector> 21#include <cassert> 22 23namespace llvm { 24 25class MachineInstr; 26class TargetMachine; 27class Value; 28class Type; 29class Instruction; 30class Constant; 31class Function; 32class MachineCodeForInstruction; 33class TargetRegisterClass; 34class LiveVariables; 35 36//--------------------------------------------------------------------------- 37// Data types used to define information about a single machine instruction 38//--------------------------------------------------------------------------- 39 40typedef short MachineOpCode; 41typedef unsigned InstrSchedClass; 42 43//--------------------------------------------------------------------------- 44// struct TargetInstrDescriptor: 45// Predefined information about each machine instruction. 46// Designed to initialized statically. 47// 48 49const unsigned M_BRANCH_FLAG = 1 << 0; 50const unsigned M_CALL_FLAG = 1 << 1; 51const unsigned M_RET_FLAG = 1 << 2; 52const unsigned M_BARRIER_FLAG = 1 << 3; 53const unsigned M_DELAY_SLOT_FLAG = 1 << 4; 54const unsigned M_LOAD_FLAG = 1 << 5; 55const unsigned M_STORE_FLAG = 1 << 6; 56 57// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be 58// changed into a 3-address instruction if the first two operands cannot be 59// assigned to the same register. The target must implement the 60// TargetInstrInfo::convertToThreeAddress method for this instruction. 61const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 7; 62 63// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 64// Z), which produces the same result if Y and Z are exchanged. 65const unsigned M_COMMUTABLE = 1 << 8; 66 67// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 68// block? Typically this is things like return and branch instructions. 69// Various passes use this to insert code into the bottom of a basic block, but 70// before control flow occurs. 71const unsigned M_TERMINATOR_FLAG = 1 << 9; 72 73// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 74// insertion support when the DAG scheduler is inserting it into a machine basic 75// block. 76const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 10; 77 78// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 79// operands in addition to the minimum number operands specified. 80const unsigned M_VARIABLE_OPS = 1 << 11; 81 82// M_PREDICATED - Set if this instruction has a predicate that controls its 83// execution. 84const unsigned M_PREDICATED = 1 << 12; 85 86 87// Machine operand flags 88// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 89// requires a callback to look up its register class. 90const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 91 92/// M_PREDICATE_OPERAND - Set if this is the first operand of a predicate 93/// operand that controls an M_PREDICATED instruction. 94const unsigned M_PREDICATE_OPERAND = 1 << 1; 95 96namespace TOI { 97 // Operand constraints: only "tied_to" for now. 98 enum OperandConstraint { 99 TIED_TO = 0 // Must be allocated the same register as. 100 }; 101} 102 103/// TargetOperandInfo - This holds information about one operand of a machine 104/// instruction, indicating the register class for register operands, etc. 105/// 106class TargetOperandInfo { 107public: 108 /// RegClass - This specifies the register class enumeration of the operand 109 /// if the operand is a register. If not, this contains 0. 110 unsigned short RegClass; 111 unsigned short Flags; 112 /// Lower 16 bits are used to specify which constraints are set. The higher 16 113 /// bits are used to specify the value of constraints (4 bits each). 114 unsigned int Constraints; 115 /// Currently no other information. 116}; 117 118 119class TargetInstrDescriptor { 120public: 121 MachineOpCode Opcode; // The opcode. 122 unsigned short numOperands; // Num of args (may be more if variable_ops). 123 const char * Name; // Assembly language mnemonic for the opcode. 124 InstrSchedClass schedClass; // enum identifying instr sched class 125 unsigned Flags; // flags identifying machine instr class 126 unsigned TSFlags; // Target Specific Flag values 127 const unsigned *ImplicitUses; // Registers implicitly read by this instr 128 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 129 const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 130 131 /// getOperandConstraint - Returns the value of the specific constraint if 132 /// it is set. Returns -1 if it is not set. 133 int getOperandConstraint(unsigned OpNum, 134 TOI::OperandConstraint Constraint) const { 135 assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) && 136 "Invalid operand # of TargetInstrInfo"); 137 if (OpNum < numOperands && 138 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 139 unsigned Pos = 16 + Constraint * 4; 140 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 141 } 142 return -1; 143 } 144 145 /// findTiedToSrcOperand - Returns the operand that is tied to the specified 146 /// dest operand. Returns -1 if there isn't one. 147 int findTiedToSrcOperand(unsigned OpNum) const; 148}; 149 150 151//--------------------------------------------------------------------------- 152/// 153/// TargetInstrInfo - Interface to description of machine instructions 154/// 155class TargetInstrInfo { 156 const TargetInstrDescriptor* desc; // raw array to allow static init'n 157 unsigned NumOpcodes; // number of entries in the desc array 158 unsigned numRealOpCodes; // number of non-dummy op codes 159 160 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 161 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 162public: 163 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 164 virtual ~TargetInstrInfo(); 165 166 // Invariant opcodes: All instruction sets have these as their low opcodes. 167 enum { 168 PHI = 0, 169 INLINEASM = 1 170 }; 171 172 unsigned getNumOpcodes() const { return NumOpcodes; } 173 174 /// get - Return the machine instruction descriptor that corresponds to the 175 /// specified instruction opcode. 176 /// 177 const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 178 assert((unsigned)Opcode < NumOpcodes); 179 return desc[Opcode]; 180 } 181 182 const char *getName(MachineOpCode Opcode) const { 183 return get(Opcode).Name; 184 } 185 186 int getNumOperands(MachineOpCode Opcode) const { 187 return get(Opcode).numOperands; 188 } 189 190 InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 191 return get(Opcode).schedClass; 192 } 193 194 const unsigned *getImplicitUses(MachineOpCode Opcode) const { 195 return get(Opcode).ImplicitUses; 196 } 197 198 const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 199 return get(Opcode).ImplicitDefs; 200 } 201 202 203 // 204 // Query instruction class flags according to the machine-independent 205 // flags listed above. 206 // 207 bool isReturn(MachineOpCode Opcode) const { 208 return get(Opcode).Flags & M_RET_FLAG; 209 } 210 211 bool isPredicated(MachineOpCode Opcode) const { 212 return get(Opcode).Flags & M_PREDICATED; 213 } 214 bool isCommutableInstr(MachineOpCode Opcode) const { 215 return get(Opcode).Flags & M_COMMUTABLE; 216 } 217 bool isTerminatorInstr(unsigned Opcode) const { 218 return get(Opcode).Flags & M_TERMINATOR_FLAG; 219 } 220 221 bool isBranch(MachineOpCode Opcode) const { 222 return get(Opcode).Flags & M_BRANCH_FLAG; 223 } 224 225 /// isBarrier - Returns true if the specified instruction stops control flow 226 /// from executing the instruction immediately following it. Examples include 227 /// unconditional branches and return instructions. 228 bool isBarrier(MachineOpCode Opcode) const { 229 return get(Opcode).Flags & M_BARRIER_FLAG; 230 } 231 232 bool isCall(MachineOpCode Opcode) const { 233 return get(Opcode).Flags & M_CALL_FLAG; 234 } 235 bool isLoad(MachineOpCode Opcode) const { 236 return get(Opcode).Flags & M_LOAD_FLAG; 237 } 238 bool isStore(MachineOpCode Opcode) const { 239 return get(Opcode).Flags & M_STORE_FLAG; 240 } 241 242 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 243 /// which must be filled by the code generator. 244 bool hasDelaySlot(unsigned Opcode) const { 245 return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 246 } 247 248 /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 249 /// custom insertion support when the DAG scheduler is inserting it into a 250 /// machine basic block. 251 bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 252 return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 253 } 254 255 bool hasVariableOperands(MachineOpCode Opcode) const { 256 return get(Opcode).Flags & M_VARIABLE_OPS; 257 } 258 259 /// getOperandConstraint - Returns the value of the specific constraint if 260 /// it is set. Returns -1 if it is not set. 261 int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum, 262 TOI::OperandConstraint Constraint) const { 263 return get(Opcode).getOperandConstraint(OpNum, Constraint); 264 } 265 266 /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL 267 /// instruction if it has one. This is used by codegen passes that update 268 /// DWARF line number info as they modify the code. 269 virtual unsigned getDWARF_LABELOpcode() const { 270 return 0; 271 } 272 273 /// Return true if the instruction is a register to register move 274 /// and leave the source and dest operands in the passed parameters. 275 virtual bool isMoveInstr(const MachineInstr& MI, 276 unsigned& sourceReg, 277 unsigned& destReg) const { 278 return false; 279 } 280 281 /// isLoadFromStackSlot - If the specified machine instruction is a direct 282 /// load from a stack slot, return the virtual or physical register number of 283 /// the destination along with the FrameIndex of the loaded stack slot. If 284 /// not, return 0. This predicate must return 0 if the instruction has 285 /// any side effects other than loading from the stack slot. 286 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 287 return 0; 288 } 289 290 /// isStoreToStackSlot - If the specified machine instruction is a direct 291 /// store to a stack slot, return the virtual or physical register number of 292 /// the source reg along with the FrameIndex of the loaded stack slot. If 293 /// not, return 0. This predicate must return 0 if the instruction has 294 /// any side effects other than storing to the stack slot. 295 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 296 return 0; 297 } 298 299 /// convertToThreeAddress - This method must be implemented by targets that 300 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 301 /// may be able to convert a two-address instruction into one or moretrue 302 /// three-address instructions on demand. This allows the X86 target (for 303 /// example) to convert ADD and SHL instructions into LEA instructions if they 304 /// would require register copies due to two-addressness. 305 /// 306 /// This method returns a null pointer if the transformation cannot be 307 /// performed, otherwise it returns the last new instruction. 308 /// 309 virtual MachineInstr * 310 convertToThreeAddress(MachineFunction::iterator &MFI, 311 MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 312 return 0; 313 } 314 315 /// commuteInstruction - If a target has any instructions that are commutable, 316 /// but require converting to a different instruction or making non-trivial 317 /// changes to commute them, this method can overloaded to do this. The 318 /// default implementation of this method simply swaps the first two operands 319 /// of MI and returns it. 320 /// 321 /// If a target wants to make more aggressive changes, they can construct and 322 /// return a new machine instruction. If an instruction cannot commute, it 323 /// can also return null. 324 /// 325 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 326 327 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 328 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 329 /// implemented for a target). Upon success, this returns false and returns 330 /// with the following information in various cases: 331 /// 332 /// 1. If this block ends with no branches (it just falls through to its succ) 333 /// just return false, leaving TBB/FBB null. 334 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 335 /// the destination block. 336 /// 3. If this block ends with an conditional branch, it returns the 'true' 337 /// destination in TBB, the 'false' destination in FBB, and a list of 338 /// operands that evaluate the condition. These operands can be passed to 339 /// other TargetInstrInfo methods to create new branches. 340 /// 341 /// Note that RemoveBranch and InsertBranch must be implemented to support 342 /// cases where this method returns success. 343 /// 344 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 345 MachineBasicBlock *&FBB, 346 std::vector<MachineOperand> &Cond) const { 347 return true; 348 } 349 350 /// RemoveBranch - Remove the branching code at the end of the specific MBB. 351 /// this is only invoked in cases where AnalyzeBranch returns success. 352 virtual void RemoveBranch(MachineBasicBlock &MBB) const { 353 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 354 } 355 356 /// InsertBranch - Insert a branch into the end of the specified 357 /// MachineBasicBlock. This operands to this method are the same as those 358 /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 359 /// returns success and when an unconditional branch (TBB is non-null, FBB is 360 /// null, Cond is empty) needs to be inserted. 361 virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 362 MachineBasicBlock *FBB, 363 const std::vector<MachineOperand> &Cond) const { 364 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 365 } 366 367 /// BlockHasNoFallThrough - Return true if the specified block does not 368 /// fall-through into its successor block. This is primarily used when a 369 /// branch is unanalyzable. It is useful for things like unconditional 370 /// indirect branches (jump tables). 371 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 372 return false; 373 } 374 375 /// ReverseBranchCondition - Reverses the branch condition of the specified 376 /// condition list, returning false on success and true if it cannot be 377 /// reversed. 378 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 379 return true; 380 } 381 382 /// insertNoop - Insert a noop into the instruction stream at the specified 383 /// point. 384 virtual void insertNoop(MachineBasicBlock &MBB, 385 MachineBasicBlock::iterator MI) const { 386 assert(0 && "Target didn't implement insertNoop!"); 387 abort(); 388 } 389 390 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 391 /// values. 392 virtual const TargetRegisterClass *getPointerRegClass() const { 393 assert(0 && "Target didn't implement getPointerRegClass!"); 394 abort(); 395 } 396}; 397 398} // End llvm namespace 399 400#endif 401