TargetMachine.h revision 31649e61bcead26a63c7cd452da90fff5e000b91
1//===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the TargetMachine and LLVMTargetMachine classes. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETMACHINE_H 15#define LLVM_TARGET_TARGETMACHINE_H 16 17#include "llvm/Target/TargetInstrItineraries.h" 18#include <cassert> 19#include <string> 20 21namespace llvm { 22 23class Target; 24class MCAsmInfo; 25class TargetData; 26class TargetSubtarget; 27class TargetInstrInfo; 28class TargetIntrinsicInfo; 29class TargetJITInfo; 30class TargetLowering; 31class TargetSelectionDAGInfo; 32class TargetFrameLowering; 33class JITCodeEmitter; 34class MCContext; 35class TargetRegisterInfo; 36class PassManagerBase; 37class PassManager; 38class Pass; 39class TargetELFWriterInfo; 40class formatted_raw_ostream; 41class raw_ostream; 42 43// Relocation model types. 44namespace Reloc { 45 enum Model { 46 Default, 47 Static, 48 PIC_, // Cannot be named PIC due to collision with -DPIC 49 DynamicNoPIC 50 }; 51} 52 53// Code model types. 54namespace CodeModel { 55 enum Model { 56 Default, 57 Small, 58 Kernel, 59 Medium, 60 Large 61 }; 62} 63 64// Code generation optimization level. 65namespace CodeGenOpt { 66 enum Level { 67 None, // -O0 68 Less, // -O1 69 Default, // -O2, -Os 70 Aggressive // -O3 71 }; 72} 73 74namespace Sched { 75 enum Preference { 76 None, // No preference 77 Latency, // Scheduling for shortest total latency. 78 RegPressure, // Scheduling for lowest register pressure. 79 Hybrid, // Scheduling for both latency and register pressure. 80 ILP // Scheduling for ILP in low register pressure mode. 81 }; 82} 83 84//===----------------------------------------------------------------------===// 85/// 86/// TargetMachine - Primary interface to the complete machine description for 87/// the target machine. All target-specific information should be accessible 88/// through this interface. 89/// 90class TargetMachine { 91 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT 92 void operator=(const TargetMachine &); // DO NOT IMPLEMENT 93protected: // Can only create subclasses. 94 TargetMachine(const Target &); 95 96 /// getSubtargetImpl - virtual method implemented by subclasses that returns 97 /// a reference to that target's TargetSubtarget-derived member variable. 98 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; } 99 100 /// TheTarget - The Target that this machine was created for. 101 const Target &TheTarget; 102 103 /// AsmInfo - Contains target specific asm information. 104 /// 105 const MCAsmInfo *AsmInfo; 106 107 unsigned MCRelaxAll : 1; 108 unsigned MCNoExecStack : 1; 109 unsigned MCUseLoc : 1; 110 111public: 112 virtual ~TargetMachine(); 113 114 const Target &getTarget() const { return TheTarget; } 115 116 // Interfaces to the major aspects of target machine information: 117 // -- Instruction opcode and operand information 118 // -- Pipelines and scheduling information 119 // -- Stack frame information 120 // -- Selection DAG lowering information 121 // 122 virtual const TargetInstrInfo *getInstrInfo() const { return 0; } 123 virtual const TargetFrameLowering *getFrameLowering() const { return 0; } 124 virtual const TargetLowering *getTargetLowering() const { return 0; } 125 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; } 126 virtual const TargetData *getTargetData() const { return 0; } 127 128 /// getMCAsmInfo - Return target specific asm information. 129 /// 130 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; } 131 132 /// getSubtarget - This method returns a pointer to the specified type of 133 /// TargetSubtarget. In debug builds, it verifies that the object being 134 /// returned is of the correct type. 135 template<typename STC> const STC &getSubtarget() const { 136 return *static_cast<const STC*>(getSubtargetImpl()); 137 } 138 139 /// getRegisterInfo - If register information is available, return it. If 140 /// not, return null. This is kept separate from RegInfo until RegInfo has 141 /// details of graph coloring register allocation removed from it. 142 /// 143 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; } 144 145 /// getIntrinsicInfo - If intrinsic information is available, return it. If 146 /// not, return null. 147 /// 148 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; } 149 150 /// getJITInfo - If this target supports a JIT, return information for it, 151 /// otherwise return null. 152 /// 153 virtual TargetJITInfo *getJITInfo() { return 0; } 154 155 /// getInstrItineraryData - Returns instruction itinerary data for the target 156 /// or specific subtarget. 157 /// 158 virtual const InstrItineraryData *getInstrItineraryData() const { 159 return 0; 160 } 161 162 /// getELFWriterInfo - If this target supports an ELF writer, return 163 /// information for it, otherwise return null. 164 /// 165 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; } 166 167 /// hasMCRelaxAll - Check whether all machine code instructions should be 168 /// relaxed. 169 bool hasMCRelaxAll() const { return MCRelaxAll; } 170 171 /// setMCRelaxAll - Set whether all machine code instructions should be 172 /// relaxed. 173 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; } 174 175 /// hasMCNoExecStack - Check whether an executable stack is not needed. 176 bool hasMCNoExecStack() const { return MCNoExecStack; } 177 178 /// setMCNoExecStack - Set whether an executabel stack is not needed. 179 void setMCNoExecStack(bool Value) { MCNoExecStack = Value; } 180 181 /// hasMCUseLoc - Check whether we should use dwarf's .loc directive. 182 bool hasMCUseLoc() const { return MCUseLoc; } 183 184 /// setMCUseLoc - Set whether all we should use dwarf's .loc directive. 185 void setMCUseLoc(bool Value) { MCUseLoc = Value; } 186 187 /// getRelocationModel - Returns the code generation relocation model. The 188 /// choices are static, PIC, and dynamic-no-pic, and target default. 189 static Reloc::Model getRelocationModel(); 190 191 /// setRelocationModel - Sets the code generation relocation model. 192 /// 193 static void setRelocationModel(Reloc::Model Model); 194 195 /// getCodeModel - Returns the code model. The choices are small, kernel, 196 /// medium, large, and target default. 197 static CodeModel::Model getCodeModel(); 198 199 /// setCodeModel - Sets the code model. 200 /// 201 static void setCodeModel(CodeModel::Model Model); 202 203 /// getAsmVerbosityDefault - Returns the default value of asm verbosity. 204 /// 205 static bool getAsmVerbosityDefault(); 206 207 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default 208 /// is false. 209 static void setAsmVerbosityDefault(bool); 210 211 /// getDataSections - Return true if data objects should be emitted into their 212 /// own section, corresponds to -fdata-sections. 213 static bool getDataSections(); 214 215 /// getFunctionSections - Return true if functions should be emitted into 216 /// their own section, corresponding to -ffunction-sections. 217 static bool getFunctionSections(); 218 219 /// setDataSections - Set if the data are emit into separate sections. 220 static void setDataSections(bool); 221 222 /// setFunctionSections - Set if the functions are emit into separate 223 /// sections. 224 static void setFunctionSections(bool); 225 226 /// CodeGenFileType - These enums are meant to be passed into 227 /// addPassesToEmitFile to indicate what type of file to emit, and returned by 228 /// it to indicate what type of file could actually be made. 229 enum CodeGenFileType { 230 CGFT_AssemblyFile, 231 CGFT_ObjectFile, 232 CGFT_Null // Do not emit any output. 233 }; 234 235 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge 236 /// on this target. User flag overrides. 237 virtual bool getEnableTailMergeDefault() const { return true; } 238 239 /// addPassesToEmitFile - Add passes to the specified pass manager to get the 240 /// specified file emitted. Typically this will involve several steps of code 241 /// generation. This method should return true if emission of this file type 242 /// is not supported, or false on success. 243 virtual bool addPassesToEmitFile(PassManagerBase &, 244 formatted_raw_ostream &, 245 CodeGenFileType, 246 CodeGenOpt::Level, 247 bool = true) { 248 return true; 249 } 250 251 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 252 /// get machine code emitted. This uses a JITCodeEmitter object to handle 253 /// actually outputting the machine code and resolving things like the address 254 /// of functions. This method returns true if machine code emission is 255 /// not supported. 256 /// 257 virtual bool addPassesToEmitMachineCode(PassManagerBase &, 258 JITCodeEmitter &, 259 CodeGenOpt::Level, 260 bool = true) { 261 return true; 262 } 263 264 /// addPassesToEmitMC - Add passes to the specified pass manager to get 265 /// machine code emitted with the MCJIT. This method returns true if machine 266 /// code is not supported. It fills the MCContext Ctx pointer which can be 267 /// used to build custom MCStreamer. 268 /// 269 virtual bool addPassesToEmitMC(PassManagerBase &, 270 MCContext *&, 271 raw_ostream &OS, 272 CodeGenOpt::Level, 273 bool = true) { 274 return true; 275 } 276}; 277 278/// LLVMTargetMachine - This class describes a target machine that is 279/// implemented with the LLVM target-independent code generator. 280/// 281class LLVMTargetMachine : public TargetMachine { 282 std::string TargetTriple; 283 284protected: // Can only create subclasses. 285 LLVMTargetMachine(const Target &T, const std::string &TargetTriple); 286 287private: 288 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for 289 /// both emitting to assembly files or machine code output. 290 /// 291 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level, 292 bool DisableVerify, MCContext *&OutCtx); 293 294 virtual void setCodeModelForJIT(); 295 virtual void setCodeModelForStatic(); 296 297public: 298 299 const std::string &getTargetTriple() const { return TargetTriple; } 300 301 /// addPassesToEmitFile - Add passes to the specified pass manager to get the 302 /// specified file emitted. Typically this will involve several steps of code 303 /// generation. If OptLevel is None, the code generator should emit code as 304 /// fast as possible, though the generated code may be less efficient. 305 virtual bool addPassesToEmitFile(PassManagerBase &PM, 306 formatted_raw_ostream &Out, 307 CodeGenFileType FileType, 308 CodeGenOpt::Level, 309 bool DisableVerify = true); 310 311 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 312 /// get machine code emitted. This uses a JITCodeEmitter object to handle 313 /// actually outputting the machine code and resolving things like the address 314 /// of functions. This method returns true if machine code emission is 315 /// not supported. 316 /// 317 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM, 318 JITCodeEmitter &MCE, 319 CodeGenOpt::Level, 320 bool DisableVerify = true); 321 322 /// addPassesToEmitMC - Add passes to the specified pass manager to get 323 /// machine code emitted with the MCJIT. This method returns true if machine 324 /// code is not supported. It fills the MCContext Ctx pointer which can be 325 /// used to build custom MCStreamer. 326 /// 327 virtual bool addPassesToEmitMC(PassManagerBase &PM, 328 MCContext *&Ctx, 329 raw_ostream &OS, 330 CodeGenOpt::Level OptLevel, 331 bool DisableVerify = true); 332 333 /// Target-Independent Code Generator Pass Configuration Options. 334 335 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM 336 /// passes (which are run just before instruction selector). 337 virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) { 338 return true; 339 } 340 341 /// addInstSelector - This method should install an instruction selector pass, 342 /// which converts from LLVM code to machine instructions. 343 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) { 344 return true; 345 } 346 347 /// addPreRegAlloc - This method may be implemented by targets that want to 348 /// run passes immediately before register allocation. This should return 349 /// true if -print-machineinstrs should print after these passes. 350 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) { 351 return false; 352 } 353 354 /// addPostRegAlloc - This method may be implemented by targets that want 355 /// to run passes after register allocation but before prolog-epilog 356 /// insertion. This should return true if -print-machineinstrs should print 357 /// after these passes. 358 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) { 359 return false; 360 } 361 362 /// addPreSched2 - This method may be implemented by targets that want to 363 /// run passes after prolog-epilog insertion and before the second instruction 364 /// scheduling pass. This should return true if -print-machineinstrs should 365 /// print after these passes. 366 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) { 367 return false; 368 } 369 370 /// addPreEmitPass - This pass may be implemented by targets that want to run 371 /// passes immediately before machine code is emitted. This should return 372 /// true if -print-machineinstrs should print out the code after the passes. 373 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) { 374 return false; 375 } 376 377 378 /// addCodeEmitter - This pass should be overridden by the target to add a 379 /// code emitter, if supported. If this is not supported, 'true' should be 380 /// returned. 381 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level, 382 JITCodeEmitter &) { 383 return true; 384 } 385 386 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge 387 /// on this target. User flag overrides. 388 virtual bool getEnableTailMergeDefault() const { return true; } 389}; 390 391} // End llvm namespace 392 393#endif 394