TargetMachine.h revision 96aa78c8c5ef1a5f268539c9edc86569b436d573
1//===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the TargetMachine and LLVMTargetMachine classes. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_TARGETMACHINE_H 15#define LLVM_TARGET_TARGETMACHINE_H 16 17#include "llvm/Target/TargetInstrItineraries.h" 18#include <cassert> 19#include <string> 20 21namespace llvm { 22 23class Target; 24class MCAsmInfo; 25class TargetData; 26class TargetSubtarget; 27class TargetInstrInfo; 28class TargetIntrinsicInfo; 29class TargetJITInfo; 30class TargetLowering; 31class TargetSelectionDAGInfo; 32class TargetFrameLowering; 33class JITCodeEmitter; 34class MCContext; 35class TargetRegisterInfo; 36class PassManagerBase; 37class PassManager; 38class Pass; 39class TargetELFWriterInfo; 40class formatted_raw_ostream; 41 42// Relocation model types. 43namespace Reloc { 44 enum Model { 45 Default, 46 Static, 47 PIC_, // Cannot be named PIC due to collision with -DPIC 48 DynamicNoPIC 49 }; 50} 51 52// Code model types. 53namespace CodeModel { 54 enum Model { 55 Default, 56 Small, 57 Kernel, 58 Medium, 59 Large 60 }; 61} 62 63// Code generation optimization level. 64namespace CodeGenOpt { 65 enum Level { 66 None, // -O0 67 Less, // -O1 68 Default, // -O2, -Os 69 Aggressive // -O3 70 }; 71} 72 73namespace Sched { 74 enum Preference { 75 None, // No preference 76 Latency, // Scheduling for shortest total latency. 77 RegPressure, // Scheduling for lowest register pressure. 78 Hybrid, // Scheduling for both latency and register pressure. 79 ILP // Scheduling for ILP in low register pressure mode. 80 }; 81} 82 83//===----------------------------------------------------------------------===// 84/// 85/// TargetMachine - Primary interface to the complete machine description for 86/// the target machine. All target-specific information should be accessible 87/// through this interface. 88/// 89class TargetMachine { 90 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT 91 void operator=(const TargetMachine &); // DO NOT IMPLEMENT 92protected: // Can only create subclasses. 93 TargetMachine(const Target &); 94 95 /// getSubtargetImpl - virtual method implemented by subclasses that returns 96 /// a reference to that target's TargetSubtarget-derived member variable. 97 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; } 98 99 /// TheTarget - The Target that this machine was created for. 100 const Target &TheTarget; 101 102 /// AsmInfo - Contains target specific asm information. 103 /// 104 const MCAsmInfo *AsmInfo; 105 106 unsigned MCRelaxAll : 1; 107 unsigned MCNoExecStack : 1; 108 unsigned MCUseLoc : 1; 109 110public: 111 virtual ~TargetMachine(); 112 113 const Target &getTarget() const { return TheTarget; } 114 115 // Interfaces to the major aspects of target machine information: 116 // -- Instruction opcode and operand information 117 // -- Pipelines and scheduling information 118 // -- Stack frame information 119 // -- Selection DAG lowering information 120 // 121 virtual const TargetInstrInfo *getInstrInfo() const { return 0; } 122 virtual const TargetFrameLowering *getFrameLowering() const { return 0; } 123 virtual const TargetLowering *getTargetLowering() const { return 0; } 124 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; } 125 virtual const TargetData *getTargetData() const { return 0; } 126 127 /// getMCAsmInfo - Return target specific asm information. 128 /// 129 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; } 130 131 /// getSubtarget - This method returns a pointer to the specified type of 132 /// TargetSubtarget. In debug builds, it verifies that the object being 133 /// returned is of the correct type. 134 template<typename STC> const STC &getSubtarget() const { 135 return *static_cast<const STC*>(getSubtargetImpl()); 136 } 137 138 /// getRegisterInfo - If register information is available, return it. If 139 /// not, return null. This is kept separate from RegInfo until RegInfo has 140 /// details of graph coloring register allocation removed from it. 141 /// 142 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; } 143 144 /// getIntrinsicInfo - If intrinsic information is available, return it. If 145 /// not, return null. 146 /// 147 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; } 148 149 /// getJITInfo - If this target supports a JIT, return information for it, 150 /// otherwise return null. 151 /// 152 virtual TargetJITInfo *getJITInfo() { return 0; } 153 154 /// getInstrItineraryData - Returns instruction itinerary data for the target 155 /// or specific subtarget. 156 /// 157 virtual const InstrItineraryData *getInstrItineraryData() const { 158 return 0; 159 } 160 161 /// getELFWriterInfo - If this target supports an ELF writer, return 162 /// information for it, otherwise return null. 163 /// 164 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; } 165 166 /// hasMCRelaxAll - Check whether all machine code instructions should be 167 /// relaxed. 168 bool hasMCRelaxAll() const { return MCRelaxAll; } 169 170 /// setMCRelaxAll - Set whether all machine code instructions should be 171 /// relaxed. 172 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; } 173 174 /// hasMCNoExecStack - Check whether an executable stack is not needed. 175 bool hasMCNoExecStack() const { return MCNoExecStack; } 176 177 /// setMCNoExecStack - Set whether an executabel stack is not needed. 178 void setMCNoExecStack(bool Value) { MCNoExecStack = Value; } 179 180 /// hasMCUseLoc - Check whether we should use dwarf's .loc directive. 181 bool hasMCUseLoc() const { return MCUseLoc; } 182 183 /// setMCUseLoc - Set whether all we should use dwarf's .loc directive. 184 void setMCUseLoc(bool Value) { MCUseLoc = Value; } 185 186 /// getRelocationModel - Returns the code generation relocation model. The 187 /// choices are static, PIC, and dynamic-no-pic, and target default. 188 static Reloc::Model getRelocationModel(); 189 190 /// setRelocationModel - Sets the code generation relocation model. 191 /// 192 static void setRelocationModel(Reloc::Model Model); 193 194 /// getCodeModel - Returns the code model. The choices are small, kernel, 195 /// medium, large, and target default. 196 static CodeModel::Model getCodeModel(); 197 198 /// setCodeModel - Sets the code model. 199 /// 200 static void setCodeModel(CodeModel::Model Model); 201 202 /// getAsmVerbosityDefault - Returns the default value of asm verbosity. 203 /// 204 static bool getAsmVerbosityDefault(); 205 206 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default 207 /// is false. 208 static void setAsmVerbosityDefault(bool); 209 210 /// getDataSections - Return true if data objects should be emitted into their 211 /// own section, corresponds to -fdata-sections. 212 static bool getDataSections(); 213 214 /// getFunctionSections - Return true if functions should be emitted into 215 /// their own section, corresponding to -ffunction-sections. 216 static bool getFunctionSections(); 217 218 /// setDataSections - Set if the data are emit into separate sections. 219 static void setDataSections(bool); 220 221 /// setFunctionSections - Set if the functions are emit into separate 222 /// sections. 223 static void setFunctionSections(bool); 224 225 /// CodeGenFileType - These enums are meant to be passed into 226 /// addPassesToEmitFile to indicate what type of file to emit, and returned by 227 /// it to indicate what type of file could actually be made. 228 enum CodeGenFileType { 229 CGFT_AssemblyFile, 230 CGFT_ObjectFile, 231 CGFT_Null // Do not emit any output. 232 }; 233 234 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge 235 /// on this target. User flag overrides. 236 virtual bool getEnableTailMergeDefault() const { return true; } 237 238 /// addPassesToEmitFile - Add passes to the specified pass manager to get the 239 /// specified file emitted. Typically this will involve several steps of code 240 /// generation. This method should return true if emission of this file type 241 /// is not supported, or false on success. 242 virtual bool addPassesToEmitFile(PassManagerBase &, 243 formatted_raw_ostream &, 244 CodeGenFileType, 245 CodeGenOpt::Level, 246 bool = true) { 247 return true; 248 } 249 250 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 251 /// get machine code emitted. This uses a JITCodeEmitter object to handle 252 /// actually outputting the machine code and resolving things like the address 253 /// of functions. This method returns true if machine code emission is 254 /// not supported. 255 /// 256 virtual bool addPassesToEmitMachineCode(PassManagerBase &, 257 JITCodeEmitter &, 258 CodeGenOpt::Level, 259 bool = true) { 260 return true; 261 } 262 263 /// addPassesToEmitMC - Add passes to the specified pass manager to get 264 /// machine code emitted with the MCJIT. This method returns true if machine 265 /// code is not supported. It fills the MCContext Ctx pointer which can be 266 /// used to build custom MCStreamer. 267 /// 268 virtual bool addPassesToEmitMC(PassManagerBase &, 269 MCContext *&, 270 CodeGenOpt::Level, 271 bool = true) { 272 return true; 273 } 274}; 275 276/// LLVMTargetMachine - This class describes a target machine that is 277/// implemented with the LLVM target-independent code generator. 278/// 279class LLVMTargetMachine : public TargetMachine { 280 std::string TargetTriple; 281 282protected: // Can only create subclasses. 283 LLVMTargetMachine(const Target &T, const std::string &TargetTriple); 284 285private: 286 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for 287 /// both emitting to assembly files or machine code output. 288 /// 289 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level, 290 bool DisableVerify, MCContext *&OutCtx); 291 292 virtual void setCodeModelForJIT(); 293 virtual void setCodeModelForStatic(); 294 295public: 296 297 const std::string &getTargetTriple() const { return TargetTriple; } 298 299 /// addPassesToEmitFile - Add passes to the specified pass manager to get the 300 /// specified file emitted. Typically this will involve several steps of code 301 /// generation. If OptLevel is None, the code generator should emit code as 302 /// fast as possible, though the generated code may be less efficient. 303 virtual bool addPassesToEmitFile(PassManagerBase &PM, 304 formatted_raw_ostream &Out, 305 CodeGenFileType FileType, 306 CodeGenOpt::Level, 307 bool DisableVerify = true); 308 309 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 310 /// get machine code emitted. This uses a JITCodeEmitter object to handle 311 /// actually outputting the machine code and resolving things like the address 312 /// of functions. This method returns true if machine code emission is 313 /// not supported. 314 /// 315 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM, 316 JITCodeEmitter &MCE, 317 CodeGenOpt::Level, 318 bool DisableVerify = true); 319 320 /// addPassesToEmitMC - Add passes to the specified pass manager to get 321 /// machine code emitted with the MCJIT. This method returns true if machine 322 /// code is not supported. It fills the MCContext Ctx pointer which can be 323 /// used to build custom MCStreamer. 324 /// 325 virtual bool addPassesToEmitMC(PassManagerBase &PM, 326 MCContext *&Ctx, 327 CodeGenOpt::Level OptLevel, 328 bool DisableVerify = true); 329 330 /// Target-Independent Code Generator Pass Configuration Options. 331 332 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM 333 /// passes (which are run just before instruction selector). 334 virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) { 335 return true; 336 } 337 338 /// addInstSelector - This method should install an instruction selector pass, 339 /// which converts from LLVM code to machine instructions. 340 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) { 341 return true; 342 } 343 344 /// addPreRegAlloc - This method may be implemented by targets that want to 345 /// run passes immediately before register allocation. This should return 346 /// true if -print-machineinstrs should print after these passes. 347 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) { 348 return false; 349 } 350 351 /// addPostRegAlloc - This method may be implemented by targets that want 352 /// to run passes after register allocation but before prolog-epilog 353 /// insertion. This should return true if -print-machineinstrs should print 354 /// after these passes. 355 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) { 356 return false; 357 } 358 359 /// addPreSched2 - This method may be implemented by targets that want to 360 /// run passes after prolog-epilog insertion and before the second instruction 361 /// scheduling pass. This should return true if -print-machineinstrs should 362 /// print after these passes. 363 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) { 364 return false; 365 } 366 367 /// addPreEmitPass - This pass may be implemented by targets that want to run 368 /// passes immediately before machine code is emitted. This should return 369 /// true if -print-machineinstrs should print out the code after the passes. 370 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) { 371 return false; 372 } 373 374 375 /// addCodeEmitter - This pass should be overridden by the target to add a 376 /// code emitter, if supported. If this is not supported, 'true' should be 377 /// returned. 378 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level, 379 JITCodeEmitter &) { 380 return true; 381 } 382 383 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge 384 /// on this target. User flag overrides. 385 virtual bool getEnableTailMergeDefault() const { return true; } 386}; 387 388} // End llvm namespace 389 390#endif 391