TargetMachine.h revision e5dafc395656645c3a5d90e7c1b55477800f2ab1 
1//===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the TargetMachine and LLVMTargetMachine classes.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_TARGETMACHINE_H
15#define LLVM_TARGET_TARGETMACHINE_H
16
17#include "llvm/Target/TargetOptions.h"
18#include "llvm/MC/MCCodeGenInfo.h"
19#include "llvm/ADT/StringRef.h"
20#include <cassert>
21#include <string>
22
23namespace llvm {
24
25class InstrItineraryData;
26class JITCodeEmitter;
27class MCAsmInfo;
28class MCCodeGenInfo;
29class MCContext;
30class Pass;
31class PassManager;
32class PassManagerBase;
33class Target;
34class TargetData;
35class TargetELFWriterInfo;
36class TargetFrameLowering;
37class TargetInstrInfo;
38class TargetIntrinsicInfo;
39class TargetJITInfo;
40class TargetLowering;
41class TargetRegisterInfo;
42class TargetSelectionDAGInfo;
43class TargetSubtargetInfo;
44class formatted_raw_ostream;
45class raw_ostream;
46
47//===----------------------------------------------------------------------===//
48///
49/// TargetMachine - Primary interface to the complete machine description for
50/// the target machine.  All target-specific information should be accessible
51/// through this interface.
52///
53class TargetMachine {
54  TargetMachine(const TargetMachine &);   // DO NOT IMPLEMENT
55  void operator=(const TargetMachine &);  // DO NOT IMPLEMENT
56protected: // Can only create subclasses.
57  TargetMachine(const Target &T, StringRef TargetTriple,
58                StringRef CPU, StringRef FS, const TargetOptions &Options);
59
60  /// getSubtargetImpl - virtual method implemented by subclasses that returns
61  /// a reference to that target's TargetSubtargetInfo-derived member variable.
62  virtual const TargetSubtargetInfo *getSubtargetImpl() const { return 0; }
63
64  /// TheTarget - The Target that this machine was created for.
65  const Target &TheTarget;
66
67  /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target
68  /// feature strings the TargetMachine instance is created with.
69  std::string TargetTriple;
70  std::string TargetCPU;
71  std::string TargetFS;
72
73  /// CodeGenInfo - Low level target information such as relocation model.
74  const MCCodeGenInfo *CodeGenInfo;
75
76  /// AsmInfo - Contains target specific asm information.
77  ///
78  const MCAsmInfo *AsmInfo;
79
80  unsigned MCRelaxAll : 1;
81  unsigned MCNoExecStack : 1;
82  unsigned MCSaveTempLabels : 1;
83  unsigned MCUseLoc : 1;
84  unsigned MCUseCFI : 1;
85  unsigned MCUseDwarfDirectory : 1;
86
87public:
88  virtual ~TargetMachine();
89
90  const Target &getTarget() const { return TheTarget; }
91
92  const StringRef getTargetTriple() const { return TargetTriple; }
93  const StringRef getTargetCPU() const { return TargetCPU; }
94  const StringRef getTargetFeatureString() const { return TargetFS; }
95
96  TargetOptions Options;
97
98  // Interfaces to the major aspects of target machine information:
99  // -- Instruction opcode and operand information
100  // -- Pipelines and scheduling information
101  // -- Stack frame information
102  // -- Selection DAG lowering information
103  //
104  virtual const TargetInstrInfo         *getInstrInfo() const { return 0; }
105  virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
106  virtual const TargetLowering    *getTargetLowering() const { return 0; }
107  virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
108  virtual const TargetData             *getTargetData() const { return 0; }
109
110  /// getMCAsmInfo - Return target specific asm information.
111  ///
112  const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
113
114  /// getSubtarget - This method returns a pointer to the specified type of
115  /// TargetSubtargetInfo.  In debug builds, it verifies that the object being
116  /// returned is of the correct type.
117  template<typename STC> const STC &getSubtarget() const {
118    return *static_cast<const STC*>(getSubtargetImpl());
119  }
120
121  /// getRegisterInfo - If register information is available, return it.  If
122  /// not, return null.  This is kept separate from RegInfo until RegInfo has
123  /// details of graph coloring register allocation removed from it.
124  ///
125  virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
126
127  /// getIntrinsicInfo - If intrinsic information is available, return it.  If
128  /// not, return null.
129  ///
130  virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
131
132  /// getJITInfo - If this target supports a JIT, return information for it,
133  /// otherwise return null.
134  ///
135  virtual TargetJITInfo *getJITInfo() { return 0; }
136
137  /// getInstrItineraryData - Returns instruction itinerary data for the target
138  /// or specific subtarget.
139  ///
140  virtual const InstrItineraryData *getInstrItineraryData() const {
141    return 0;
142  }
143
144  /// getELFWriterInfo - If this target supports an ELF writer, return
145  /// information for it, otherwise return null.
146  ///
147  virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
148
149  /// hasMCRelaxAll - Check whether all machine code instructions should be
150  /// relaxed.
151  bool hasMCRelaxAll() const { return MCRelaxAll; }
152
153  /// setMCRelaxAll - Set whether all machine code instructions should be
154  /// relaxed.
155  void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
156
157  /// hasMCSaveTempLabels - Check whether temporary labels will be preserved
158  /// (i.e., not treated as temporary).
159  bool hasMCSaveTempLabels() const { return MCSaveTempLabels; }
160
161  /// setMCSaveTempLabels - Set whether temporary labels will be preserved
162  /// (i.e., not treated as temporary).
163  void setMCSaveTempLabels(bool Value) { MCSaveTempLabels = Value; }
164
165  /// hasMCNoExecStack - Check whether an executable stack is not needed.
166  bool hasMCNoExecStack() const { return MCNoExecStack; }
167
168  /// setMCNoExecStack - Set whether an executabel stack is not needed.
169  void setMCNoExecStack(bool Value) { MCNoExecStack = Value; }
170
171  /// hasMCUseLoc - Check whether we should use dwarf's .loc directive.
172  bool hasMCUseLoc() const { return MCUseLoc; }
173
174  /// setMCUseLoc - Set whether all we should use dwarf's .loc directive.
175  void setMCUseLoc(bool Value) { MCUseLoc = Value; }
176
177  /// hasMCUseCFI - Check whether we should use dwarf's .cfi_* directives.
178  bool hasMCUseCFI() const { return MCUseCFI; }
179
180  /// setMCUseCFI - Set whether all we should use dwarf's .cfi_* directives.
181  void setMCUseCFI(bool Value) { MCUseCFI = Value; }
182
183  /// hasMCUseDwarfDirectory - Check whether we should use .file directives with
184  /// explicit directories.
185  bool hasMCUseDwarfDirectory() const { return MCUseDwarfDirectory; }
186
187  /// setMCUseDwarfDirectory - Set whether all we should use .file directives
188  /// with explicit directories.
189  void setMCUseDwarfDirectory(bool Value) { MCUseDwarfDirectory = Value; }
190
191  /// getRelocationModel - Returns the code generation relocation model. The
192  /// choices are static, PIC, and dynamic-no-pic, and target default.
193  Reloc::Model getRelocationModel() const;
194
195  /// getCodeModel - Returns the code model. The choices are small, kernel,
196  /// medium, large, and target default.
197  CodeModel::Model getCodeModel() const;
198
199  /// getOptLevel - Returns the optimization level: None, Less,
200  /// Default, or Aggressive.
201  CodeGenOpt::Level getOptLevel() const;
202
203  /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
204  ///
205  static bool getAsmVerbosityDefault();
206
207  /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
208  /// is false.
209  static void setAsmVerbosityDefault(bool);
210
211  /// getDataSections - Return true if data objects should be emitted into their
212  /// own section, corresponds to -fdata-sections.
213  static bool getDataSections();
214
215  /// getFunctionSections - Return true if functions should be emitted into
216  /// their own section, corresponding to -ffunction-sections.
217  static bool getFunctionSections();
218
219  /// setDataSections - Set if the data are emit into separate sections.
220  static void setDataSections(bool);
221
222  /// setFunctionSections - Set if the functions are emit into separate
223  /// sections.
224  static void setFunctionSections(bool);
225
226  /// CodeGenFileType - These enums are meant to be passed into
227  /// addPassesToEmitFile to indicate what type of file to emit, and returned by
228  /// it to indicate what type of file could actually be made.
229  enum CodeGenFileType {
230    CGFT_AssemblyFile,
231    CGFT_ObjectFile,
232    CGFT_Null         // Do not emit any output.
233  };
234
235  /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
236  /// on this target.  User flag overrides.
237  virtual bool getEnableTailMergeDefault() const { return true; }
238
239  /// addPassesToEmitFile - Add passes to the specified pass manager to get the
240  /// specified file emitted.  Typically this will involve several steps of code
241  /// generation.  This method should return true if emission of this file type
242  /// is not supported, or false on success.
243  virtual bool addPassesToEmitFile(PassManagerBase &,
244                                   formatted_raw_ostream &,
245                                   CodeGenFileType,
246                                   bool /*DisableVerify*/ = true) {
247    return true;
248  }
249
250  /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
251  /// get machine code emitted.  This uses a JITCodeEmitter object to handle
252  /// actually outputting the machine code and resolving things like the address
253  /// of functions.  This method returns true if machine code emission is
254  /// not supported.
255  ///
256  virtual bool addPassesToEmitMachineCode(PassManagerBase &,
257                                          JITCodeEmitter &,
258                                          bool /*DisableVerify*/ = true) {
259    return true;
260  }
261
262  /// addPassesToEmitMC - Add passes to the specified pass manager to get
263  /// machine code emitted with the MCJIT. This method returns true if machine
264  /// code is not supported. It fills the MCContext Ctx pointer which can be
265  /// used to build custom MCStreamer.
266  ///
267  virtual bool addPassesToEmitMC(PassManagerBase &,
268                                 MCContext *&,
269                                 raw_ostream &,
270                                 bool /*DisableVerify*/ = true) {
271    return true;
272  }
273};
274
275/// LLVMTargetMachine - This class describes a target machine that is
276/// implemented with the LLVM target-independent code generator.
277///
278class LLVMTargetMachine : public TargetMachine {
279protected: // Can only create subclasses.
280  LLVMTargetMachine(const Target &T, StringRef TargetTriple,
281                    StringRef CPU, StringRef FS, TargetOptions Options,
282                    Reloc::Model RM, CodeModel::Model CM,
283                    CodeGenOpt::Level OL);
284
285  /// printNoVerify - Add a pass to dump the machine function, if debugging is
286  /// enabled.
287  ///
288  void printNoVerify(PassManagerBase &PM, const char *Banner) const;
289
290  /// printAndVerify - Add a pass to dump then verify the machine function, if
291  /// those steps are enabled.
292  ///
293  void printAndVerify(PassManagerBase &PM, const char *Banner) const;
294
295private:
296  /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
297  /// both emitting to assembly files or machine code output.
298  ///
299  bool addCommonCodeGenPasses(PassManagerBase &,
300                              bool DisableVerify, MCContext *&OutCtx);
301
302public:
303  /// addPassesToEmitFile - Add passes to the specified pass manager to get the
304  /// specified file emitted.  Typically this will involve several steps of code
305  /// generation.
306  virtual bool addPassesToEmitFile(PassManagerBase &PM,
307                                   formatted_raw_ostream &Out,
308                                   CodeGenFileType FileType,
309                                   bool DisableVerify = true);
310
311  /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
312  /// get machine code emitted.  This uses a JITCodeEmitter object to handle
313  /// actually outputting the machine code and resolving things like the address
314  /// of functions.  This method returns true if machine code emission is
315  /// not supported.
316  ///
317  virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
318                                          JITCodeEmitter &MCE,
319                                          bool DisableVerify = true);
320
321  /// addPassesToEmitMC - Add passes to the specified pass manager to get
322  /// machine code emitted with the MCJIT. This method returns true if machine
323  /// code is not supported. It fills the MCContext Ctx pointer which can be
324  /// used to build custom MCStreamer.
325  ///
326  virtual bool addPassesToEmitMC(PassManagerBase &PM,
327                                 MCContext *&Ctx,
328                                 raw_ostream &OS,
329                                 bool DisableVerify = true);
330
331  /// Target-Independent Code Generator Pass Configuration Options.
332
333  /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
334  /// passes (which are run just before instruction selector).
335  virtual bool addPreISel(PassManagerBase &) {
336    return true;
337  }
338
339  /// addInstSelector - This method should install an instruction selector pass,
340  /// which converts from LLVM code to machine instructions.
341  virtual bool addInstSelector(PassManagerBase &) {
342    return true;
343  }
344
345  /// addPreRegAlloc - This method may be implemented by targets that want to
346  /// run passes immediately before register allocation. This should return
347  /// true if -print-machineinstrs should print after these passes.
348  virtual bool addPreRegAlloc(PassManagerBase &) {
349    return false;
350  }
351
352  /// addPostRegAlloc - This method may be implemented by targets that want
353  /// to run passes after register allocation but before prolog-epilog
354  /// insertion.  This should return true if -print-machineinstrs should print
355  /// after these passes.
356  virtual bool addPostRegAlloc(PassManagerBase &) {
357    return false;
358  }
359
360  /// addPreSched2 - This method may be implemented by targets that want to
361  /// run passes after prolog-epilog insertion and before the second instruction
362  /// scheduling pass.  This should return true if -print-machineinstrs should
363  /// print after these passes.
364  virtual bool addPreSched2(PassManagerBase &) {
365    return false;
366  }
367
368  /// addPreEmitPass - This pass may be implemented by targets that want to run
369  /// passes immediately before machine code is emitted.  This should return
370  /// true if -print-machineinstrs should print out the code after the passes.
371  virtual bool addPreEmitPass(PassManagerBase &) {
372    return false;
373  }
374
375
376  /// addCodeEmitter - This pass should be overridden by the target to add a
377  /// code emitter, if supported.  If this is not supported, 'true' should be
378  /// returned.
379  virtual bool addCodeEmitter(PassManagerBase &,
380                              JITCodeEmitter &) {
381    return true;
382  }
383
384  /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
385  /// on this target.  User flag overrides.
386  virtual bool getEnableTailMergeDefault() const { return true; }
387};
388
389} // End llvm namespace
390
391#endif
392