TargetSchedule.td revision 027fdbe3ba6762b9867c6f891d64f76b7d6a4557 
1//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10// This file defines the target-independent scheduling interfaces which should
11// be implemented by each target which is using TableGen based scheduling.
12//
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// Processor functional unit - These values represent the function units
17// available across all chip sets for the target.  Eg., IntUnit, FPUnit, ...
18// These may be independent values for each chip set or may be shared across
19// all chip sets of the target.  Each functional unit is treated as a resource
20// during scheduling and has an affect instruction order based on availability
21// during a time interval.
22//  
23class FuncUnit;
24
25//===----------------------------------------------------------------------===//
26// Instruction stage - These values represent a step in the execution of an
27// instruction.  The latency represents the number of discrete time slots used
28// need to complete the stage.  Units represent the choice of functional units
29// that can be used to complete the stage.  Eg. IntUnit1, IntUnit2.
30//
31class InstrStage<int cycles, list<FuncUnit> units> {
32  int Cycles          = cycles;       // length of stage in machine cycles
33  list<FuncUnit> Units = units;       // choice of functional units
34}
35
36//===----------------------------------------------------------------------===//
37// Instruction itinerary - An itinerary represents a sequential series of steps
38// required to complete an instruction.  Itineraries are represented as lists of
39// instruction stages.
40//
41
42//===----------------------------------------------------------------------===//
43// Instruction itinerary classes - These values represent 'named' instruction
44// itinerary.  Using named itineraries simplifies managing groups of
45// instructions across chip sets.  An instruction uses the same itinerary class
46// across all chip sets.  Thus a new chip set can be added without modifying
47// instruction information.
48//
49class InstrItinClass;
50def NoItinerary : InstrItinClass;
51
52//===----------------------------------------------------------------------===//
53// Instruction itinerary data - These values provide a runtime map of an 
54// instruction itinerary class (name) to it's itinerary data.
55//
56class InstrItinData<InstrItinClass Class, list<InstrStage> stages> {
57  InstrItinClass TheClass = Class;
58  list<InstrStage> Stages = stages;
59}
60
61//===----------------------------------------------------------------------===//
62// Processor itineraries - These values represent the set of all itinerary
63// classes for a given chip set.
64//
65class ProcessorItineraries<list<InstrItinData> iid> {
66  list<InstrItinData> IID = iid;
67}
68
69// NoItineraries - A marker that can be used by processors without schedule
70// info.
71def NoItineraries : ProcessorItineraries<[]>;
72
73