TargetSchedule.td revision 63d66eed16a6ee4e838f2f7a4c8299def0722c20
1//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent scheduling interfaces which should 11// be implemented by each target which is using TableGen based scheduling. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Processor functional unit - These values represent the function units 17// available across all chip sets for the target. Eg., IntUnit, FPUnit, ... 18// These may be independent values for each chip set or may be shared across 19// all chip sets of the target. Each functional unit is treated as a resource 20// during scheduling and has an affect instruction order based on availability 21// during a time interval. 22// 23class FuncUnit; 24 25//===----------------------------------------------------------------------===// 26// Pipeline bypass / forwarding - These values specifies the symbolic names of 27// pipeline bypasses which can be used to forward results of instructions 28// that are forwarded to uses. 29class Bypass; 30 31def NoBypass : Bypass; 32 33class ReservationKind<bits<1> val> { 34 int Value = val; 35} 36 37def Required : ReservationKind<0>; 38def Reserved : ReservationKind<1>; 39 40//===----------------------------------------------------------------------===// 41// Instruction stage - These values represent a non-pipelined step in 42// the execution of an instruction. Cycles represents the number of 43// discrete time slots needed to complete the stage. Units represent 44// the choice of functional units that can be used to complete the 45// stage. Eg. IntUnit1, IntUnit2. NextCycles indicates how many 46// cycles should elapse from the start of this stage to the start of 47// the next stage in the itinerary. For example: 48// 49// A stage is specified in one of two ways: 50// 51// InstrStage<1, [FU_x, FU_y]> - TimeInc defaults to Cycles 52// InstrStage<1, [FU_x, FU_y], 0> - TimeInc explicit 53// 54 55class InstrStage<int cycles, list<FuncUnit> units, 56 int timeinc = -1, 57 ReservationKind kind = Required> { 58 int Cycles = cycles; // length of stage in machine cycles 59 list<FuncUnit> Units = units; // choice of functional units 60 int TimeInc = timeinc; // cycles till start of next stage 61 int Kind = kind.Value; // kind of FU reservation 62} 63 64//===----------------------------------------------------------------------===// 65// Instruction itinerary - An itinerary represents a sequential series of steps 66// required to complete an instruction. Itineraries are represented as lists of 67// instruction stages. 68// 69 70//===----------------------------------------------------------------------===// 71// Instruction itinerary classes - These values represent 'named' instruction 72// itinerary. Using named itineraries simplifies managing groups of 73// instructions across chip sets. An instruction uses the same itinerary class 74// across all chip sets. Thus a new chip set can be added without modifying 75// instruction information. 76// 77// NumMicroOps represents the number of micro-operations that each instruction 78// in the class are decoded to. If the number is zero, then it means the 79// instruction can decode into variable number of micro-ops and it must be 80// determined dynamically. 81// 82class InstrItinClass<int ops = 1> { 83 int NumMicroOps = ops; 84} 85def NoItinerary : InstrItinClass; 86 87//===----------------------------------------------------------------------===// 88// Instruction itinerary data - These values provide a runtime map of an 89// instruction itinerary class (name) to its itinerary data. 90// 91class InstrItinData<InstrItinClass Class, list<InstrStage> stages, 92 list<int> operandcycles = [], 93 list<Bypass> bypasses = []> { 94 InstrItinClass TheClass = Class; 95 list<InstrStage> Stages = stages; 96 list<int> OperandCycles = operandcycles; 97 list<Bypass> Bypasses = bypasses; 98} 99 100//===----------------------------------------------------------------------===// 101// Processor itineraries - These values represent the set of all itinerary 102// classes for a given chip set. 103// 104class ProcessorItineraries<list<FuncUnit> fu, list<Bypass> bp, 105 list<InstrItinData> iid> { 106 list<FuncUnit> FU = fu; 107 list<Bypass> BP = bp; 108 list<InstrItinData> IID = iid; 109} 110 111// NoItineraries - A marker that can be used by processors without schedule 112// info. 113def NoItineraries : ProcessorItineraries<[], [], []>; 114 115