TargetSchedule.td revision fac8541dd40e01aa2b52962516f9ae67c99720cc 
1//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10// This file defines the target-independent scheduling interfaces which should
11// be implemented by each target which is using TableGen based scheduling.
12//
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// Processor functional unit - These values represent the function units
17// available across all chip sets for the target.  Eg., IntUnit, FPUnit, ...
18// These may be independent values for each chip set or may be shared across
19// all chip sets of the target.  Each functional unit is treated as a resource
20// during scheduling and has an affect instruction order based on availability
21// during a time interval.
22//  
23class FuncUnit;
24
25//===----------------------------------------------------------------------===//
26// Instruction stage - These values represent a non-pipelined step in
27// the execution of an instruction.  Cycles represents the number of
28// discrete time slots needed to complete the stage.  Units represent
29// the choice of functional units that can be used to complete the
30// stage.  Eg. IntUnit1, IntUnit2. NextCycles indicates how many
31// cycles should elapse from the start of this stage to the start of
32// the next stage in the itinerary.  For example:
33//
34// A stage is specified in one of two ways:
35//
36//   InstrStage<1, [FU_x, FU_y]>     - TimeInc defaults to Cycles
37//   InstrStage<1, [FU_x, FU_y], 0>  - TimeInc explicit
38//
39class InstrStage<int cycles, list<FuncUnit> units, int timeinc = -1> {
40  int Cycles          = cycles;       // length of stage in machine cycles
41  list<FuncUnit> Units = units;       // choice of functional units
42  int TimeInc         = timeinc;      // cycles till start of next stage
43}
44
45//===----------------------------------------------------------------------===//
46// Instruction itinerary - An itinerary represents a sequential series of steps
47// required to complete an instruction.  Itineraries are represented as lists of
48// instruction stages.
49//
50
51//===----------------------------------------------------------------------===//
52// Instruction itinerary classes - These values represent 'named' instruction
53// itinerary.  Using named itineraries simplifies managing groups of
54// instructions across chip sets.  An instruction uses the same itinerary class
55// across all chip sets.  Thus a new chip set can be added without modifying
56// instruction information.
57//
58class InstrItinClass;
59def NoItinerary : InstrItinClass;
60
61//===----------------------------------------------------------------------===//
62// Instruction itinerary data - These values provide a runtime map of an 
63// instruction itinerary class (name) to it's itinerary data.
64//
65class InstrItinData<InstrItinClass Class, list<InstrStage> stages,
66                    list<int> operandcycles = []> {
67  InstrItinClass TheClass = Class;
68  list<InstrStage> Stages = stages;
69  list<int> OperandCycles = operandcycles;
70}
71
72//===----------------------------------------------------------------------===//
73// Processor itineraries - These values represent the set of all itinerary
74// classes for a given chip set.
75//
76class ProcessorItineraries<list<InstrItinData> iid> {
77  list<InstrItinData> IID = iid;
78}
79
80// NoItineraries - A marker that can be used by processors without schedule
81// info.
82def NoItineraries : ProcessorItineraries<[]>;
83
84