TargetSelectionDAG.td revision 19fdc268c316b3b0bdcb2b558449819f4f402d6a
1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces used by SelectionDAG 11// instruction selection generators. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Selection DAG Type Constraint definitions. 17// 18// Note that the semantics of these constraints are hard coded into tblgen. To 19// modify or add constraints, you have to hack tblgen. 20// 21 22class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24} 25 26// SDTCisVT - The specified operand has exactly this VT. 27class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29} 30 31class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33// SDTCisInt - The specified operand has integer type. 34class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36// SDTCisFP - The specified operand has floating-point type. 37class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39// SDTCisVec - The specified operand has a vector type. 40class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42// SDTCisSameAs - The two specified operands have identical types. 43class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45} 46 47// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48// smaller than the 'Other' operand. 49class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51} 52 53class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55} 56 57/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58/// type as the element type of OtherOp, which is a vector type. 59class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62} 63 64/// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 65/// with length less that of OtherOp, which is a vector type. 66class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 67 : SDTypeConstraint<ThisOp> { 68 int OtherOpNum = OtherOp; 69} 70 71//===----------------------------------------------------------------------===// 72// Selection DAG Type Profile definitions. 73// 74// These use the constraints defined above to describe the type requirements of 75// the various nodes. These are not hard coded into tblgen, allowing targets to 76// add their own if needed. 77// 78 79// SDTypeProfile - This profile describes the type requirements of a Selection 80// DAG node. 81class SDTypeProfile<int numresults, int numoperands, 82 list<SDTypeConstraint> constraints> { 83 int NumResults = numresults; 84 int NumOperands = numoperands; 85 list<SDTypeConstraint> Constraints = constraints; 86} 87 88// Builtin profiles. 89def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 90def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 91def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 92def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 93def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 94def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 95 96def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 97 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 98]>; 99def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 100 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 101]>; 102def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 103 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 104]>; 105 106def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 107 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 108]>; 109def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 110 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 111]>; 112def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 114]>; 115def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 116 SDTCisSameAs<0, 1>, SDTCisInt<0> 117]>; 118def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 119 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 120]>; 121def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 122 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 123]>; 124def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 125 SDTCisSameAs<0, 1>, SDTCisFP<0> 126]>; 127def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 128 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 129]>; 130def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 131 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 132]>; 133def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 134 SDTCisFP<0>, SDTCisInt<1> 135]>; 136def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 137 SDTCisInt<0>, SDTCisFP<1> 138]>; 139def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 140 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 141 SDTCisVTSmallerThanOp<2, 1> 142]>; 143 144def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 145 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 146]>; 147 148def SDTSelect : SDTypeProfile<1, 3, [ // select 149 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 150]>; 151 152def SDTVSelect : SDTypeProfile<1, 3, [ // vselect 153 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 154]>; 155 156def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 157 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 158 SDTCisVT<5, OtherVT> 159]>; 160 161def SDTBr : SDTypeProfile<0, 1, [ // br 162 SDTCisVT<0, OtherVT> 163]>; 164 165def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 166 SDTCisInt<0>, SDTCisVT<1, OtherVT> 167]>; 168 169def SDTBrind : SDTypeProfile<0, 1, [ // brind 170 SDTCisPtrTy<0> 171]>; 172 173def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 174 175def SDTLoad : SDTypeProfile<1, 1, [ // load 176 SDTCisPtrTy<1> 177]>; 178 179def SDTStore : SDTypeProfile<0, 2, [ // store 180 SDTCisPtrTy<1> 181]>; 182 183def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 184 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 185]>; 186 187def SDTVecShuffle : SDTypeProfile<1, 2, [ 188 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 189]>; 190def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 191 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 192]>; 193def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 194 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 195]>; 196 197def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 198 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 199]>; 200def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 201 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 202]>; 203 204def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch 205 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> 206]>; 207 208def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier 209 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 210 SDTCisInt<0> 211]>; 212def SDTAtomicFence : SDTypeProfile<0, 2, [ 213 SDTCisSameAs<0,1>, SDTCisPtrTy<0> 214]>; 215def SDTAtomic3 : SDTypeProfile<1, 3, [ 216 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 217]>; 218def SDTAtomic2 : SDTypeProfile<1, 2, [ 219 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 220]>; 221def SDTAtomicStore : SDTypeProfile<0, 2, [ 222 SDTCisPtrTy<0>, SDTCisInt<1> 223]>; 224def SDTAtomicLoad : SDTypeProfile<1, 1, [ 225 SDTCisInt<0>, SDTCisPtrTy<1> 226]>; 227 228def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 229 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 230]>; 231 232class SDCallSeqStart<list<SDTypeConstraint> constraints> : 233 SDTypeProfile<0, 1, constraints>; 234class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 235 SDTypeProfile<0, 2, constraints>; 236 237//===----------------------------------------------------------------------===// 238// Selection DAG Node Properties. 239// 240// Note: These are hard coded into tblgen. 241// 242class SDNodeProperty; 243def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 244def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 245def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 246def SDNPOutGlue : SDNodeProperty; // Write a flag result 247def SDNPInGlue : SDNodeProperty; // Read a flag operand 248def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand 249def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 250def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 251def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 252def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 253def SDNPVariadic : SDNodeProperty; // Node has variable arguments. 254def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match 255def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent 256 257//===----------------------------------------------------------------------===// 258// Selection DAG Pattern Operations 259class SDPatternOperator; 260 261//===----------------------------------------------------------------------===// 262// Selection DAG Node definitions. 263// 264class SDNode<string opcode, SDTypeProfile typeprof, 265 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 266 : SDPatternOperator { 267 string Opcode = opcode; 268 string SDClass = sdclass; 269 list<SDNodeProperty> Properties = props; 270 SDTypeProfile TypeProfile = typeprof; 271} 272 273// Special TableGen-recognized dag nodes 274def set; 275def implicit; 276def node; 277def srcvalue; 278 279def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 280def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 281def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 282def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 283def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 284def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 285def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 286def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 287 "GlobalAddressSDNode">; 288def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 289 "GlobalAddressSDNode">; 290def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 291 "GlobalAddressSDNode">; 292def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 293 "GlobalAddressSDNode">; 294def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 295 "ConstantPoolSDNode">; 296def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 297 "ConstantPoolSDNode">; 298def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 299 "JumpTableSDNode">; 300def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 301 "JumpTableSDNode">; 302def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 303 "FrameIndexSDNode">; 304def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 305 "FrameIndexSDNode">; 306def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 307 "ExternalSymbolSDNode">; 308def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 309 "ExternalSymbolSDNode">; 310def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 311 "BlockAddressSDNode">; 312def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 313 "BlockAddressSDNode">; 314 315def add : SDNode<"ISD::ADD" , SDTIntBinOp , 316 [SDNPCommutative, SDNPAssociative]>; 317def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 318def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 319 [SDNPCommutative, SDNPAssociative]>; 320def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 321def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 322def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 323def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 324def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 325def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 326def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 327def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 328def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 329def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 330def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 331def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 332def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 333def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 334def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 335def and : SDNode<"ISD::AND" , SDTIntBinOp, 336 [SDNPCommutative, SDNPAssociative]>; 337def or : SDNode<"ISD::OR" , SDTIntBinOp, 338 [SDNPCommutative, SDNPAssociative]>; 339def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 340 [SDNPCommutative, SDNPAssociative]>; 341def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 342 [SDNPCommutative, SDNPOutGlue]>; 343def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 344 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 345def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 346 [SDNPOutGlue]>; 347def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 348 [SDNPOutGlue, SDNPInGlue]>; 349 350def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 351def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 352def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 353def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 354def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 355def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>; 356def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>; 357def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 358def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 359def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 360def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 361def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 362def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 363def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 364 365 366def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 367def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 368def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 369def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 370def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 371def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>; 372def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 373def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; 374def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 375def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 376def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 377def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 378def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 379def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>; 380def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 381def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 382def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 383def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 384def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 385def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 386def frnd : SDNode<"ISD::FROUND" , SDTFPUnaryOp>; 387 388def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 389def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 390def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 391 392def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 393def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 394def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 395def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 396def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>; 397def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>; 398 399def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 400def select : SDNode<"ISD::SELECT" , SDTSelect>; 401def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>; 402def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 403 404def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 405def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 406def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 407def trap : SDNode<"ISD::TRAP" , SDTNone, 408 [SDNPHasChain, SDNPSideEffect]>; 409def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone, 410 [SDNPHasChain, SDNPSideEffect]>; 411 412def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 413 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 414 SDNPMemOperand]>; 415 416def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf, 417 [SDNPHasChain, SDNPSideEffect]>; 418 419def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, 420 [SDNPHasChain, SDNPSideEffect]>; 421 422def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 423 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 424def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 425 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 426def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 427 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 428def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 429 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 430def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 431 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 432def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 433 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 434def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 435 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 436def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 437 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 438def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 439 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 440def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 441 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 442def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 443 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 444def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 445 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 446def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, 447 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 448def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, 449 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 450 451// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 452// and truncst (see below). 453def ld : SDNode<"ISD::LOAD" , SDTLoad, 454 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 455def st : SDNode<"ISD::STORE" , SDTStore, 456 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 457def ist : SDNode<"ISD::STORE" , SDTIStore, 458 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 459 460def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 461def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 462def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 463 []>; 464def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 465 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 466def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 467 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 468def concat_vectors : SDNode<"ISD::CONCAT_VECTORS", 469 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1, 2>]>,[]>; 470 471// This operator does not do subvector type checking. The ARM 472// backend, at least, needs it. 473def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 474 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 475 []>; 476 477// This operator does subvector type checking. 478def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 479def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 480 481// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 482// these internally. Don't reference these directly. 483def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 484 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 485 [SDNPHasChain]>; 486def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 487 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 488 [SDNPHasChain]>; 489def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 490 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 491 492// Do not use cvt directly. Use cvt forms below 493def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 494 495//===----------------------------------------------------------------------===// 496// Selection DAG Condition Codes 497 498class CondCode; // ISD::CondCode enums 499def SETOEQ : CondCode; def SETOGT : CondCode; 500def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 501def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 502def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 503def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 504 505def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 506def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 507 508 509//===----------------------------------------------------------------------===// 510// Selection DAG Node Transformation Functions. 511// 512// This mechanism allows targets to manipulate nodes in the output DAG once a 513// match has been formed. This is typically used to manipulate immediate 514// values. 515// 516class SDNodeXForm<SDNode opc, code xformFunction> { 517 SDNode Opcode = opc; 518 code XFormFunction = xformFunction; 519} 520 521def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 522 523//===----------------------------------------------------------------------===// 524// PatPred Subclasses. 525// 526// These allow specifying different sorts of predicates that control whether a 527// node is matched. 528// 529class PatPred; 530 531class CodePatPred<code predicate> : PatPred { 532 code PredicateCode = predicate; 533} 534 535 536//===----------------------------------------------------------------------===// 537// Selection DAG Pattern Fragments. 538// 539// Pattern fragments are reusable chunks of dags that match specific things. 540// They can take arguments and have C++ predicates that control whether they 541// match. They are intended to make the patterns for common instructions more 542// compact and readable. 543// 544 545/// PatFrag - Represents a pattern fragment. This can match something on the 546/// DAG, from a single node to multiple nested other fragments. 547/// 548class PatFrag<dag ops, dag frag, code pred = [{}], 549 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 550 dag Operands = ops; 551 dag Fragment = frag; 552 code PredicateCode = pred; 553 code ImmediateCode = [{}]; 554 SDNodeXForm OperandTransform = xform; 555} 556 557// PatLeaf's are pattern fragments that have no operands. This is just a helper 558// to define immediates and other common things concisely. 559class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 560 : PatFrag<(ops), frag, pred, xform>; 561 562 563// ImmLeaf is a pattern fragment with a constraint on the immediate. The 564// constraint is a function that is run on the immediate (always with the value 565// sign extended out to an int64_t) as Imm. For example: 566// 567// def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>; 568// 569// this is a more convenient form to match 'imm' nodes in than PatLeaf and also 570// is preferred over using PatLeaf because it allows the code generator to 571// reason more about the constraint. 572// 573// If FastIsel should ignore all instructions that have an operand of this type, 574// the FastIselShouldIgnore flag can be set. This is an optimization to reduce 575// the code size of the generated fast instruction selector. 576class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 577 : PatFrag<(ops), (vt imm), [{}], xform> { 578 let ImmediateCode = pred; 579 bit FastIselShouldIgnore = 0; 580} 581 582 583// Leaf fragments. 584 585def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 586def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 587 588def immAllOnesV: PatLeaf<(build_vector), [{ 589 return ISD::isBuildVectorAllOnes(N); 590}]>; 591def immAllZerosV: PatLeaf<(build_vector), [{ 592 return ISD::isBuildVectorAllZeros(N); 593}]>; 594 595 596 597// Other helper fragments. 598def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 599def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 600def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 601 602// null_frag - The null pattern operator is used in multiclass instantiations 603// which accept an SDPatternOperator for use in matching patterns for internal 604// definitions. When expanding a pattern, if the null fragment is referenced 605// in the expansion, the pattern is discarded and it is as-if '[]' had been 606// specified. This allows multiclasses to have the isel patterns be optional. 607def null_frag : SDPatternOperator; 608 609// load fragments. 610def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 611 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 612}]>; 613def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 614 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 615}]>; 616 617// extending load fragments. 618def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 619 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 620}]>; 621def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 622 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 623}]>; 624def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 625 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 626}]>; 627 628def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 629 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 630}]>; 631def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 632 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 633}]>; 634def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 635 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 636}]>; 637def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 638 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 639}]>; 640def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 641 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 642}]>; 643def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 644 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 645}]>; 646 647def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 648 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 649}]>; 650def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 651 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 652}]>; 653def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 654 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 655}]>; 656def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 657 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 658}]>; 659 660def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 661 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 662}]>; 663def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 664 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 665}]>; 666def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 667 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 668}]>; 669def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 670 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 671}]>; 672 673def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 674 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 675}]>; 676def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 677 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 678}]>; 679def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 680 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 681}]>; 682def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 683 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 684}]>; 685def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 686 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32; 687}]>; 688def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 689 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64; 690}]>; 691 692def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 693 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 694}]>; 695def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 696 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 697}]>; 698def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 699 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 700}]>; 701def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 702 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 703}]>; 704 705def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 706 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 707}]>; 708def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 709 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 710}]>; 711def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 712 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 713}]>; 714def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 715 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 716}]>; 717 718// store fragments. 719def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 720 (st node:$val, node:$ptr), [{ 721 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 722}]>; 723def store : PatFrag<(ops node:$val, node:$ptr), 724 (unindexedstore node:$val, node:$ptr), [{ 725 return !cast<StoreSDNode>(N)->isTruncatingStore(); 726}]>; 727 728// truncstore fragments. 729def truncstore : PatFrag<(ops node:$val, node:$ptr), 730 (unindexedstore node:$val, node:$ptr), [{ 731 return cast<StoreSDNode>(N)->isTruncatingStore(); 732}]>; 733def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 734 (truncstore node:$val, node:$ptr), [{ 735 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 736}]>; 737def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 738 (truncstore node:$val, node:$ptr), [{ 739 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 740}]>; 741def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 742 (truncstore node:$val, node:$ptr), [{ 743 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 744}]>; 745def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 746 (truncstore node:$val, node:$ptr), [{ 747 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 748}]>; 749def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 750 (truncstore node:$val, node:$ptr), [{ 751 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 752}]>; 753 754// indexed store fragments. 755def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 756 (ist node:$val, node:$base, node:$offset), [{ 757 return !cast<StoreSDNode>(N)->isTruncatingStore(); 758}]>; 759 760def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 761 (istore node:$val, node:$base, node:$offset), [{ 762 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 763 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 764}]>; 765 766def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 767 (ist node:$val, node:$base, node:$offset), [{ 768 return cast<StoreSDNode>(N)->isTruncatingStore(); 769}]>; 770def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 771 (itruncstore node:$val, node:$base, node:$offset), [{ 772 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 773 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 774}]>; 775def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 776 (pre_truncst node:$val, node:$base, node:$offset), [{ 777 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 778}]>; 779def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 780 (pre_truncst node:$val, node:$base, node:$offset), [{ 781 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 782}]>; 783def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 784 (pre_truncst node:$val, node:$base, node:$offset), [{ 785 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 786}]>; 787def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 788 (pre_truncst node:$val, node:$base, node:$offset), [{ 789 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 790}]>; 791def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 792 (pre_truncst node:$val, node:$base, node:$offset), [{ 793 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 794}]>; 795 796def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 797 (istore node:$val, node:$ptr, node:$offset), [{ 798 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 799 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 800}]>; 801 802def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 803 (itruncstore node:$val, node:$base, node:$offset), [{ 804 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 805 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 806}]>; 807def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 808 (post_truncst node:$val, node:$base, node:$offset), [{ 809 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 810}]>; 811def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 812 (post_truncst node:$val, node:$base, node:$offset), [{ 813 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 814}]>; 815def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 816 (post_truncst node:$val, node:$base, node:$offset), [{ 817 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 818}]>; 819def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 820 (post_truncst node:$val, node:$base, node:$offset), [{ 821 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 822}]>; 823def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 824 (post_truncst node:$val, node:$base, node:$offset), [{ 825 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 826}]>; 827 828// setcc convenience fragments. 829def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 830 (setcc node:$lhs, node:$rhs, SETOEQ)>; 831def setogt : PatFrag<(ops node:$lhs, node:$rhs), 832 (setcc node:$lhs, node:$rhs, SETOGT)>; 833def setoge : PatFrag<(ops node:$lhs, node:$rhs), 834 (setcc node:$lhs, node:$rhs, SETOGE)>; 835def setolt : PatFrag<(ops node:$lhs, node:$rhs), 836 (setcc node:$lhs, node:$rhs, SETOLT)>; 837def setole : PatFrag<(ops node:$lhs, node:$rhs), 838 (setcc node:$lhs, node:$rhs, SETOLE)>; 839def setone : PatFrag<(ops node:$lhs, node:$rhs), 840 (setcc node:$lhs, node:$rhs, SETONE)>; 841def seto : PatFrag<(ops node:$lhs, node:$rhs), 842 (setcc node:$lhs, node:$rhs, SETO)>; 843def setuo : PatFrag<(ops node:$lhs, node:$rhs), 844 (setcc node:$lhs, node:$rhs, SETUO)>; 845def setueq : PatFrag<(ops node:$lhs, node:$rhs), 846 (setcc node:$lhs, node:$rhs, SETUEQ)>; 847def setugt : PatFrag<(ops node:$lhs, node:$rhs), 848 (setcc node:$lhs, node:$rhs, SETUGT)>; 849def setuge : PatFrag<(ops node:$lhs, node:$rhs), 850 (setcc node:$lhs, node:$rhs, SETUGE)>; 851def setult : PatFrag<(ops node:$lhs, node:$rhs), 852 (setcc node:$lhs, node:$rhs, SETULT)>; 853def setule : PatFrag<(ops node:$lhs, node:$rhs), 854 (setcc node:$lhs, node:$rhs, SETULE)>; 855def setune : PatFrag<(ops node:$lhs, node:$rhs), 856 (setcc node:$lhs, node:$rhs, SETUNE)>; 857def seteq : PatFrag<(ops node:$lhs, node:$rhs), 858 (setcc node:$lhs, node:$rhs, SETEQ)>; 859def setgt : PatFrag<(ops node:$lhs, node:$rhs), 860 (setcc node:$lhs, node:$rhs, SETGT)>; 861def setge : PatFrag<(ops node:$lhs, node:$rhs), 862 (setcc node:$lhs, node:$rhs, SETGE)>; 863def setlt : PatFrag<(ops node:$lhs, node:$rhs), 864 (setcc node:$lhs, node:$rhs, SETLT)>; 865def setle : PatFrag<(ops node:$lhs, node:$rhs), 866 (setcc node:$lhs, node:$rhs, SETLE)>; 867def setne : PatFrag<(ops node:$lhs, node:$rhs), 868 (setcc node:$lhs, node:$rhs, SETNE)>; 869 870def atomic_cmp_swap_8 : 871 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 872 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 873 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 874}]>; 875def atomic_cmp_swap_16 : 876 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 877 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 878 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 879}]>; 880def atomic_cmp_swap_32 : 881 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 882 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 883 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 884}]>; 885def atomic_cmp_swap_64 : 886 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 887 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 888 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 889}]>; 890 891multiclass binary_atomic_op<SDNode atomic_op> { 892 def _8 : PatFrag<(ops node:$ptr, node:$val), 893 (atomic_op node:$ptr, node:$val), [{ 894 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 895 }]>; 896 def _16 : PatFrag<(ops node:$ptr, node:$val), 897 (atomic_op node:$ptr, node:$val), [{ 898 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 899 }]>; 900 def _32 : PatFrag<(ops node:$ptr, node:$val), 901 (atomic_op node:$ptr, node:$val), [{ 902 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 903 }]>; 904 def _64 : PatFrag<(ops node:$ptr, node:$val), 905 (atomic_op node:$ptr, node:$val), [{ 906 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 907 }]>; 908} 909 910defm atomic_load_add : binary_atomic_op<atomic_load_add>; 911defm atomic_swap : binary_atomic_op<atomic_swap>; 912defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 913defm atomic_load_and : binary_atomic_op<atomic_load_and>; 914defm atomic_load_or : binary_atomic_op<atomic_load_or>; 915defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 916defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 917defm atomic_load_min : binary_atomic_op<atomic_load_min>; 918defm atomic_load_max : binary_atomic_op<atomic_load_max>; 919defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 920defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 921defm atomic_store : binary_atomic_op<atomic_store>; 922 923def atomic_load_8 : 924 PatFrag<(ops node:$ptr), 925 (atomic_load node:$ptr), [{ 926 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 927}]>; 928def atomic_load_16 : 929 PatFrag<(ops node:$ptr), 930 (atomic_load node:$ptr), [{ 931 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 932}]>; 933def atomic_load_32 : 934 PatFrag<(ops node:$ptr), 935 (atomic_load node:$ptr), [{ 936 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 937}]>; 938def atomic_load_64 : 939 PatFrag<(ops node:$ptr), 940 (atomic_load node:$ptr), [{ 941 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 942}]>; 943 944//===----------------------------------------------------------------------===// 945// Selection DAG CONVERT_RNDSAT patterns 946 947def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 948 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 949 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 950 }]>; 951 952def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 953 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 954 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 955 }]>; 956 957def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 958 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 959 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 960 }]>; 961 962def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 963 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 964 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 965 }]>; 966 967def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 968 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 969 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 970 }]>; 971 972def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 973 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 974 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 975 }]>; 976 977def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 978 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 979 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 980 }]>; 981 982def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 983 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 984 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 985 }]>; 986 987def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 988 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 989 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 990 }]>; 991 992//===----------------------------------------------------------------------===// 993// Selection DAG Pattern Support. 994// 995// Patterns are what are actually matched against by the target-flavored 996// instruction selection DAG. Instructions defined by the target implicitly 997// define patterns in most cases, but patterns can also be explicitly added when 998// an operation is defined by a sequence of instructions (e.g. loading a large 999// immediate value on RISC targets that do not support immediates as large as 1000// their GPRs). 1001// 1002 1003class Pattern<dag patternToMatch, list<dag> resultInstrs> { 1004 dag PatternToMatch = patternToMatch; 1005 list<dag> ResultInstrs = resultInstrs; 1006 list<Predicate> Predicates = []; // See class Instruction in Target.td. 1007 int AddedComplexity = 0; // See class Instruction in Target.td. 1008} 1009 1010// Pat - A simple (but common) form of a pattern, which produces a simple result 1011// not needing a full list. 1012class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 1013 1014//===----------------------------------------------------------------------===// 1015// Complex pattern definitions. 1016// 1017 1018// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 1019// in C++. NumOperands is the number of operands returned by the select function; 1020// SelectFunc is the name of the function used to pattern match the max. pattern; 1021// RootNodes are the list of possible root nodes of the sub-dags to match. 1022// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 1023// 1024class ComplexPattern<ValueType ty, int numops, string fn, 1025 list<SDNode> roots = [], list<SDNodeProperty> props = []> { 1026 ValueType Ty = ty; 1027 int NumOperands = numops; 1028 string SelectFunc = fn; 1029 list<SDNode> RootNodes = roots; 1030 list<SDNodeProperty> Properties = props; 1031} 1032