TargetSelectionDAG.td revision 76eb5f2401125c358eaf5e97a223a78ad4cc99e9
1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces used by SelectionDAG 11// instruction selection generators. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Selection DAG Type Constraint definitions. 17// 18// Note that the semantics of these constraints are hard coded into tblgen. To 19// modify or add constraints, you have to hack tblgen. 20// 21 22class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24} 25 26// SDTCisVT - The specified operand has exactly this VT. 27class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29} 30 31class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33// SDTCisInt - The specified operand has integer type. 34class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36// SDTCisFP - The specified operand has floating-point type. 37class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39// SDTCisVec - The specified operand has a vector type. 40class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42// SDTCisSameAs - The two specified operands have identical types. 43class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45} 46 47// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48// smaller than the 'Other' operand. 49class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51} 52 53class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55} 56 57/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58/// type as the element type of OtherOp, which is a vector type. 59class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62} 63 64//===----------------------------------------------------------------------===// 65// Selection DAG Type Profile definitions. 66// 67// These use the constraints defined above to describe the type requirements of 68// the various nodes. These are not hard coded into tblgen, allowing targets to 69// add their own if needed. 70// 71 72// SDTypeProfile - This profile describes the type requirements of a Selection 73// DAG node. 74class SDTypeProfile<int numresults, int numoperands, 75 list<SDTypeConstraint> constraints> { 76 int NumResults = numresults; 77 int NumOperands = numoperands; 78 list<SDTypeConstraint> Constraints = constraints; 79} 80 81// Builtin profiles. 82def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 83def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 84def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 85def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 86def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 87def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 88 89def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 90 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 91]>; 92def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 93 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 94]>; 95def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 97]>; 98 99def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 100 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 101]>; 102def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 103 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 104]>; 105def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 106 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 107]>; 108def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 109 SDTCisSameAs<0, 1>, SDTCisInt<0> 110]>; 111def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 112 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 113]>; 114def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 115 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 116]>; 117def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 118 SDTCisSameAs<0, 1>, SDTCisFP<0> 119]>; 120def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 121 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 122]>; 123def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 124 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 125]>; 126def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 127 SDTCisFP<0>, SDTCisInt<1> 128]>; 129def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 130 SDTCisInt<0>, SDTCisFP<1> 131]>; 132def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 133 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 134 SDTCisVTSmallerThanOp<2, 1> 135]>; 136 137def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 138 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 139]>; 140 141def SDTSelect : SDTypeProfile<1, 3, [ // select 142 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 143]>; 144 145def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 146 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 147 SDTCisVT<5, OtherVT> 148]>; 149 150def SDTBr : SDTypeProfile<0, 1, [ // br 151 SDTCisVT<0, OtherVT> 152]>; 153 154def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 155 SDTCisInt<0>, SDTCisVT<1, OtherVT> 156]>; 157 158def SDTBrind : SDTypeProfile<0, 1, [ // brind 159 SDTCisPtrTy<0> 160]>; 161 162def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 163 164def SDTLoad : SDTypeProfile<1, 1, [ // load 165 SDTCisPtrTy<1> 166]>; 167 168def SDTStore : SDTypeProfile<0, 2, [ // store 169 SDTCisPtrTy<1> 170]>; 171 172def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 173 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 174]>; 175 176def SDTVecShuffle : SDTypeProfile<1, 2, [ 177 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 178]>; 179def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 180 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 181]>; 182def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 183 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 184]>; 185 186def SDTPrefetch : SDTypeProfile<0, 3, [ // prefetch 187 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1> 188]>; 189 190def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier 191 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 192 SDTCisInt<0> 193]>; 194def SDTAtomic3 : SDTypeProfile<1, 3, [ 195 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 196]>; 197def SDTAtomic2 : SDTypeProfile<1, 2, [ 198 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 199]>; 200 201def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 202 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 203]>; 204 205class SDCallSeqStart<list<SDTypeConstraint> constraints> : 206 SDTypeProfile<0, 1, constraints>; 207class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 208 SDTypeProfile<0, 2, constraints>; 209 210//===----------------------------------------------------------------------===// 211// Selection DAG Node Properties. 212// 213// Note: These are hard coded into tblgen. 214// 215class SDNodeProperty; 216def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 217def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 218def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 219def SDNPOutFlag : SDNodeProperty; // Write a flag result 220def SDNPInFlag : SDNodeProperty; // Read a flag operand 221def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand 222def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 223def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 224def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 225def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 226def SDNPVariadic : SDNodeProperty; // Node has variable arguments. 227def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match 228def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent 229 230//===----------------------------------------------------------------------===// 231// Selection DAG Pattern Operations 232class SDPatternOperator; 233 234//===----------------------------------------------------------------------===// 235// Selection DAG Node definitions. 236// 237class SDNode<string opcode, SDTypeProfile typeprof, 238 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 239 : SDPatternOperator { 240 string Opcode = opcode; 241 string SDClass = sdclass; 242 list<SDNodeProperty> Properties = props; 243 SDTypeProfile TypeProfile = typeprof; 244} 245 246// Special TableGen-recognized dag nodes 247def set; 248def implicit; 249def node; 250def srcvalue; 251 252def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 253def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 254def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 255def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 256def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 257def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 258def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 259def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 260 "GlobalAddressSDNode">; 261def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 262 "GlobalAddressSDNode">; 263def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 264 "GlobalAddressSDNode">; 265def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 266 "GlobalAddressSDNode">; 267def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 268 "ConstantPoolSDNode">; 269def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 270 "ConstantPoolSDNode">; 271def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 272 "JumpTableSDNode">; 273def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 274 "JumpTableSDNode">; 275def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 276 "FrameIndexSDNode">; 277def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 278 "FrameIndexSDNode">; 279def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 280 "ExternalSymbolSDNode">; 281def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 282 "ExternalSymbolSDNode">; 283def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 284 "BlockAddressSDNode">; 285def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 286 "BlockAddressSDNode">; 287 288def add : SDNode<"ISD::ADD" , SDTIntBinOp , 289 [SDNPCommutative, SDNPAssociative]>; 290def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 291def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 292 [SDNPCommutative, SDNPAssociative]>; 293def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 294def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 295def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 296def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 297def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 298def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 299def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 300def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 301def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 302def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 303def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 304def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 305def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 306def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 307def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 308def and : SDNode<"ISD::AND" , SDTIntBinOp, 309 [SDNPCommutative, SDNPAssociative]>; 310def or : SDNode<"ISD::OR" , SDTIntBinOp, 311 [SDNPCommutative, SDNPAssociative]>; 312def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 313 [SDNPCommutative, SDNPAssociative]>; 314def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 315 [SDNPCommutative, SDNPOutFlag]>; 316def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 317 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>; 318def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 319 [SDNPOutFlag]>; 320def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 321 [SDNPOutFlag, SDNPInFlag]>; 322 323def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 324def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 325def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 326def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 327def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 328def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 329def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 330def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 331def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 332def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>; 333def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 334def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 335 336 337def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 338def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 339def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 340def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 341def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 342def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 343def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 344def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 345def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 346def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 347def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 348def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 349def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 350def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 351def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 352def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 353def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 354 355def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 356def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 357def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 358 359def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 360def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 361def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 362def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 363def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>; 364def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>; 365 366def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 367def select : SDNode<"ISD::SELECT" , SDTSelect>; 368def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 369def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>; 370 371def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 372def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 373def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 374def trap : SDNode<"ISD::TRAP" , SDTNone, 375 [SDNPHasChain, SDNPSideEffect]>; 376 377def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 378 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 379 SDNPMemOperand]>; 380 381def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier, 382 [SDNPHasChain, SDNPSideEffect]>; 383 384def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 385 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 386def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 387 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 388def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 389 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 390def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 391 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 392def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 393 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 394def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 395 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 396def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 397 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 398def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 399 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 400def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 401 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 402def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 403 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 404def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 405 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 406def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 407 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 408 409// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 410// and truncst (see below). 411def ld : SDNode<"ISD::LOAD" , SDTLoad, 412 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 413def st : SDNode<"ISD::STORE" , SDTStore, 414 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 415def ist : SDNode<"ISD::STORE" , SDTIStore, 416 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 417 418def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 419def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 420def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 421 []>; 422def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 423 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 424def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 425 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 426 427// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 428// these internally. Don't reference these directly. 429def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 430 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 431 [SDNPHasChain]>; 432def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 433 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 434 [SDNPHasChain]>; 435def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 436 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 437 438// Do not use cvt directly. Use cvt forms below 439def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 440 441//===----------------------------------------------------------------------===// 442// Selection DAG Condition Codes 443 444class CondCode; // ISD::CondCode enums 445def SETOEQ : CondCode; def SETOGT : CondCode; 446def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 447def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 448def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 449def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 450 451def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 452def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 453 454 455//===----------------------------------------------------------------------===// 456// Selection DAG Node Transformation Functions. 457// 458// This mechanism allows targets to manipulate nodes in the output DAG once a 459// match has been formed. This is typically used to manipulate immediate 460// values. 461// 462class SDNodeXForm<SDNode opc, code xformFunction> { 463 SDNode Opcode = opc; 464 code XFormFunction = xformFunction; 465} 466 467def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 468 469 470//===----------------------------------------------------------------------===// 471// Selection DAG Pattern Fragments. 472// 473// Pattern fragments are reusable chunks of dags that match specific things. 474// They can take arguments and have C++ predicates that control whether they 475// match. They are intended to make the patterns for common instructions more 476// compact and readable. 477// 478 479/// PatFrag - Represents a pattern fragment. This can match something on the 480/// DAG, from a single node to multiple nested other fragments. 481/// 482class PatFrag<dag ops, dag frag, code pred = [{}], 483 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 484 dag Operands = ops; 485 dag Fragment = frag; 486 code Predicate = pred; 487 SDNodeXForm OperandTransform = xform; 488} 489 490// PatLeaf's are pattern fragments that have no operands. This is just a helper 491// to define immediates and other common things concisely. 492class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 493 : PatFrag<(ops), frag, pred, xform>; 494 495// Leaf fragments. 496 497def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 498def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 499 500def immAllOnesV: PatLeaf<(build_vector), [{ 501 return ISD::isBuildVectorAllOnes(N); 502}]>; 503def immAllZerosV: PatLeaf<(build_vector), [{ 504 return ISD::isBuildVectorAllZeros(N); 505}]>; 506 507 508 509// Other helper fragments. 510def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 511def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 512def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 513 514// load fragments. 515def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 516 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 517}]>; 518def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 519 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 520}]>; 521 522// extending load fragments. 523def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 524 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 525}]>; 526def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 527 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 528}]>; 529def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 530 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 531}]>; 532 533def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 534 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 535}]>; 536def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 537 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 538}]>; 539def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 540 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 541}]>; 542def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 543 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 544}]>; 545def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 546 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 547}]>; 548def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 549 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 550}]>; 551 552def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 553 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 554}]>; 555def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 556 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 557}]>; 558def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 559 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 560}]>; 561def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 562 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 563}]>; 564 565def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 566 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 567}]>; 568def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 569 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 570}]>; 571def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 572 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 573}]>; 574def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 575 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 576}]>; 577 578// store fragments. 579def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 580 (st node:$val, node:$ptr), [{ 581 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 582}]>; 583def store : PatFrag<(ops node:$val, node:$ptr), 584 (unindexedstore node:$val, node:$ptr), [{ 585 return !cast<StoreSDNode>(N)->isTruncatingStore(); 586}]>; 587 588// truncstore fragments. 589def truncstore : PatFrag<(ops node:$val, node:$ptr), 590 (unindexedstore node:$val, node:$ptr), [{ 591 return cast<StoreSDNode>(N)->isTruncatingStore(); 592}]>; 593def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 594 (truncstore node:$val, node:$ptr), [{ 595 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 596}]>; 597def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 598 (truncstore node:$val, node:$ptr), [{ 599 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 600}]>; 601def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 602 (truncstore node:$val, node:$ptr), [{ 603 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 604}]>; 605def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 606 (truncstore node:$val, node:$ptr), [{ 607 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 608}]>; 609def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 610 (truncstore node:$val, node:$ptr), [{ 611 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 612}]>; 613 614// indexed store fragments. 615def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 616 (ist node:$val, node:$base, node:$offset), [{ 617 return !cast<StoreSDNode>(N)->isTruncatingStore(); 618}]>; 619 620def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 621 (istore node:$val, node:$base, node:$offset), [{ 622 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 623 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 624}]>; 625 626def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 627 (ist node:$val, node:$base, node:$offset), [{ 628 return cast<StoreSDNode>(N)->isTruncatingStore(); 629}]>; 630def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 631 (itruncstore node:$val, node:$base, node:$offset), [{ 632 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 633 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 634}]>; 635def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 636 (pre_truncst node:$val, node:$base, node:$offset), [{ 637 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 638}]>; 639def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 640 (pre_truncst node:$val, node:$base, node:$offset), [{ 641 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 642}]>; 643def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 644 (pre_truncst node:$val, node:$base, node:$offset), [{ 645 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 646}]>; 647def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 648 (pre_truncst node:$val, node:$base, node:$offset), [{ 649 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 650}]>; 651def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 652 (pre_truncst node:$val, node:$base, node:$offset), [{ 653 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 654}]>; 655 656def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 657 (istore node:$val, node:$ptr, node:$offset), [{ 658 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 659 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 660}]>; 661 662def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 663 (itruncstore node:$val, node:$base, node:$offset), [{ 664 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 665 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 666}]>; 667def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 668 (post_truncst node:$val, node:$base, node:$offset), [{ 669 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 670}]>; 671def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 672 (post_truncst node:$val, node:$base, node:$offset), [{ 673 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 674}]>; 675def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 676 (post_truncst node:$val, node:$base, node:$offset), [{ 677 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 678}]>; 679def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 680 (post_truncst node:$val, node:$base, node:$offset), [{ 681 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 682}]>; 683def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 684 (post_truncst node:$val, node:$base, node:$offset), [{ 685 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 686}]>; 687 688// setcc convenience fragments. 689def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 690 (setcc node:$lhs, node:$rhs, SETOEQ)>; 691def setogt : PatFrag<(ops node:$lhs, node:$rhs), 692 (setcc node:$lhs, node:$rhs, SETOGT)>; 693def setoge : PatFrag<(ops node:$lhs, node:$rhs), 694 (setcc node:$lhs, node:$rhs, SETOGE)>; 695def setolt : PatFrag<(ops node:$lhs, node:$rhs), 696 (setcc node:$lhs, node:$rhs, SETOLT)>; 697def setole : PatFrag<(ops node:$lhs, node:$rhs), 698 (setcc node:$lhs, node:$rhs, SETOLE)>; 699def setone : PatFrag<(ops node:$lhs, node:$rhs), 700 (setcc node:$lhs, node:$rhs, SETONE)>; 701def seto : PatFrag<(ops node:$lhs, node:$rhs), 702 (setcc node:$lhs, node:$rhs, SETO)>; 703def setuo : PatFrag<(ops node:$lhs, node:$rhs), 704 (setcc node:$lhs, node:$rhs, SETUO)>; 705def setueq : PatFrag<(ops node:$lhs, node:$rhs), 706 (setcc node:$lhs, node:$rhs, SETUEQ)>; 707def setugt : PatFrag<(ops node:$lhs, node:$rhs), 708 (setcc node:$lhs, node:$rhs, SETUGT)>; 709def setuge : PatFrag<(ops node:$lhs, node:$rhs), 710 (setcc node:$lhs, node:$rhs, SETUGE)>; 711def setult : PatFrag<(ops node:$lhs, node:$rhs), 712 (setcc node:$lhs, node:$rhs, SETULT)>; 713def setule : PatFrag<(ops node:$lhs, node:$rhs), 714 (setcc node:$lhs, node:$rhs, SETULE)>; 715def setune : PatFrag<(ops node:$lhs, node:$rhs), 716 (setcc node:$lhs, node:$rhs, SETUNE)>; 717def seteq : PatFrag<(ops node:$lhs, node:$rhs), 718 (setcc node:$lhs, node:$rhs, SETEQ)>; 719def setgt : PatFrag<(ops node:$lhs, node:$rhs), 720 (setcc node:$lhs, node:$rhs, SETGT)>; 721def setge : PatFrag<(ops node:$lhs, node:$rhs), 722 (setcc node:$lhs, node:$rhs, SETGE)>; 723def setlt : PatFrag<(ops node:$lhs, node:$rhs), 724 (setcc node:$lhs, node:$rhs, SETLT)>; 725def setle : PatFrag<(ops node:$lhs, node:$rhs), 726 (setcc node:$lhs, node:$rhs, SETLE)>; 727def setne : PatFrag<(ops node:$lhs, node:$rhs), 728 (setcc node:$lhs, node:$rhs, SETNE)>; 729 730def atomic_cmp_swap_8 : 731 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 732 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 733 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 734}]>; 735def atomic_cmp_swap_16 : 736 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 737 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 738 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 739}]>; 740def atomic_cmp_swap_32 : 741 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 742 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 743 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 744}]>; 745def atomic_cmp_swap_64 : 746 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 747 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 748 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 749}]>; 750 751multiclass binary_atomic_op<SDNode atomic_op> { 752 def _8 : PatFrag<(ops node:$ptr, node:$val), 753 (atomic_op node:$ptr, node:$val), [{ 754 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 755 }]>; 756 def _16 : PatFrag<(ops node:$ptr, node:$val), 757 (atomic_op node:$ptr, node:$val), [{ 758 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 759 }]>; 760 def _32 : PatFrag<(ops node:$ptr, node:$val), 761 (atomic_op node:$ptr, node:$val), [{ 762 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 763 }]>; 764 def _64 : PatFrag<(ops node:$ptr, node:$val), 765 (atomic_op node:$ptr, node:$val), [{ 766 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 767 }]>; 768} 769 770defm atomic_load_add : binary_atomic_op<atomic_load_add>; 771defm atomic_swap : binary_atomic_op<atomic_swap>; 772defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 773defm atomic_load_and : binary_atomic_op<atomic_load_and>; 774defm atomic_load_or : binary_atomic_op<atomic_load_or>; 775defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 776defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 777defm atomic_load_min : binary_atomic_op<atomic_load_min>; 778defm atomic_load_max : binary_atomic_op<atomic_load_max>; 779defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 780defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 781 782//===----------------------------------------------------------------------===// 783// Selection DAG CONVERT_RNDSAT patterns 784 785def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 786 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 787 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 788 }]>; 789 790def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 791 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 792 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 793 }]>; 794 795def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 796 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 797 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 798 }]>; 799 800def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 801 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 802 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 803 }]>; 804 805def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 806 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 807 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 808 }]>; 809 810def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 811 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 812 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 813 }]>; 814 815def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 816 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 817 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 818 }]>; 819 820def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 821 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 822 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 823 }]>; 824 825def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 826 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 827 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 828 }]>; 829 830//===----------------------------------------------------------------------===// 831// Selection DAG Pattern Support. 832// 833// Patterns are what are actually matched against by the target-flavored 834// instruction selection DAG. Instructions defined by the target implicitly 835// define patterns in most cases, but patterns can also be explicitly added when 836// an operation is defined by a sequence of instructions (e.g. loading a large 837// immediate value on RISC targets that do not support immediates as large as 838// their GPRs). 839// 840 841class Pattern<dag patternToMatch, list<dag> resultInstrs> { 842 dag PatternToMatch = patternToMatch; 843 list<dag> ResultInstrs = resultInstrs; 844 list<Predicate> Predicates = []; // See class Instruction in Target.td. 845 int AddedComplexity = 0; // See class Instruction in Target.td. 846} 847 848// Pat - A simple (but common) form of a pattern, which produces a simple result 849// not needing a full list. 850class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 851 852//===----------------------------------------------------------------------===// 853// Complex pattern definitions. 854// 855 856// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 857// in C++. NumOperands is the number of operands returned by the select function; 858// SelectFunc is the name of the function used to pattern match the max. pattern; 859// RootNodes are the list of possible root nodes of the sub-dags to match. 860// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 861// 862class ComplexPattern<ValueType ty, int numops, string fn, 863 list<SDNode> roots = [], list<SDNodeProperty> props = []> { 864 ValueType Ty = ty; 865 int NumOperands = numops; 866 string SelectFunc = fn; 867 list<SDNode> RootNodes = roots; 868 list<SDNodeProperty> Properties = props; 869} 870