TargetSelectionDAG.td revision b5b80a93f611ee63788b10d89989b3644642cba5
1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces used by SelectionDAG 11// instruction selection generators. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Selection DAG Type Constraint definitions. 17// 18// Note that the semantics of these constraints are hard coded into tblgen. To 19// modify or add constraints, you have to hack tblgen. 20// 21 22class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24} 25 26// SDTCisVT - The specified operand has exactly this VT. 27class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29} 30 31class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33// SDTCisInt - The specified operand has integer type. 34class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36// SDTCisFP - The specified operand has floating-point type. 37class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39// SDTCisVec - The specified operand has a vector type. 40class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42// SDTCisSameAs - The two specified operands have identical types. 43class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45} 46 47// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48// smaller than the 'Other' operand. 49class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51} 52 53class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55} 56 57/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58/// type as the element type of OtherOp, which is a vector type. 59class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62} 63 64/// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 65/// with length less that of OtherOp, which is a vector type. 66class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 67 : SDTypeConstraint<ThisOp> { 68 int OtherOpNum = OtherOp; 69} 70 71//===----------------------------------------------------------------------===// 72// Selection DAG Type Profile definitions. 73// 74// These use the constraints defined above to describe the type requirements of 75// the various nodes. These are not hard coded into tblgen, allowing targets to 76// add their own if needed. 77// 78 79// SDTypeProfile - This profile describes the type requirements of a Selection 80// DAG node. 81class SDTypeProfile<int numresults, int numoperands, 82 list<SDTypeConstraint> constraints> { 83 int NumResults = numresults; 84 int NumOperands = numoperands; 85 list<SDTypeConstraint> Constraints = constraints; 86} 87 88// Builtin profiles. 89def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 90def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 91def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 92def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 93def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 94def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 95 96def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 97 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 98]>; 99def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 100 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 101]>; 102def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 103 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 104]>; 105 106def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 107 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 108]>; 109def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 110 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 111]>; 112def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 114]>; 115def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 116 SDTCisSameAs<0, 1>, SDTCisInt<0> 117]>; 118def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 119 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 120]>; 121def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 122 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 123]>; 124def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 125 SDTCisSameAs<0, 1>, SDTCisFP<0> 126]>; 127def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 128 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 129]>; 130def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 131 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 132]>; 133def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 134 SDTCisFP<0>, SDTCisInt<1> 135]>; 136def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 137 SDTCisInt<0>, SDTCisFP<1> 138]>; 139def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 140 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 141 SDTCisVTSmallerThanOp<2, 1> 142]>; 143 144def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 145 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 146]>; 147 148def SDTSelect : SDTypeProfile<1, 3, [ // select 149 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 150]>; 151 152def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 153 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 154 SDTCisVT<5, OtherVT> 155]>; 156 157def SDTBr : SDTypeProfile<0, 1, [ // br 158 SDTCisVT<0, OtherVT> 159]>; 160 161def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 162 SDTCisInt<0>, SDTCisVT<1, OtherVT> 163]>; 164 165def SDTBrind : SDTypeProfile<0, 1, [ // brind 166 SDTCisPtrTy<0> 167]>; 168 169def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 170 171def SDTLoad : SDTypeProfile<1, 1, [ // load 172 SDTCisPtrTy<1> 173]>; 174 175def SDTStore : SDTypeProfile<0, 2, [ // store 176 SDTCisPtrTy<1> 177]>; 178 179def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 180 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 181]>; 182 183def SDTVecShuffle : SDTypeProfile<1, 2, [ 184 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 185]>; 186def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 187 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 188]>; 189def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 190 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 191]>; 192 193def SDTSubVecExtract : SDTypeProfile<1, 1, [// subvector extract 194 SDTCisSubVecOfVec<0,1> 195]>; 196def SDTSubVecInsert : SDTypeProfile<1, 2, [ // subvector insert 197 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1> 198]>; 199 200def SDTPrefetch : SDTypeProfile<0, 3, [ // prefetch 201 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1> 202]>; 203 204def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier 205 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 206 SDTCisInt<0> 207]>; 208def SDTAtomic3 : SDTypeProfile<1, 3, [ 209 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 210]>; 211def SDTAtomic2 : SDTypeProfile<1, 2, [ 212 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 213]>; 214 215def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 216 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 217]>; 218 219class SDCallSeqStart<list<SDTypeConstraint> constraints> : 220 SDTypeProfile<0, 1, constraints>; 221class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 222 SDTypeProfile<0, 2, constraints>; 223 224//===----------------------------------------------------------------------===// 225// Selection DAG Node Properties. 226// 227// Note: These are hard coded into tblgen. 228// 229class SDNodeProperty; 230def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 231def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 232def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 233def SDNPOutGlue : SDNodeProperty; // Write a flag result 234def SDNPInGlue : SDNodeProperty; // Read a flag operand 235def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand 236def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 237def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 238def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 239def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 240def SDNPVariadic : SDNodeProperty; // Node has variable arguments. 241def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match 242def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent 243 244//===----------------------------------------------------------------------===// 245// Selection DAG Pattern Operations 246class SDPatternOperator; 247 248//===----------------------------------------------------------------------===// 249// Selection DAG Node definitions. 250// 251class SDNode<string opcode, SDTypeProfile typeprof, 252 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 253 : SDPatternOperator { 254 string Opcode = opcode; 255 string SDClass = sdclass; 256 list<SDNodeProperty> Properties = props; 257 SDTypeProfile TypeProfile = typeprof; 258} 259 260// Special TableGen-recognized dag nodes 261def set; 262def implicit; 263def node; 264def srcvalue; 265 266def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 267def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 268def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 269def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 270def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 271def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 272def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 273def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 274 "GlobalAddressSDNode">; 275def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 276 "GlobalAddressSDNode">; 277def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 278 "GlobalAddressSDNode">; 279def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 280 "GlobalAddressSDNode">; 281def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 282 "ConstantPoolSDNode">; 283def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 284 "ConstantPoolSDNode">; 285def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 286 "JumpTableSDNode">; 287def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 288 "JumpTableSDNode">; 289def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 290 "FrameIndexSDNode">; 291def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 292 "FrameIndexSDNode">; 293def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 294 "ExternalSymbolSDNode">; 295def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 296 "ExternalSymbolSDNode">; 297def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 298 "BlockAddressSDNode">; 299def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 300 "BlockAddressSDNode">; 301 302def add : SDNode<"ISD::ADD" , SDTIntBinOp , 303 [SDNPCommutative, SDNPAssociative]>; 304def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 305def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 306 [SDNPCommutative, SDNPAssociative]>; 307def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 308def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 309def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 310def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 311def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 312def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 313def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 314def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 315def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 316def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 317def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 318def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 319def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 320def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 321def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 322def and : SDNode<"ISD::AND" , SDTIntBinOp, 323 [SDNPCommutative, SDNPAssociative]>; 324def or : SDNode<"ISD::OR" , SDTIntBinOp, 325 [SDNPCommutative, SDNPAssociative]>; 326def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 327 [SDNPCommutative, SDNPAssociative]>; 328def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 329 [SDNPCommutative, SDNPOutGlue]>; 330def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 331 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 332def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 333 [SDNPOutGlue]>; 334def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 335 [SDNPOutGlue, SDNPInGlue]>; 336 337def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 338def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 339def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 340def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 341def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 342def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 343def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 344def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 345def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 346def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 347def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 348def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 349 350 351def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 352def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 353def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 354def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 355def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 356def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 357def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 358def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 359def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 360def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 361def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 362def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 363def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 364def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 365def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 366def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 367def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 368 369def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 370def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 371def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 372 373def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 374def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 375def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 376def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 377def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>; 378def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>; 379 380def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 381def select : SDNode<"ISD::SELECT" , SDTSelect>; 382def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 383def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>; 384 385def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 386def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 387def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 388def trap : SDNode<"ISD::TRAP" , SDTNone, 389 [SDNPHasChain, SDNPSideEffect]>; 390 391def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 392 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 393 SDNPMemOperand]>; 394 395def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier, 396 [SDNPHasChain, SDNPSideEffect]>; 397 398def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 399 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 400def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 401 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 402def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 403 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 404def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 405 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 406def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 407 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 408def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 409 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 410def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 411 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 412def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 413 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 414def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 415 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 416def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 417 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 418def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 419 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 420def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 421 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 422 423// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 424// and truncst (see below). 425def ld : SDNode<"ISD::LOAD" , SDTLoad, 426 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 427def st : SDNode<"ISD::STORE" , SDTStore, 428 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 429def ist : SDNode<"ISD::STORE" , SDTIStore, 430 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 431 432def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 433def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 434def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 435 []>; 436def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 437 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 438def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 439 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 440 []>; 441def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 442 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 443 444// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 445// these internally. Don't reference these directly. 446def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 447 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 448 [SDNPHasChain]>; 449def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 450 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 451 [SDNPHasChain]>; 452def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 453 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 454 455// Do not use cvt directly. Use cvt forms below 456def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 457 458//===----------------------------------------------------------------------===// 459// Selection DAG Condition Codes 460 461class CondCode; // ISD::CondCode enums 462def SETOEQ : CondCode; def SETOGT : CondCode; 463def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 464def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 465def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 466def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 467 468def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 469def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 470 471 472//===----------------------------------------------------------------------===// 473// Selection DAG Node Transformation Functions. 474// 475// This mechanism allows targets to manipulate nodes in the output DAG once a 476// match has been formed. This is typically used to manipulate immediate 477// values. 478// 479class SDNodeXForm<SDNode opc, code xformFunction> { 480 SDNode Opcode = opc; 481 code XFormFunction = xformFunction; 482} 483 484def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 485 486 487//===----------------------------------------------------------------------===// 488// Selection DAG Pattern Fragments. 489// 490// Pattern fragments are reusable chunks of dags that match specific things. 491// They can take arguments and have C++ predicates that control whether they 492// match. They are intended to make the patterns for common instructions more 493// compact and readable. 494// 495 496/// PatFrag - Represents a pattern fragment. This can match something on the 497/// DAG, from a single node to multiple nested other fragments. 498/// 499class PatFrag<dag ops, dag frag, code pred = [{}], 500 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 501 dag Operands = ops; 502 dag Fragment = frag; 503 code Predicate = pred; 504 SDNodeXForm OperandTransform = xform; 505} 506 507// PatLeaf's are pattern fragments that have no operands. This is just a helper 508// to define immediates and other common things concisely. 509class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 510 : PatFrag<(ops), frag, pred, xform>; 511 512// Leaf fragments. 513 514def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 515def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 516 517def immAllOnesV: PatLeaf<(build_vector), [{ 518 return ISD::isBuildVectorAllOnes(N); 519}]>; 520def immAllZerosV: PatLeaf<(build_vector), [{ 521 return ISD::isBuildVectorAllZeros(N); 522}]>; 523 524 525 526// Other helper fragments. 527def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 528def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 529def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 530 531// load fragments. 532def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 533 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 534}]>; 535def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 536 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 537}]>; 538 539// extending load fragments. 540def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 541 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 542}]>; 543def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 544 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 545}]>; 546def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 547 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 548}]>; 549 550def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 551 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 552}]>; 553def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 554 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 555}]>; 556def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 557 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 558}]>; 559def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 560 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 561}]>; 562def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 563 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 564}]>; 565def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 566 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 567}]>; 568 569def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 570 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 571}]>; 572def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 573 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 574}]>; 575def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 576 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 577}]>; 578def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 579 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 580}]>; 581 582def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 583 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 584}]>; 585def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 586 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 587}]>; 588def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 589 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 590}]>; 591def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 592 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 593}]>; 594 595// store fragments. 596def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 597 (st node:$val, node:$ptr), [{ 598 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 599}]>; 600def store : PatFrag<(ops node:$val, node:$ptr), 601 (unindexedstore node:$val, node:$ptr), [{ 602 return !cast<StoreSDNode>(N)->isTruncatingStore(); 603}]>; 604 605// truncstore fragments. 606def truncstore : PatFrag<(ops node:$val, node:$ptr), 607 (unindexedstore node:$val, node:$ptr), [{ 608 return cast<StoreSDNode>(N)->isTruncatingStore(); 609}]>; 610def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 611 (truncstore node:$val, node:$ptr), [{ 612 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 613}]>; 614def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 615 (truncstore node:$val, node:$ptr), [{ 616 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 617}]>; 618def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 619 (truncstore node:$val, node:$ptr), [{ 620 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 621}]>; 622def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 623 (truncstore node:$val, node:$ptr), [{ 624 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 625}]>; 626def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 627 (truncstore node:$val, node:$ptr), [{ 628 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 629}]>; 630 631// indexed store fragments. 632def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 633 (ist node:$val, node:$base, node:$offset), [{ 634 return !cast<StoreSDNode>(N)->isTruncatingStore(); 635}]>; 636 637def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 638 (istore node:$val, node:$base, node:$offset), [{ 639 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 640 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 641}]>; 642 643def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 644 (ist node:$val, node:$base, node:$offset), [{ 645 return cast<StoreSDNode>(N)->isTruncatingStore(); 646}]>; 647def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 648 (itruncstore node:$val, node:$base, node:$offset), [{ 649 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 650 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 651}]>; 652def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 653 (pre_truncst node:$val, node:$base, node:$offset), [{ 654 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 655}]>; 656def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 657 (pre_truncst node:$val, node:$base, node:$offset), [{ 658 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 659}]>; 660def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 661 (pre_truncst node:$val, node:$base, node:$offset), [{ 662 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 663}]>; 664def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 665 (pre_truncst node:$val, node:$base, node:$offset), [{ 666 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 667}]>; 668def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 669 (pre_truncst node:$val, node:$base, node:$offset), [{ 670 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 671}]>; 672 673def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 674 (istore node:$val, node:$ptr, node:$offset), [{ 675 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 676 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 677}]>; 678 679def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 680 (itruncstore node:$val, node:$base, node:$offset), [{ 681 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 682 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 683}]>; 684def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 685 (post_truncst node:$val, node:$base, node:$offset), [{ 686 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 687}]>; 688def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 689 (post_truncst node:$val, node:$base, node:$offset), [{ 690 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 691}]>; 692def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 693 (post_truncst node:$val, node:$base, node:$offset), [{ 694 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 695}]>; 696def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 697 (post_truncst node:$val, node:$base, node:$offset), [{ 698 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 699}]>; 700def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 701 (post_truncst node:$val, node:$base, node:$offset), [{ 702 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 703}]>; 704 705// setcc convenience fragments. 706def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 707 (setcc node:$lhs, node:$rhs, SETOEQ)>; 708def setogt : PatFrag<(ops node:$lhs, node:$rhs), 709 (setcc node:$lhs, node:$rhs, SETOGT)>; 710def setoge : PatFrag<(ops node:$lhs, node:$rhs), 711 (setcc node:$lhs, node:$rhs, SETOGE)>; 712def setolt : PatFrag<(ops node:$lhs, node:$rhs), 713 (setcc node:$lhs, node:$rhs, SETOLT)>; 714def setole : PatFrag<(ops node:$lhs, node:$rhs), 715 (setcc node:$lhs, node:$rhs, SETOLE)>; 716def setone : PatFrag<(ops node:$lhs, node:$rhs), 717 (setcc node:$lhs, node:$rhs, SETONE)>; 718def seto : PatFrag<(ops node:$lhs, node:$rhs), 719 (setcc node:$lhs, node:$rhs, SETO)>; 720def setuo : PatFrag<(ops node:$lhs, node:$rhs), 721 (setcc node:$lhs, node:$rhs, SETUO)>; 722def setueq : PatFrag<(ops node:$lhs, node:$rhs), 723 (setcc node:$lhs, node:$rhs, SETUEQ)>; 724def setugt : PatFrag<(ops node:$lhs, node:$rhs), 725 (setcc node:$lhs, node:$rhs, SETUGT)>; 726def setuge : PatFrag<(ops node:$lhs, node:$rhs), 727 (setcc node:$lhs, node:$rhs, SETUGE)>; 728def setult : PatFrag<(ops node:$lhs, node:$rhs), 729 (setcc node:$lhs, node:$rhs, SETULT)>; 730def setule : PatFrag<(ops node:$lhs, node:$rhs), 731 (setcc node:$lhs, node:$rhs, SETULE)>; 732def setune : PatFrag<(ops node:$lhs, node:$rhs), 733 (setcc node:$lhs, node:$rhs, SETUNE)>; 734def seteq : PatFrag<(ops node:$lhs, node:$rhs), 735 (setcc node:$lhs, node:$rhs, SETEQ)>; 736def setgt : PatFrag<(ops node:$lhs, node:$rhs), 737 (setcc node:$lhs, node:$rhs, SETGT)>; 738def setge : PatFrag<(ops node:$lhs, node:$rhs), 739 (setcc node:$lhs, node:$rhs, SETGE)>; 740def setlt : PatFrag<(ops node:$lhs, node:$rhs), 741 (setcc node:$lhs, node:$rhs, SETLT)>; 742def setle : PatFrag<(ops node:$lhs, node:$rhs), 743 (setcc node:$lhs, node:$rhs, SETLE)>; 744def setne : PatFrag<(ops node:$lhs, node:$rhs), 745 (setcc node:$lhs, node:$rhs, SETNE)>; 746 747def atomic_cmp_swap_8 : 748 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 749 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 750 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 751}]>; 752def atomic_cmp_swap_16 : 753 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 754 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 755 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 756}]>; 757def atomic_cmp_swap_32 : 758 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 759 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 760 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 761}]>; 762def atomic_cmp_swap_64 : 763 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 764 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 765 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 766}]>; 767 768multiclass binary_atomic_op<SDNode atomic_op> { 769 def _8 : PatFrag<(ops node:$ptr, node:$val), 770 (atomic_op node:$ptr, node:$val), [{ 771 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 772 }]>; 773 def _16 : PatFrag<(ops node:$ptr, node:$val), 774 (atomic_op node:$ptr, node:$val), [{ 775 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 776 }]>; 777 def _32 : PatFrag<(ops node:$ptr, node:$val), 778 (atomic_op node:$ptr, node:$val), [{ 779 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 780 }]>; 781 def _64 : PatFrag<(ops node:$ptr, node:$val), 782 (atomic_op node:$ptr, node:$val), [{ 783 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 784 }]>; 785} 786 787defm atomic_load_add : binary_atomic_op<atomic_load_add>; 788defm atomic_swap : binary_atomic_op<atomic_swap>; 789defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 790defm atomic_load_and : binary_atomic_op<atomic_load_and>; 791defm atomic_load_or : binary_atomic_op<atomic_load_or>; 792defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 793defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 794defm atomic_load_min : binary_atomic_op<atomic_load_min>; 795defm atomic_load_max : binary_atomic_op<atomic_load_max>; 796defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 797defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 798 799//===----------------------------------------------------------------------===// 800// Selection DAG CONVERT_RNDSAT patterns 801 802def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 803 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 804 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 805 }]>; 806 807def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 808 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 809 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 810 }]>; 811 812def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 813 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 814 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 815 }]>; 816 817def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 818 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 819 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 820 }]>; 821 822def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 823 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 824 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 825 }]>; 826 827def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 828 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 829 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 830 }]>; 831 832def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 833 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 834 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 835 }]>; 836 837def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 838 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 839 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 840 }]>; 841 842def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 843 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 844 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 845 }]>; 846 847//===----------------------------------------------------------------------===// 848// Selection DAG Pattern Support. 849// 850// Patterns are what are actually matched against by the target-flavored 851// instruction selection DAG. Instructions defined by the target implicitly 852// define patterns in most cases, but patterns can also be explicitly added when 853// an operation is defined by a sequence of instructions (e.g. loading a large 854// immediate value on RISC targets that do not support immediates as large as 855// their GPRs). 856// 857 858class Pattern<dag patternToMatch, list<dag> resultInstrs> { 859 dag PatternToMatch = patternToMatch; 860 list<dag> ResultInstrs = resultInstrs; 861 list<Predicate> Predicates = []; // See class Instruction in Target.td. 862 int AddedComplexity = 0; // See class Instruction in Target.td. 863} 864 865// Pat - A simple (but common) form of a pattern, which produces a simple result 866// not needing a full list. 867class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 868 869//===----------------------------------------------------------------------===// 870// Complex pattern definitions. 871// 872 873// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 874// in C++. NumOperands is the number of operands returned by the select function; 875// SelectFunc is the name of the function used to pattern match the max. pattern; 876// RootNodes are the list of possible root nodes of the sub-dags to match. 877// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 878// 879class ComplexPattern<ValueType ty, int numops, string fn, 880 list<SDNode> roots = [], list<SDNodeProperty> props = []> { 881 ValueType Ty = ty; 882 int NumOperands = numops; 883 string SelectFunc = fn; 884 list<SDNode> RootNodes = roots; 885 list<SDNodeProperty> Properties = props; 886} 887