TargetSelectionDAG.td revision e1b469170bb3ab259fd488fb95c29efe802cdd6a
1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces used by SelectionDAG 11// instruction selection generators. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Selection DAG Type Constraint definitions. 17// 18// Note that the semantics of these constraints are hard coded into tblgen. To 19// modify or add constraints, you have to hack tblgen. 20// 21 22class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24} 25 26// SDTCisVT - The specified operand has exactly this VT. 27class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29} 30 31class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33// SDTCisInt - The specified operand is has integer type. 34class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36// SDTCisFP - The specified operand is has floating point type. 37class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39// SDTCisSameAs - The two specified operands have identical types. 40class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 41 int OtherOperandNum = OtherOp; 42} 43 44// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 45// smaller than the 'Other' operand. 46class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 47 int OtherOperandNum = OtherOp; 48} 49 50class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 51 int BigOperandNum = BigOp; 52} 53 54/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 55/// type as the element type of OtherOp, which is a vector type. 56class SDTCisEltOfVec<int ThisOp, int OtherOp> 57 : SDTypeConstraint<ThisOp> { 58 int OtherOpNum = OtherOp; 59} 60 61//===----------------------------------------------------------------------===// 62// Selection DAG Type Profile definitions. 63// 64// These use the constraints defined above to describe the type requirements of 65// the various nodes. These are not hard coded into tblgen, allowing targets to 66// add their own if needed. 67// 68 69// SDTypeProfile - This profile describes the type requirements of a Selection 70// DAG node. 71class SDTypeProfile<int numresults, int numoperands, 72 list<SDTypeConstraint> constraints> { 73 int NumResults = numresults; 74 int NumOperands = numoperands; 75 list<SDTypeConstraint> Constraints = constraints; 76} 77 78// Builtin profiles. 79def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 80def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 81def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 82def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 83def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 84def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 85 86def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 87 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 88]>; 89def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 90 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 91]>; 92def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 93 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 94]>; 95def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 96 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 97]>; 98def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 99 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 100]>; 101def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 102 SDTCisSameAs<0, 1>, SDTCisInt<0> 103]>; 104def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 105 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 106]>; 107def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 108 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 109]>; 110def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 111 SDTCisSameAs<0, 1>, SDTCisFP<0> 112]>; 113def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 114 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 115]>; 116def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 117 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 118]>; 119def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 120 SDTCisFP<0>, SDTCisInt<1> 121]>; 122def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 123 SDTCisInt<0>, SDTCisFP<1> 124]>; 125def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 126 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 127 SDTCisVTSmallerThanOp<2, 1> 128]>; 129 130def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 131 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 132]>; 133 134def SDTSelect : SDTypeProfile<1, 3, [ // select 135 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 136]>; 137 138def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 139 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 140 SDTCisVT<5, OtherVT> 141]>; 142 143def SDTBr : SDTypeProfile<0, 1, [ // br 144 SDTCisVT<0, OtherVT> 145]>; 146 147def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 148 SDTCisInt<0>, SDTCisVT<1, OtherVT> 149]>; 150 151def SDTBrind : SDTypeProfile<0, 1, [ // brind 152 SDTCisPtrTy<0> 153]>; 154 155def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 156 157def SDTLoad : SDTypeProfile<1, 1, [ // load 158 SDTCisPtrTy<1> 159]>; 160 161def SDTStore : SDTypeProfile<0, 2, [ // store 162 SDTCisPtrTy<1> 163]>; 164 165def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 166 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 167]>; 168 169def SDTVecShuffle : SDTypeProfile<1, 2, [ 170 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 171]>; 172def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 173 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 174]>; 175def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 176 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 177]>; 178 179def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch 180 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1> 181]>; 182 183def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier 184 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 185 SDTCisInt<0> 186]>; 187def STDAtomic3 : SDTypeProfile<1, 3, [ 188 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 189]>; 190def STDAtomic2 : SDTypeProfile<1, 2, [ 191 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 192]>; 193 194def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 195 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 196]>; 197 198class SDCallSeqStart<list<SDTypeConstraint> constraints> : 199 SDTypeProfile<0, 1, constraints>; 200class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 201 SDTypeProfile<0, 2, constraints>; 202 203//===----------------------------------------------------------------------===// 204// Selection DAG Node Properties. 205// 206// Note: These are hard coded into tblgen. 207// 208class SDNodeProperty; 209def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 210def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 211def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 212def SDNPOutFlag : SDNodeProperty; // Write a flag result 213def SDNPInFlag : SDNodeProperty; // Read a flag operand 214def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand 215def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 216def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 217def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 218def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 219 220//===----------------------------------------------------------------------===// 221// Selection DAG Node definitions. 222// 223class SDNode<string opcode, SDTypeProfile typeprof, 224 list<SDNodeProperty> props = [], string sdclass = "SDNode"> { 225 string Opcode = opcode; 226 string SDClass = sdclass; 227 list<SDNodeProperty> Properties = props; 228 SDTypeProfile TypeProfile = typeprof; 229} 230 231// Special TableGen-recognized dag nodes 232def set; 233def implicit; 234def parallel; 235def node; 236def srcvalue; 237 238def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 239def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 240def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 241def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 242def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 243def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 244def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 245def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 246 "GlobalAddressSDNode">; 247def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 248 "GlobalAddressSDNode">; 249def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 250 "GlobalAddressSDNode">; 251def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 252 "GlobalAddressSDNode">; 253def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 254 "ConstantPoolSDNode">; 255def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 256 "ConstantPoolSDNode">; 257def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 258 "JumpTableSDNode">; 259def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 260 "JumpTableSDNode">; 261def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 262 "FrameIndexSDNode">; 263def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 264 "FrameIndexSDNode">; 265def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 266 "ExternalSymbolSDNode">; 267def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 268 "ExternalSymbolSDNode">; 269 270def add : SDNode<"ISD::ADD" , SDTIntBinOp , 271 [SDNPCommutative, SDNPAssociative]>; 272def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 273def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 274 [SDNPCommutative, SDNPAssociative]>; 275def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 276def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 277def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 278def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 279def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 280def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 281def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 282def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 283def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 284def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 285def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 286def and : SDNode<"ISD::AND" , SDTIntBinOp, 287 [SDNPCommutative, SDNPAssociative]>; 288def or : SDNode<"ISD::OR" , SDTIntBinOp, 289 [SDNPCommutative, SDNPAssociative]>; 290def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 291 [SDNPCommutative, SDNPAssociative]>; 292def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 293 [SDNPCommutative, SDNPOutFlag]>; 294def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 295 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>; 296def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 297 [SDNPOutFlag]>; 298def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 299 [SDNPOutFlag, SDNPInFlag]>; 300 301def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 302def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 303def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 304def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 305def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 306def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 307def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 308def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 309def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 310def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>; 311def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 312def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 313 314 315def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 316def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 317def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 318def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 319def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 320def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 321def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 322def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 323def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 324def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 325def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 326def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 327def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 328def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 329def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 330 331def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 332def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 333def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 334 335def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 336def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 337def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 338def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 339 340def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 341def select : SDNode<"ISD::SELECT" , SDTSelect>; 342def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 343def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>; 344 345def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 346def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 347def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 348def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>; 349def trap : SDNode<"ISD::TRAP" , SDTNone, 350 [SDNPHasChain, SDNPSideEffect]>; 351 352def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch, 353 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 354 355def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier, 356 [SDNPHasChain, SDNPSideEffect]>; 357 358def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , STDAtomic3, 359 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 360def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2, 361 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 362def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2, 363 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 364def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2, 365 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 366def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2, 367 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 368def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2, 369 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 370def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2, 371 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 372def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2, 373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 374def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2, 375 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 376def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2, 377 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 378def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2, 379 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 380def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2, 381 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 382 383// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 384// and truncst (see below). 385def ld : SDNode<"ISD::LOAD" , SDTLoad, 386 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 387def st : SDNode<"ISD::STORE" , SDTStore, 388 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 389def ist : SDNode<"ISD::STORE" , SDTIStore, 390 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 391 392def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 393def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 394def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 395 []>; 396def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 397 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 398def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 399 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 400 401// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 402// these internally. Don't reference these directly. 403def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 404 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 405 [SDNPHasChain]>; 406def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 407 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 408 [SDNPHasChain]>; 409def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 410 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 411 412// Do not use cvt directly. Use cvt forms below 413def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 414 415//===----------------------------------------------------------------------===// 416// Selection DAG Condition Codes 417 418class CondCode; // ISD::CondCode enums 419def SETOEQ : CondCode; def SETOGT : CondCode; 420def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 421def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 422def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 423def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 424 425def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 426def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 427 428 429//===----------------------------------------------------------------------===// 430// Selection DAG Node Transformation Functions. 431// 432// This mechanism allows targets to manipulate nodes in the output DAG once a 433// match has been formed. This is typically used to manipulate immediate 434// values. 435// 436class SDNodeXForm<SDNode opc, code xformFunction> { 437 SDNode Opcode = opc; 438 code XFormFunction = xformFunction; 439} 440 441def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 442 443 444//===----------------------------------------------------------------------===// 445// Selection DAG Pattern Fragments. 446// 447// Pattern fragments are reusable chunks of dags that match specific things. 448// They can take arguments and have C++ predicates that control whether they 449// match. They are intended to make the patterns for common instructions more 450// compact and readable. 451// 452 453/// PatFrag - Represents a pattern fragment. This can match something on the 454/// DAG, frame a single node to multiply nested other fragments. 455/// 456class PatFrag<dag ops, dag frag, code pred = [{}], 457 SDNodeXForm xform = NOOP_SDNodeXForm> { 458 dag Operands = ops; 459 dag Fragment = frag; 460 code Predicate = pred; 461 SDNodeXForm OperandTransform = xform; 462} 463 464// PatLeaf's are pattern fragments that have no operands. This is just a helper 465// to define immediates and other common things concisely. 466class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 467 : PatFrag<(ops), frag, pred, xform>; 468 469// Leaf fragments. 470 471def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 472def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 473 474def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>; 475def immAllOnesV: PatLeaf<(build_vector), [{ 476 return ISD::isBuildVectorAllOnes(N); 477}]>; 478def immAllOnesV_bc: PatLeaf<(bitconvert), [{ 479 return ISD::isBuildVectorAllOnes(N); 480}]>; 481def immAllZerosV: PatLeaf<(build_vector), [{ 482 return ISD::isBuildVectorAllZeros(N); 483}]>; 484def immAllZerosV_bc: PatLeaf<(bitconvert), [{ 485 return ISD::isBuildVectorAllZeros(N); 486}]>; 487 488 489 490// Other helper fragments. 491def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>; 492def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 493def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>; 494def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 495 496// load fragments. 497def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 498 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 499}]>; 500def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 501 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 502}]>; 503 504// extending load fragments. 505def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 506 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 507}]>; 508def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 509 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 510}]>; 511def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 512 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 513}]>; 514 515def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 516 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 517}]>; 518def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 519 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 520}]>; 521def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 522 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 523}]>; 524def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 525 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 526}]>; 527def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 528 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 529}]>; 530def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 531 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 532}]>; 533 534def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 535 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 536}]>; 537def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 538 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 539}]>; 540def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 541 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 542}]>; 543def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 544 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 545}]>; 546 547def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 548 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 549}]>; 550def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 551 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 552}]>; 553def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 554 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 555}]>; 556def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 557 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 558}]>; 559 560// store fragments. 561def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 562 (st node:$val, node:$ptr), [{ 563 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 564}]>; 565def store : PatFrag<(ops node:$val, node:$ptr), 566 (unindexedstore node:$val, node:$ptr), [{ 567 return !cast<StoreSDNode>(N)->isTruncatingStore(); 568}]>; 569 570// truncstore fragments. 571def truncstore : PatFrag<(ops node:$val, node:$ptr), 572 (unindexedstore node:$val, node:$ptr), [{ 573 return cast<StoreSDNode>(N)->isTruncatingStore(); 574}]>; 575def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 576 (truncstore node:$val, node:$ptr), [{ 577 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 578}]>; 579def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 580 (truncstore node:$val, node:$ptr), [{ 581 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 582}]>; 583def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 584 (truncstore node:$val, node:$ptr), [{ 585 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 586}]>; 587def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 588 (truncstore node:$val, node:$ptr), [{ 589 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 590}]>; 591def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 592 (truncstore node:$val, node:$ptr), [{ 593 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 594}]>; 595 596// indexed store fragments. 597def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 598 (ist node:$val, node:$base, node:$offset), [{ 599 return !cast<StoreSDNode>(N)->isTruncatingStore(); 600}]>; 601 602def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 603 (istore node:$val, node:$base, node:$offset), [{ 604 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 605 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 606}]>; 607 608def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 609 (ist node:$val, node:$base, node:$offset), [{ 610 return cast<StoreSDNode>(N)->isTruncatingStore(); 611}]>; 612def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 613 (itruncstore node:$val, node:$base, node:$offset), [{ 614 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 615 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 616}]>; 617def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 618 (pre_truncst node:$val, node:$base, node:$offset), [{ 619 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 620}]>; 621def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 622 (pre_truncst node:$val, node:$base, node:$offset), [{ 623 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 624}]>; 625def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 626 (pre_truncst node:$val, node:$base, node:$offset), [{ 627 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 628}]>; 629def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 630 (pre_truncst node:$val, node:$base, node:$offset), [{ 631 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 632}]>; 633def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 634 (pre_truncst node:$val, node:$base, node:$offset), [{ 635 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 636}]>; 637 638def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 639 (istore node:$val, node:$ptr, node:$offset), [{ 640 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 641 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 642}]>; 643 644def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 645 (itruncstore node:$val, node:$base, node:$offset), [{ 646 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 647 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 648}]>; 649def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 650 (post_truncst node:$val, node:$base, node:$offset), [{ 651 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 652}]>; 653def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 654 (post_truncst node:$val, node:$base, node:$offset), [{ 655 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 656}]>; 657def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 658 (post_truncst node:$val, node:$base, node:$offset), [{ 659 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 660}]>; 661def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 662 (post_truncst node:$val, node:$base, node:$offset), [{ 663 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 664}]>; 665def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 666 (post_truncst node:$val, node:$base, node:$offset), [{ 667 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 668}]>; 669 670// setcc convenience fragments. 671def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 672 (setcc node:$lhs, node:$rhs, SETOEQ)>; 673def setogt : PatFrag<(ops node:$lhs, node:$rhs), 674 (setcc node:$lhs, node:$rhs, SETOGT)>; 675def setoge : PatFrag<(ops node:$lhs, node:$rhs), 676 (setcc node:$lhs, node:$rhs, SETOGE)>; 677def setolt : PatFrag<(ops node:$lhs, node:$rhs), 678 (setcc node:$lhs, node:$rhs, SETOLT)>; 679def setole : PatFrag<(ops node:$lhs, node:$rhs), 680 (setcc node:$lhs, node:$rhs, SETOLE)>; 681def setone : PatFrag<(ops node:$lhs, node:$rhs), 682 (setcc node:$lhs, node:$rhs, SETONE)>; 683def seto : PatFrag<(ops node:$lhs, node:$rhs), 684 (setcc node:$lhs, node:$rhs, SETO)>; 685def setuo : PatFrag<(ops node:$lhs, node:$rhs), 686 (setcc node:$lhs, node:$rhs, SETUO)>; 687def setueq : PatFrag<(ops node:$lhs, node:$rhs), 688 (setcc node:$lhs, node:$rhs, SETUEQ)>; 689def setugt : PatFrag<(ops node:$lhs, node:$rhs), 690 (setcc node:$lhs, node:$rhs, SETUGT)>; 691def setuge : PatFrag<(ops node:$lhs, node:$rhs), 692 (setcc node:$lhs, node:$rhs, SETUGE)>; 693def setult : PatFrag<(ops node:$lhs, node:$rhs), 694 (setcc node:$lhs, node:$rhs, SETULT)>; 695def setule : PatFrag<(ops node:$lhs, node:$rhs), 696 (setcc node:$lhs, node:$rhs, SETULE)>; 697def setune : PatFrag<(ops node:$lhs, node:$rhs), 698 (setcc node:$lhs, node:$rhs, SETUNE)>; 699def seteq : PatFrag<(ops node:$lhs, node:$rhs), 700 (setcc node:$lhs, node:$rhs, SETEQ)>; 701def setgt : PatFrag<(ops node:$lhs, node:$rhs), 702 (setcc node:$lhs, node:$rhs, SETGT)>; 703def setge : PatFrag<(ops node:$lhs, node:$rhs), 704 (setcc node:$lhs, node:$rhs, SETGE)>; 705def setlt : PatFrag<(ops node:$lhs, node:$rhs), 706 (setcc node:$lhs, node:$rhs, SETLT)>; 707def setle : PatFrag<(ops node:$lhs, node:$rhs), 708 (setcc node:$lhs, node:$rhs, SETLE)>; 709def setne : PatFrag<(ops node:$lhs, node:$rhs), 710 (setcc node:$lhs, node:$rhs, SETNE)>; 711 712def atomic_cmp_swap_8 : 713 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 714 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 715 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 716}]>; 717def atomic_cmp_swap_16 : 718 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 719 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 720 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 721}]>; 722def atomic_cmp_swap_32 : 723 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 724 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 725 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 726}]>; 727def atomic_cmp_swap_64 : 728 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 729 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 730 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 731}]>; 732 733multiclass binary_atomic_op<SDNode atomic_op> { 734 def _8 : PatFrag<(ops node:$ptr, node:$val), 735 (atomic_op node:$ptr, node:$val), [{ 736 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 737 }]>; 738 def _16 : PatFrag<(ops node:$ptr, node:$val), 739 (atomic_op node:$ptr, node:$val), [{ 740 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 741 }]>; 742 def _32 : PatFrag<(ops node:$ptr, node:$val), 743 (atomic_op node:$ptr, node:$val), [{ 744 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 745 }]>; 746 def _64 : PatFrag<(ops node:$ptr, node:$val), 747 (atomic_op node:$ptr, node:$val), [{ 748 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 749 }]>; 750} 751 752defm atomic_load_add : binary_atomic_op<atomic_load_add>; 753defm atomic_swap : binary_atomic_op<atomic_swap>; 754defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 755defm atomic_load_and : binary_atomic_op<atomic_load_and>; 756defm atomic_load_or : binary_atomic_op<atomic_load_or>; 757defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 758defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 759defm atomic_load_min : binary_atomic_op<atomic_load_min>; 760defm atomic_load_max : binary_atomic_op<atomic_load_max>; 761defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 762defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 763 764//===----------------------------------------------------------------------===// 765// Selection DAG CONVERT_RNDSAT patterns 766 767def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 768 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 769 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 770 }]>; 771 772def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 773 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 774 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 775 }]>; 776 777def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 778 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 779 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 780 }]>; 781 782def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 783 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 784 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 785 }]>; 786 787def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 788 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 789 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 790 }]>; 791 792def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 793 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 794 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 795 }]>; 796 797def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 798 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 799 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 800 }]>; 801 802def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 803 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 804 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 805 }]>; 806 807def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 808 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 809 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 810 }]>; 811 812//===----------------------------------------------------------------------===// 813// Selection DAG Pattern Support. 814// 815// Patterns are what are actually matched against the target-flavored 816// instruction selection DAG. Instructions defined by the target implicitly 817// define patterns in most cases, but patterns can also be explicitly added when 818// an operation is defined by a sequence of instructions (e.g. loading a large 819// immediate value on RISC targets that do not support immediates as large as 820// their GPRs). 821// 822 823class Pattern<dag patternToMatch, list<dag> resultInstrs> { 824 dag PatternToMatch = patternToMatch; 825 list<dag> ResultInstrs = resultInstrs; 826 list<Predicate> Predicates = []; // See class Instruction in Target.td. 827 int AddedComplexity = 0; // See class Instruction in Target.td. 828} 829 830// Pat - A simple (but common) form of a pattern, which produces a simple result 831// not needing a full list. 832class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 833 834//===----------------------------------------------------------------------===// 835// Complex pattern definitions. 836// 837 838class CPAttribute; 839// Pass the parent Operand as root to CP function rather 840// than the root of the sub-DAG 841def CPAttrParentAsRoot : CPAttribute; 842 843// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 844// in C++. NumOperands is the number of operands returned by the select function; 845// SelectFunc is the name of the function used to pattern match the max. pattern; 846// RootNodes are the list of possible root nodes of the sub-dags to match. 847// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 848// 849class ComplexPattern<ValueType ty, int numops, string fn, 850 list<SDNode> roots = [], list<SDNodeProperty> props = [], 851 list<CPAttribute> attrs = []> { 852 ValueType Ty = ty; 853 int NumOperands = numops; 854 string SelectFunc = fn; 855 list<SDNode> RootNodes = roots; 856 list<SDNodeProperty> Properties = props; 857 list<CPAttribute> Attributes = attrs; 858} 859 860//===----------------------------------------------------------------------===// 861// Dwarf support. 862// 863def SDT_dwarf_loc : SDTypeProfile<0, 3, 864 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>; 865def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>; 866