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AggressiveAntiDepBreaker.cpp12-Mar-201534.4 KiB

AggressiveAntiDepBreaker.h12-Mar-20157.1 KiB

AllocationOrder.cpp12-Mar-20151.8 KiB

AllocationOrder.h12-Mar-20152.7 KiB

Analysis.cpp12-Mar-201524.5 KiB

Android.mk12-Mar-20153.5 KiB

AntiDepBreaker.h12-Mar-20152.6 KiB

AsmPrinter/12-Mar-20154 KiB

AtomicExpandLoadLinkedPass.cpp12-Mar-201513.7 KiB

BasicTargetTransformInfo.cpp12-Mar-201523.3 KiB

BranchFolding.cpp12-Mar-201564.8 KiB

BranchFolding.h12-Mar-20154.2 KiB

CalcSpillWeights.cpp12-Mar-20156.3 KiB

CallingConvLower.cpp12-Mar-20156.5 KiB

CMakeLists.txt12-Mar-20152.7 KiB

CodeGen.cpp12-Mar-20153.2 KiB

CodeGenPrepare.cpp12-Mar-2015121.6 KiB

CriticalAntiDepBreaker.cpp12-Mar-201527.8 KiB

CriticalAntiDepBreaker.h12-Mar-20154.3 KiB

DeadMachineInstructionElim.cpp12-Mar-20156.6 KiB

DFAPacketizer.cpp12-Mar-20158.2 KiB

DwarfEHPrepare.cpp12-Mar-20155.9 KiB

EarlyIfConversion.cpp12-Mar-201528.5 KiB

EdgeBundles.cpp12-Mar-20153 KiB

ErlangGC.cpp12-Mar-20152.5 KiB

ExecutionDepsFix.cpp12-Mar-201525.7 KiB

ExpandISelPseudos.cpp12-Mar-20152.5 KiB

ExpandPostRAPseudos.cpp12-Mar-20157.1 KiB

GCMetadata.cpp12-Mar-20154.9 KiB

GCMetadataPrinter.cpp12-Mar-2015824

GCStrategy.cpp12-Mar-201514.1 KiB

GlobalMerge.cpp12-Mar-201512.5 KiB

IfConversion.cpp12-Mar-201559.7 KiB

InlineSpiller.cpp12-Mar-201548.4 KiB

InterferenceCache.cpp12-Mar-20158.4 KiB

InterferenceCache.h12-Mar-20157 KiB

IntrinsicLowering.cpp12-Mar-201521.1 KiB

JITCodeEmitter.cpp12-Mar-2015440

JumpInstrTables.cpp12-Mar-201510 KiB

LatencyPriorityQueue.cpp12-Mar-20155.5 KiB

LexicalScopes.cpp12-Mar-201511.9 KiB

LiveDebugVariables.cpp12-Mar-201534.5 KiB

LiveDebugVariables.h12-Mar-20152.5 KiB

LiveInterval.cpp12-Mar-201530.1 KiB

LiveIntervalAnalysis.cpp12-Mar-201542.6 KiB

LiveIntervalUnion.cpp12-Mar-20156.4 KiB

LivePhysRegs.cpp12-Mar-20153.3 KiB

LiveRangeCalc.cpp12-Mar-201512.8 KiB

LiveRangeCalc.h12-Mar-20159.7 KiB

LiveRangeEdit.cpp12-Mar-201513.9 KiB

LiveRegMatrix.cpp12-Mar-20155.5 KiB

LiveStackAnalysis.cpp12-Mar-20152.9 KiB

LiveVariables.cpp12-Mar-201530 KiB

LLVMBuild.txt12-Mar-2015795

LLVMTargetMachine.cpp12-Mar-201511 KiB

LocalStackSlotAllocation.cpp12-Mar-201516.5 KiB

MachineBasicBlock.cpp12-Mar-201542.5 KiB

MachineBlockFrequencyInfo.cpp12-Mar-20156 KiB

MachineBlockPlacement.cpp12-Mar-201548.6 KiB

MachineBranchProbabilityInfo.cpp12-Mar-20154.2 KiB

MachineCodeEmitter.cpp12-Mar-2015449

MachineCopyPropagation.cpp12-Mar-201511.6 KiB

MachineCSE.cpp12-Mar-201523.1 KiB

MachineDominators.cpp12-Mar-20151.7 KiB

MachineFunction.cpp12-Mar-201534.5 KiB

MachineFunctionAnalysis.cpp12-Mar-20151.8 KiB

MachineFunctionPass.cpp12-Mar-20152.1 KiB

MachineFunctionPrinterPass.cpp12-Mar-20152.1 KiB

MachineInstr.cpp12-Mar-201566.4 KiB

MachineInstrBundle.cpp12-Mar-201510.6 KiB

MachineLICM.cpp12-Mar-201553.3 KiB

MachineLoopInfo.cpp12-Mar-20152.8 KiB

MachineModuleInfo.cpp12-Mar-201520.3 KiB

MachineModuleInfoImpls.cpp12-Mar-20151.6 KiB

MachinePassRegistry.cpp12-Mar-20151.7 KiB

MachinePostDominators.cpp12-Mar-20151.7 KiB

MachineRegisterInfo.cpp12-Mar-201514.9 KiB

MachineScheduler.cpp12-Mar-2015118.7 KiB

MachineSink.cpp12-Mar-201525.5 KiB

MachineSSAUpdater.cpp12-Mar-201512.9 KiB

MachineTraceMetrics.cpp12-Mar-201548.3 KiB

MachineVerifier.cpp12-Mar-201562.2 KiB

Makefile12-Mar-2015719

module.modulemap12-Mar-201573

OcamlGC.cpp12-Mar-2015999

OptimizePHIs.cpp12-Mar-20156.2 KiB

Passes.cpp12-Mar-201529.9 KiB

PeepholeOptimizer.cpp12-Mar-201538.6 KiB

PHIElimination.cpp12-Mar-201525.5 KiB

PHIEliminationUtils.cpp12-Mar-20152.2 KiB

PHIEliminationUtils.h12-Mar-2015936

PostRASchedulerList.cpp12-Mar-201523.3 KiB

ProcessImplicitDefs.cpp12-Mar-20155.4 KiB

PrologEpilogInserter.cpp12-Mar-201534.8 KiB

PrologEpilogInserter.h12-Mar-20152.7 KiB

PseudoSourceValue.cpp12-Mar-20153.8 KiB

README.txt12-Mar-20156.2 KiB

RegAllocBase.cpp12-Mar-20155.6 KiB

RegAllocBase.h12-Mar-20153.9 KiB

RegAllocBasic.cpp12-Mar-201510.3 KiB

RegAllocFast.cpp12-Mar-201540.7 KiB

RegAllocGreedy.cpp12-Mar-201588 KiB

RegAllocPBQP.cpp12-Mar-201520.8 KiB

RegisterClassInfo.cpp12-Mar-20156.2 KiB

RegisterCoalescer.cpp12-Mar-201584.6 KiB

RegisterCoalescer.h12-Mar-20154.4 KiB

RegisterPressure.cpp12-Mar-201535.3 KiB

RegisterScavenging.cpp12-Mar-201514 KiB

ScheduleDAG.cpp12-Mar-201519.8 KiB

ScheduleDAGInstrs.cpp12-Mar-201557.1 KiB

ScheduleDAGPrinter.cpp12-Mar-20153.2 KiB

ScoreboardHazardRecognizer.cpp12-Mar-20157.9 KiB

SelectionDAG/12-Mar-20154 KiB

ShadowStackGC.cpp12-Mar-201517.1 KiB

SjLjEHPrepare.cpp12-Mar-201519.7 KiB

SlotIndexes.cpp12-Mar-20158.1 KiB

Spiller.cpp12-Mar-20155.6 KiB

Spiller.h12-Mar-20151.3 KiB

SpillPlacement.cpp12-Mar-201513.4 KiB

SpillPlacement.h12-Mar-20156.2 KiB

SplitKit.cpp12-Mar-201550.3 KiB

SplitKit.h12-Mar-201519.2 KiB

StackColoring.cpp12-Mar-201528.2 KiB

StackMapLivenessAnalysis.cpp12-Mar-20154.5 KiB

StackMaps.cpp12-Mar-201517.5 KiB

StackProtector.cpp12-Mar-201518 KiB

StackSlotColoring.cpp12-Mar-201515.2 KiB

TailDuplication.cpp12-Mar-201534.9 KiB

TargetFrameLoweringImpl.cpp12-Mar-20151.7 KiB

TargetInstrInfo.cpp12-Mar-201530.3 KiB

TargetLoweringBase.cpp12-Mar-201555.7 KiB

TargetLoweringObjectFileImpl.cpp12-Mar-201535 KiB

TargetOptionsImpl.cpp12-Mar-20152.1 KiB

TargetRegisterInfo.cpp12-Mar-201510.7 KiB

TargetSchedule.cpp12-Mar-201510.8 KiB

TwoAddressInstructionPass.cpp12-Mar-201560.1 KiB

UnreachableBlockElim.cpp12-Mar-20157.1 KiB

VirtRegMap.cpp12-Mar-201515.5 KiB

README.txt

1//===---------------------------------------------------------------------===//
2
3Common register allocation / spilling problem:
4
5        mul lr, r4, lr
6        str lr, [sp, #+52]
7        ldr lr, [r1, #+32]
8        sxth r3, r3
9        ldr r4, [sp, #+52]
10        mla r4, r3, lr, r4
11
12can be:
13
14        mul lr, r4, lr
15        mov r4, lr
16        str lr, [sp, #+52]
17        ldr lr, [r1, #+32]
18        sxth r3, r3
19        mla r4, r3, lr, r4
20
21and then "merge" mul and mov:
22
23        mul r4, r4, lr
24        str r4, [sp, #+52]
25        ldr lr, [r1, #+32]
26        sxth r3, r3
27        mla r4, r3, lr, r4
28
29It also increase the likelihood the store may become dead.
30
31//===---------------------------------------------------------------------===//
32
33bb27 ...
34        ...
35        %reg1037 = ADDri %reg1039, 1
36        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
37    Successors according to CFG: 0x8b03bf0 (#5)
38
39bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
40    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
41        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>
42
43Note ADDri is not a two-address instruction. However, its result %reg1037 is an
44operand of the PHI node in bb76 and its operand %reg1039 is the result of the
45PHI node. We should treat it as a two-address code and make sure the ADDri is
46scheduled after any node that reads %reg1039.
47
48//===---------------------------------------------------------------------===//
49
50Use local info (i.e. register scavenger) to assign it a free register to allow
51reuse:
52        ldr r3, [sp, #+4]
53        add r3, r3, #3
54        ldr r2, [sp, #+8]
55        add r2, r2, #2
56        ldr r1, [sp, #+4]  <==
57        add r1, r1, #1
58        ldr r0, [sp, #+4]
59        add r0, r0, #2
60
61//===---------------------------------------------------------------------===//
62
63LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
64effects:
65
66R1 = X + 4
67R2 = X + 7
68R3 = X + 15
69
70loop:
71load [i + R1]
72...
73load [i + R2]
74...
75load [i + R3]
76
77Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
78to implement proper re-materialization to handle this:
79
80R1 = X + 4
81R2 = X + 7
82R3 = X + 15
83
84loop:
85R1 = X + 4  @ re-materialized
86load [i + R1]
87...
88R2 = X + 7 @ re-materialized
89load [i + R2]
90...
91R3 = X + 15 @ re-materialized
92load [i + R3]
93
94Furthermore, with re-association, we can enable sharing:
95
96R1 = X + 4
97R2 = X + 7
98R3 = X + 15
99
100loop:
101T = i + X
102load [T + 4]
103...
104load [T + 7]
105...
106load [T + 15]
107//===---------------------------------------------------------------------===//
108
109It's not always a good idea to choose rematerialization over spilling. If all
110the load / store instructions would be folded then spilling is cheaper because
111it won't require new live intervals / registers. See 2003-05-31-LongShifts for
112an example.
113
114//===---------------------------------------------------------------------===//
115
116With a copying garbage collector, derived pointers must not be retained across
117collector safe points; the collector could move the objects and invalidate the
118derived pointer. This is bad enough in the first place, but safe points can
119crop up unpredictably. Consider:
120
121        %array = load { i32, [0 x %obj] }** %array_addr
122        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
123        %old = load %obj** %nth_el
124        %z = div i64 %x, %y
125        store %obj* %new, %obj** %nth_el
126
127If the i64 division is lowered to a libcall, then a safe point will (must)
128appear for the call site. If a collection occurs, %array and %nth_el no longer
129point into the correct object.
130
131The fix for this is to copy address calculations so that dependent pointers
132are never live across safe point boundaries. But the loads cannot be copied
133like this if there was an intervening store, so may be hard to get right.
134
135Only a concurrent mutator can trigger a collection at the libcall safe point.
136So single-threaded programs do not have this requirement, even with a copying
137collector. Still, LLVM optimizations would probably undo a front-end's careful
138work.
139
140//===---------------------------------------------------------------------===//
141
142The ocaml frametable structure supports liveness information. It would be good
143to support it.
144
145//===---------------------------------------------------------------------===//
146
147The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
148revisited. The check is there to work around a misuse of directives in inline
149assembly.
150
151//===---------------------------------------------------------------------===//
152
153It would be good to detect collector/target compatibility instead of silently
154doing the wrong thing.
155
156//===---------------------------------------------------------------------===//
157
158It would be really nice to be able to write patterns in .td files for copies,
159which would eliminate a bunch of explicit predicates on them (e.g. no side 
160effects).  Once this is in place, it would be even better to have tblgen 
161synthesize the various copy insertion/inspection methods in TargetInstrInfo.
162
163//===---------------------------------------------------------------------===//
164
165Stack coloring improvements:
166
1671. Do proper LiveStackAnalysis on all stack objects including those which are
168   not spill slots.
1692. Reorder objects to fill in gaps between objects.
170   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4
171
172//===---------------------------------------------------------------------===//
173
174The scheduler should be able to sort nearby instructions by their address. For
175example, in an expanded memset sequence it's not uncommon to see code like this:
176
177  movl $0, 4(%rdi)
178  movl $0, 8(%rdi)
179  movl $0, 12(%rdi)
180  movl $0, 0(%rdi)
181
182Each of the stores is independent, and the scheduler is currently making an
183arbitrary decision about the order.
184
185//===---------------------------------------------------------------------===//
186
187Another opportunitiy in this code is that the $0 could be moved to a register:
188
189  movl $0, 4(%rdi)
190  movl $0, 8(%rdi)
191  movl $0, 12(%rdi)
192  movl $0, 0(%rdi)
193
194This would save substantial code size, especially for longer sequences like
195this. It would be easy to have a rule telling isel to avoid matching MOV32mi
196if the immediate has more than some fixed number of uses. It's more involved
197to teach the register allocator how to do late folding to recover from
198excessive register pressure.
199
200