12e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin//===----- CriticalAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===// 22e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 32e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// The LLVM Compiler Infrastructure 42e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 52e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// This file is distributed under the University of Illinois Open Source 62e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// License. See LICENSE.TXT for details. 72e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 82e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin//===----------------------------------------------------------------------===// 92e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// This file implements the CriticalAntiDepBreaker class, which 112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// implements register anti-dependence breaking along a blocks 122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// critical path during post-RA scheduler. 132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin// 142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin//===----------------------------------------------------------------------===// 152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "CriticalAntiDepBreaker.h" 172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/CodeGen/MachineBasicBlock.h" 182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/Support/Debug.h" 202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/Support/ErrorHandling.h" 212e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#include "llvm/Support/raw_ostream.h" 22d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/Target/TargetInstrInfo.h" 23d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/Target/TargetMachine.h" 24d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/Target/TargetRegisterInfo.h" 252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinusing namespace llvm; 272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 28dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#define DEBUG_TYPE "post-RA-sched" 29dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 302e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid GoodwinCriticalAntiDepBreaker:: 31fa796dd720f1b34596a043f17f098fac18ecc028Jakob Stoklund OlesenCriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) : 322e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepBreaker(), MF(MFi), 332e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MRI(MF.getRegInfo()), 3446df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng TII(MF.getTarget().getInstrInfo()), 352e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin TRI(MF.getTarget().getRegisterInfo()), 36fa796dd720f1b34596a043f17f098fac18ecc028Jakob Stoklund Olesen RegClassInfo(RCI), 37dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Classes(TRI->getNumRegs(), nullptr), 389c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling KillIndices(TRI->getNumRegs(), 0), 39cff4ad768ec721b72498dc6b605d882e36c1fb14Benjamin Kramer DefIndices(TRI->getNumRegs(), 0), 40cff4ad768ec721b72498dc6b605d882e36c1fb14Benjamin Kramer KeepRegs(TRI->getNumRegs(), false) {} 412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid GoodwinCriticalAntiDepBreaker::~CriticalAntiDepBreaker() { 432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 442e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 452e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) { 46990d2857654cb80e46d207533834be3047494830David Goodwin const unsigned BBSize = BB->size(); 479c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { 489c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling // Clear out the register class data. 49dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Classes[i] = nullptr; 509c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling 519c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling // Initialize the indices to indicate that no registers are live. 52990d2857654cb80e46d207533834be3047494830David Goodwin KillIndices[i] = ~0u; 53990d2857654cb80e46d207533834be3047494830David Goodwin DefIndices[i] = BBSize; 54990d2857654cb80e46d207533834be3047494830David Goodwin } 552e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 562e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Clear "do not change" set. 57cff4ad768ec721b72498dc6b605d882e36c1fb14Benjamin Kramer KeepRegs.reset(); 582e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5987f3dbc446181dc5b1c525bd28ca89760f63bc76Benjamin Kramer bool IsReturnBlock = (BBSize != 0 && BB->back().isReturn()); 602e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 61b45e4deb102d47602f5b941da7f412ecc9a867e9Jakob Stoklund Olesen // Examine the live-in regs of all successors. 6246df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), 632e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin SE = BB->succ_end(); SI != SE; ++SI) 6446df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), 652e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin E = (*SI)->livein_end(); I != E; ++I) { 66f152fe8d487c46873bbdd4abab43200f783e978bJakob Stoklund Olesen for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { 67f152fe8d487c46873bbdd4abab43200f783e978bJakob Stoklund Olesen unsigned Reg = *AI; 68f152fe8d487c46873bbdd4abab43200f783e978bJakob Stoklund Olesen Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 69f152fe8d487c46873bbdd4abab43200f783e978bJakob Stoklund Olesen KillIndices[Reg] = BBSize; 70f152fe8d487c46873bbdd4abab43200f783e978bJakob Stoklund Olesen DefIndices[Reg] = ~0u; 712e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 7246df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng } 732e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 742e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Mark live-out callee-saved registers. In a return block this is 752e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // all callee-saved registers. In non-return this is any 762e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // callee-saved register that is not saved in the prolog. 772e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin const MachineFrameInfo *MFI = MF.getFrameInfo(); 782e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin BitVector Pristine = MFI->getPristineRegs(BB); 79dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { 80f152fe8d487c46873bbdd4abab43200f783e978bJakob Stoklund Olesen if (!IsReturnBlock && !Pristine.test(*I)) continue; 81f152fe8d487c46873bbdd4abab43200f783e978bJakob Stoklund Olesen for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { 82f152fe8d487c46873bbdd4abab43200f783e978bJakob Stoklund Olesen unsigned Reg = *AI; 83f152fe8d487c46873bbdd4abab43200f783e978bJakob Stoklund Olesen Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 84f152fe8d487c46873bbdd4abab43200f783e978bJakob Stoklund Olesen KillIndices[Reg] = BBSize; 85f152fe8d487c46873bbdd4abab43200f783e978bJakob Stoklund Olesen DefIndices[Reg] = ~0u; 862e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 872e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 882e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 892e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 902e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::FinishBlock() { 912e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RegRefs.clear(); 92cff4ad768ec721b72498dc6b605d882e36c1fb14Benjamin Kramer KeepRegs.reset(); 932e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 942e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 952e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count, 962e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned InsertPosIndex) { 9722c310d78ce9630af15b0de94c18a409705b7496Tim Murray // Kill instructions can define registers but are really nops, and there might 9822c310d78ce9630af15b0de94c18a409705b7496Tim Murray // be a real definition earlier that needs to be paired with uses dominated by 9922c310d78ce9630af15b0de94c18a409705b7496Tim Murray // this kill. 10022c310d78ce9630af15b0de94c18a409705b7496Tim Murray 10122c310d78ce9630af15b0de94c18a409705b7496Tim Murray // FIXME: It may be possible to remove the isKill() restriction once PR18663 10222c310d78ce9630af15b0de94c18a409705b7496Tim Murray // has been properly fixed. There can be value in processing kills as seen in 10322c310d78ce9630af15b0de94c18a409705b7496Tim Murray // the AggressiveAntiDepBreaker class. 10422c310d78ce9630af15b0de94c18a409705b7496Tim Murray if (MI->isDebugValue() || MI->isKill()) 105b0812f114b83a32c4b90a4b553c7177c557558b5Dale Johannesen return; 1062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(Count < InsertPosIndex && "Instruction index out of expected range!"); 1072e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 108f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { 109f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson if (KillIndices[Reg] != ~0u) { 110f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // If Reg is currently live, then mark that it can't be renamed as 111f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // we don't know the extent of its live-range anymore (now that it 112f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // has been scheduled). 113f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 114f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson KillIndices[Reg] = Count; 115f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) { 116f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // Any register which was defined within the previous scheduling region 117f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // may have been rescheduled and its lifetime may overlap with registers 118f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // in ways not reflected in our current liveness state. For each such 119f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // register, adjust the liveness state to be conservatively correct. 1202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 1219c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling 1222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Move the def index to the end of the previous region, to reflect 1232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // that the def could theoretically have been scheduled at the end. 1242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[Reg] = InsertPosIndex; 1252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 126f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson } 1272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin PrescanInstruction(MI); 1292e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin ScanInstruction(MI, Count); 1302e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 1312e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1322e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin/// CriticalPathStep - Return the next SUnit after SU on the bottom-up 1332e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin/// critical path. 13466db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohmanstatic const SDep *CriticalPathStep(const SUnit *SU) { 135dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const SDep *Next = nullptr; 1362e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned NextDepth = 0; 1372e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Find the predecessor edge with the greatest depth. 13866db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end(); 1392e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin P != PE; ++P) { 14066db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman const SUnit *PredSU = P->getSUnit(); 1412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned PredLatency = P->getLatency(); 1422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned PredTotalLatency = PredSU->getDepth() + PredLatency; 1432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // In the case of a latency tie, prefer an anti-dependency edge over 1442e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // other types of edges. 1452e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (NextDepth < PredTotalLatency || 1462e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) { 1472e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin NextDepth = PredTotalLatency; 1482e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Next = &*P; 1492e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 1502e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 1512e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin return Next; 1522e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 1532e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1542e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) { 15546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // It's not safe to change register allocation for source operands of 156cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // instructions that have special allocation requirements. Also assume all 157cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // registers used in a call must not be changed (ABI). 15846df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // FIXME: The issue with predicated instruction is more complex. We are being 15959718a4f42551fc0034b860cb8119f728023c303Bob Wilson // conservative here because the kill markers cannot be trusted after 16046df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // if-conversion: 16146df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] 16246df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // ... 16346df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395] 16446df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12] 16546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8) 16646df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // 16746df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // The first R6 kill is not really a kill since it's killed by a predicated 16846df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // instruction which may not be executed. The second R6 def may or may not 16946df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // re-define R6 so it's not safe to change it since the last R6 use cannot be 17046df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // changed. 1715a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng bool Special = MI->isCall() || 1725a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng MI->hasExtraSrcRegAllocReq() || 17346df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng TII->isPredicated(MI); 17446df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng 1752e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Scan the register operands for this instruction and update 1762e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Classes and RegRefs. 1772e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1782e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineOperand &MO = MI->getOperand(i); 1792e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!MO.isReg()) continue; 1802e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = MO.getReg(); 1812e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Reg == 0) continue; 182dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterClass *NewRC = nullptr; 18301384ef159caa7eebff0e1d703638f2e2c862092Jim Grosbach 1842e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (i < MI->getDesc().getNumOperands()) 185397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF); 1862e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1872e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // For now, only allow the register to be changed if its register 1882e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // class is consistent across all uses. 1892e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!Classes[Reg] && NewRC) 1902e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = NewRC; 1912e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin else if (!NewRC || Classes[Reg] != NewRC) 1922e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 1932e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 1942e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Now check for aliases. 195396618b43a85e12d290a90b181c6af5d7c0c5f11Jakob Stoklund Olesen for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) { 1962e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If an alias of the reg is used during the live range, give up. 1972e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Note that this allows us to skip checking if AntiDepReg 1982e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // overlaps with any of the aliases, among other things. 199396618b43a85e12d290a90b181c6af5d7c0c5f11Jakob Stoklund Olesen unsigned AliasReg = *AI; 2002e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Classes[AliasReg]) { 2012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1); 2022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 2032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2052e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 2062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If we're still willing to consider this register, note the reference. 2072e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1)) 2082e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RegRefs.insert(std::make_pair(Reg, &MO)); 2092e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 210cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // If this reg is tied and live (Classes[Reg] is set to -1), we can't change 211cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // it or any of its sub or super regs. We need to use KeepRegs to mark the 212cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // reg because not all uses of the same reg within an instruction are 213cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // necessarily tagged as tied. 214cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // Example: an x86 "xor %eax, %eax" will have one source operand tied to the 215cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // def register but not the second (see PR20020 for details). 216cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // FIXME: can this check be relaxed to account for undef uses 217cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // of a register? In the above 'xor' example, the uses of %eax are undef, so 218cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // earlier instructions could still replace %eax even though the 'xor' 219cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // itself can't be changed. 220cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines if (MI->isRegTiedToUseOperand(i) && 221cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) { 222cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); 223cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines SubRegs.isValid(); ++SubRegs) { 224cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines KeepRegs.set(*SubRegs); 225cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines } 226cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines for (MCSuperRegIterator SuperRegs(Reg, TRI); 227cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines SuperRegs.isValid(); ++SuperRegs) { 228cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines KeepRegs.set(*SuperRegs); 229cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines } 230cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines } 231cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 23246df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng if (MO.isUse() && Special) { 233cff4ad768ec721b72498dc6b605d882e36c1fb14Benjamin Kramer if (!KeepRegs.test(Reg)) { 23462c320a755ac27ac2b7f64e927892249e0f486e0Chad Rosier for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); 23562c320a755ac27ac2b7f64e927892249e0f486e0Chad Rosier SubRegs.isValid(); ++SubRegs) 236396618b43a85e12d290a90b181c6af5d7c0c5f11Jakob Stoklund Olesen KeepRegs.set(*SubRegs); 2372e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2382e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2392e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 2412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 2422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinvoid CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI, 2432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Count) { 2442e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Update liveness. 245d9b0b025612992a0b724eeca8bdf10b1d7a5c355Benjamin Kramer // Proceeding upwards, registers that are defed but not used in this 2462e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // instruction are now dead. 24722c310d78ce9630af15b0de94c18a409705b7496Tim Murray assert(!MI->isKill() && "Attempting to scan a kill instruction"); 24846df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng 24946df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng if (!TII->isPredicated(MI)) { 25046df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // Predicated defs are modeled as read + write, i.e. similar to two 25146df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // address updates. 25246df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 25346df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng MachineOperand &MO = MI->getOperand(i); 254bbad2f1040fea671b4413f53b3fd816cb7bd2443Jakob Stoklund Olesen 255bbad2f1040fea671b4413f53b3fd816cb7bd2443Jakob Stoklund Olesen if (MO.isRegMask()) 256bbad2f1040fea671b4413f53b3fd816cb7bd2443Jakob Stoklund Olesen for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) 257bbad2f1040fea671b4413f53b3fd816cb7bd2443Jakob Stoklund Olesen if (MO.clobbersPhysReg(i)) { 258bbad2f1040fea671b4413f53b3fd816cb7bd2443Jakob Stoklund Olesen DefIndices[i] = Count; 259bbad2f1040fea671b4413f53b3fd816cb7bd2443Jakob Stoklund Olesen KillIndices[i] = ~0u; 260cff4ad768ec721b72498dc6b605d882e36c1fb14Benjamin Kramer KeepRegs.reset(i); 261dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Classes[i] = nullptr; 262bbad2f1040fea671b4413f53b3fd816cb7bd2443Jakob Stoklund Olesen RegRefs.erase(i); 263bbad2f1040fea671b4413f53b3fd816cb7bd2443Jakob Stoklund Olesen } 264bbad2f1040fea671b4413f53b3fd816cb7bd2443Jakob Stoklund Olesen 26546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng if (!MO.isReg()) continue; 26646df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng unsigned Reg = MO.getReg(); 26746df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng if (Reg == 0) continue; 26846df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng if (!MO.isDef()) continue; 269cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 270cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // If we've already marked this reg as unchangeable, carry on. 271cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines if (KeepRegs.test(Reg)) continue; 272cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 27346df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // Ignore two-addr defs. 27446df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng if (MI->isRegTiedToUseOperand(i)) continue; 27546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng 276cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // FIXME: we should use a SubRegIterator that includes self (as above), so 277cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // we don't have to repeat all this code for the reg itself. 27846df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng DefIndices[Reg] = Count; 27946df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng KillIndices[Reg] = ~0u; 28046df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng assert(((KillIndices[Reg] == ~0u) != 28146df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng (DefIndices[Reg] == ~0u)) && 28246df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng "Kill and Def maps aren't consistent for Reg!"); 283cff4ad768ec721b72498dc6b605d882e36c1fb14Benjamin Kramer KeepRegs.reset(Reg); 284dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Classes[Reg] = nullptr; 28546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng RegRefs.erase(Reg); 28646df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // Repeat, for all subregs. 287396618b43a85e12d290a90b181c6af5d7c0c5f11Jakob Stoklund Olesen for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { 288396618b43a85e12d290a90b181c6af5d7c0c5f11Jakob Stoklund Olesen unsigned SubregReg = *SubRegs; 28946df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng DefIndices[SubregReg] = Count; 29046df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng KillIndices[SubregReg] = ~0u; 291cff4ad768ec721b72498dc6b605d882e36c1fb14Benjamin Kramer KeepRegs.reset(SubregReg); 292dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Classes[SubregReg] = nullptr; 29346df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng RegRefs.erase(SubregReg); 29446df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng } 29546df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // Conservatively mark super-registers as unusable. 296396618b43a85e12d290a90b181c6af5d7c0c5f11Jakob Stoklund Olesen for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) 297396618b43a85e12d290a90b181c6af5d7c0c5f11Jakob Stoklund Olesen Classes[*SR] = reinterpret_cast<TargetRegisterClass *>(-1); 2982e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 2992e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 3002e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 3012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineOperand &MO = MI->getOperand(i); 3022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!MO.isReg()) continue; 3032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = MO.getReg(); 3042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Reg == 0) continue; 3052e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!MO.isUse()) continue; 3062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 307dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterClass *NewRC = nullptr; 3082e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (i < MI->getDesc().getNumOperands()) 309397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen NewRC = TII->getRegClass(MI->getDesc(), i, TRI, MF); 3102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 3112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // For now, only allow the register to be changed if its register 3122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // class is consistent across all uses. 3132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!Classes[Reg] && NewRC) 3142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = NewRC; 3152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin else if (!NewRC || Classes[Reg] != NewRC) 3162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 3172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 3182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RegRefs.insert(std::make_pair(Reg, &MO)); 3192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 320cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // FIXME: we should use an MCRegAliasIterator that includes self so we don't 321cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // have to repeat all this code for the reg itself. 322cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 3232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // It wasn't previously live but now it is, this is a kill. 3242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (KillIndices[Reg] == ~0u) { 3252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[Reg] = Count; 3262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[Reg] = ~0u; 3272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(((KillIndices[Reg] == ~0u) != 3282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (DefIndices[Reg] == ~0u)) && 3292e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Kill and Def maps aren't consistent for Reg!"); 3302e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 3312e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Repeat, for all aliases. 332396618b43a85e12d290a90b181c6af5d7c0c5f11Jakob Stoklund Olesen for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) { 333396618b43a85e12d290a90b181c6af5d7c0c5f11Jakob Stoklund Olesen unsigned AliasReg = *AI; 3342e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (KillIndices[AliasReg] == ~0u) { 3352e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[AliasReg] = Count; 3362e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[AliasReg] = ~0u; 3372e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 3382e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 3392e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 3402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 3412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 342bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// Check all machine operands that reference the antidependent register and must 343bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// be replaced by NewReg. Return true if any of their parent instructions may 344bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// clobber the new register. 345bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// 346bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// Note: AntiDepReg may be referenced by a two-address instruction such that 347bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// it's use operand is tied to a def operand. We guard against the case in which 348bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// the two-address instruction also defines NewReg, as may happen with 349bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// pre/postincrement loads. In this case, both the use and def operands are in 350bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// RegRefs because the def is inserted by PrescanInstruction and not erased 351cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines// during ScanInstruction. So checking for an instruction with definitions of 352bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick// both NewReg and AntiDepReg covers it. 35346388526963aba92344ee8ebd9e86d3556baa088Andrew Trickbool 354bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew TrickCriticalAntiDepBreaker::isNewRegClobberedByRefs(RegRefIter RegRefBegin, 355bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick RegRefIter RegRefEnd, 356bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick unsigned NewReg) 35746388526963aba92344ee8ebd9e86d3556baa088Andrew Trick{ 35846388526963aba92344ee8ebd9e86d3556baa088Andrew Trick for (RegRefIter I = RegRefBegin; I != RegRefEnd; ++I ) { 359bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick MachineOperand *RefOper = I->second; 360bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick 361bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // Don't allow the instruction defining AntiDepReg to earlyclobber its 362bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // operands, in case they may be assigned to NewReg. In this case antidep 363bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // breaking must fail, but it's too rare to bother optimizing. 364bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick if (RefOper->isDef() && RefOper->isEarlyClobber()) 36546388526963aba92344ee8ebd9e86d3556baa088Andrew Trick return true; 366bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick 367cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // Handle cases in which this instruction defines NewReg. 368bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick MachineInstr *MI = RefOper->getParent(); 369bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 370bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick const MachineOperand &CheckOper = MI->getOperand(i); 371bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick 372bbad2f1040fea671b4413f53b3fd816cb7bd2443Jakob Stoklund Olesen if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg)) 373bbad2f1040fea671b4413f53b3fd816cb7bd2443Jakob Stoklund Olesen return true; 374bbad2f1040fea671b4413f53b3fd816cb7bd2443Jakob Stoklund Olesen 375bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick if (!CheckOper.isReg() || !CheckOper.isDef() || 376bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick CheckOper.getReg() != NewReg) 377bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick continue; 378bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick 379bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // Don't allow the instruction to define NewReg and AntiDepReg. 380bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // When AntiDepReg is renamed it will be an illegal op. 381bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick if (RefOper->isDef()) 382bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick return true; 383bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick 384bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // Don't allow an instruction using AntiDepReg to be earlyclobbered by 385cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // NewReg. 386bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick if (CheckOper.isEarlyClobber()) 387bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick return true; 388bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick 389cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // Don't allow inline asm to define NewReg at all. Who knows what it's 390bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick // doing with it. 391bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick if (MI->isInlineAsm()) 392bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick return true; 393bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick } 39446388526963aba92344ee8ebd9e86d3556baa088Andrew Trick } 39546388526963aba92344ee8ebd9e86d3556baa088Andrew Trick return false; 39646388526963aba92344ee8ebd9e86d3556baa088Andrew Trick} 39746388526963aba92344ee8ebd9e86d3556baa088Andrew Trick 3985ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidtunsigned CriticalAntiDepBreaker:: 3995ff776bfde2dd5d993e51f8f78904ce331b5528cBill SchmidtfindSuitableFreeRegister(RegRefIter RegRefBegin, 4005ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt RegRefIter RegRefEnd, 4015ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt unsigned AntiDepReg, 4025ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt unsigned LastNewReg, 4035ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt const TargetRegisterClass *RC, 40478477ffdfd63ddf1ba22d9d2121c8f6ed9f9efa1Craig Topper SmallVectorImpl<unsigned> &Forbid) 4052973b57093b017f2e3b5f5edd0be9d4ea180f0e9Jim Grosbach{ 40639b5c0c049a19c7a7feffc9506da07923cc136e4Jakob Stoklund Olesen ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); 407fa796dd720f1b34596a043f17f098fac18ecc028Jakob Stoklund Olesen for (unsigned i = 0; i != Order.size(); ++i) { 408fa796dd720f1b34596a043f17f098fac18ecc028Jakob Stoklund Olesen unsigned NewReg = Order[i]; 4092e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Don't replace a register with itself. 4102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (NewReg == AntiDepReg) continue; 4112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Don't replace a register with one that was recently used to repair 4122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // an anti-dependence with this AntiDepReg, because that would 4132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // re-introduce that anti-dependence. 4142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (NewReg == LastNewReg) continue; 41546388526963aba92344ee8ebd9e86d3556baa088Andrew Trick // If any instructions that define AntiDepReg also define the NewReg, it's 41646388526963aba92344ee8ebd9e86d3556baa088Andrew Trick // not suitable. For example, Instruction with multiple definitions can 41746388526963aba92344ee8ebd9e86d3556baa088Andrew Trick // result in this condition. 418bc4bd92d52be2f6707a8c311873ded27a8f2481fAndrew Trick if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue; 4192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If NewReg is dead and NewReg's most recent def is not before 4202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg. 4212973b57093b017f2e3b5f5edd0be9d4ea180f0e9Jim Grosbach assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) 4222973b57093b017f2e3b5f5edd0be9d4ea180f0e9Jim Grosbach && "Kill and Def maps aren't consistent for AntiDepReg!"); 4232973b57093b017f2e3b5f5edd0be9d4ea180f0e9Jim Grosbach assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) 4242973b57093b017f2e3b5f5edd0be9d4ea180f0e9Jim Grosbach && "Kill and Def maps aren't consistent for NewReg!"); 4252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (KillIndices[NewReg] != ~0u || 4262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) || 4272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[AntiDepReg] > DefIndices[NewReg]) 4282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin continue; 4295ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt // If NewReg overlaps any of the forbidden registers, we can't use it. 4305ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt bool Forbidden = false; 431f22fd3f7b557a967b1edc1fa9ae770006a39e97cCraig Topper for (SmallVectorImpl<unsigned>::iterator it = Forbid.begin(), 4325ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt ite = Forbid.end(); it != ite; ++it) 4335ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt if (TRI->regsOverlap(NewReg, *it)) { 4345ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt Forbidden = true; 4355ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt break; 4365ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt } 4375ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt if (Forbidden) continue; 4382e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin return NewReg; 4392e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 4402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // No registers are free and available! 4422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin return 0; 4432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 4442e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4452e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwinunsigned CriticalAntiDepBreaker:: 44666db3a0f10e96ae190c8a46a1a8d5242928d068cDan GohmanBreakAntiDependencies(const std::vector<SUnit>& SUnits, 44766db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman MachineBasicBlock::iterator Begin, 44866db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman MachineBasicBlock::iterator End, 449e29e8e100ea38be1771e5f010a5511cbb990d515Devang Patel unsigned InsertPosIndex, 450e29e8e100ea38be1771e5f010a5511cbb990d515Devang Patel DbgValueVector &DbgValues) { 4512e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // The code below assumes that there is at least one instruction, 4522e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // so just duck out immediately if the block is empty. 4532e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (SUnits.empty()) return 0; 4542e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 455533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach // Keep a map of the MachineInstr*'s back to the SUnit representing them. 456533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach // This is used for updating debug information. 457b4566a999970b514d7c6973d99e293a6625d3f70Andrew Trick // 458b4566a999970b514d7c6973d99e293a6625d3f70Andrew Trick // FIXME: Replace this with the existing map in ScheduleDAGInstrs::MISUnitMap 459533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach DenseMap<MachineInstr*,const SUnit*> MISUnitMap; 460533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach 4612e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Find the node at the bottom of the critical path. 462dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const SUnit *Max = nullptr; 4632e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned i = 0, e = SUnits.size(); i != e; ++i) { 46466db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman const SUnit *SU = &SUnits[i]; 465533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach MISUnitMap[SU->getInstr()] = SU; 4662e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency) 4672e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Max = SU; 4682e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 4692e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4702e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#ifndef NDEBUG 4712e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin { 47289d6a2426256b56780c7934ddad24e6ecc4f690aDavid Greene DEBUG(dbgs() << "Critical path has total latency " 4732e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin << (Max->getDepth() + Max->Latency) << "\n"); 47489d6a2426256b56780c7934ddad24e6ecc4f690aDavid Greene DEBUG(dbgs() << "Available regs:"); 4752e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) { 4762e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (KillIndices[Reg] == ~0u) 47789d6a2426256b56780c7934ddad24e6ecc4f690aDavid Greene DEBUG(dbgs() << " " << TRI->getName(Reg)); 4782e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 47989d6a2426256b56780c7934ddad24e6ecc4f690aDavid Greene DEBUG(dbgs() << '\n'); 4802e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 4812e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin#endif 4822e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4832e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Track progress along the critical path through the SUnit graph as we walk 4842e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // the instructions. 48566db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman const SUnit *CriticalPathSU = Max; 4862e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineInstr *CriticalPathMI = CriticalPathSU->getInstr(); 4872e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 4882e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Consider this pattern: 4892e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 4902e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 4912e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 4922e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 4932e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 4942e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 4952e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 4962e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 4972e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // There are three anti-dependencies here, and without special care, 4982e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // we'd break all of them using the same register: 4992e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 5002e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 5012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 5022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 5032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 5042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 5052e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 5062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 5072e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // because at each anti-dependence, B is the first register that 5082e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // isn't A which is free. This re-introduces anti-dependencies 5092e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // at all but one of the original anti-dependencies that we were 5102e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // trying to break. To avoid this, keep track of the most recent 5112e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // register that each register was replaced with, avoid 5122e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // using it to repair an anti-dependence on the same register. 5132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // This lets us produce this: 5142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // A = ... 5152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = A 5162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 5172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 5182e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // C = ... 5192e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = C 5202e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // B = ... 5212e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // ... = B 5222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // This still has an anti-dependence on B, but at least it isn't on the 5232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // original critical path. 5242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // 5252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // TODO: If we tracked more than one register here, we could potentially 5262e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // fix that remaining critical edge too. This is a little more involved, 5272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // because unlike the most recent register, less recent registers should 5282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // still be considered, though only if no other registers are available. 5299c2a034730b289a2cf48bc91aa2ef69737a7afbbBill Wendling std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0); 5302e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5312e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Attempt to break anti-dependence edges on the critical path. Walk the 5322e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // instructions from the bottom up, tracking information about liveness 5332e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // as we go to help determine which registers are available. 5342e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Broken = 0; 5352e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Count = InsertPosIndex - 1; 536cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines for (MachineBasicBlock::iterator I = End, E = Begin; I != E; --Count) { 5372e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineInstr *MI = --I; 53822c310d78ce9630af15b0de94c18a409705b7496Tim Murray // Kill instructions can define registers but are really nops, and there 53922c310d78ce9630af15b0de94c18a409705b7496Tim Murray // might be a real definition earlier that needs to be paired with uses 54022c310d78ce9630af15b0de94c18a409705b7496Tim Murray // dominated by this kill. 54122c310d78ce9630af15b0de94c18a409705b7496Tim Murray 54222c310d78ce9630af15b0de94c18a409705b7496Tim Murray // FIXME: It may be possible to remove the isKill() restriction once PR18663 54322c310d78ce9630af15b0de94c18a409705b7496Tim Murray // has been properly fixed. There can be value in processing kills as seen 54422c310d78ce9630af15b0de94c18a409705b7496Tim Murray // in the AggressiveAntiDepBreaker class. 54522c310d78ce9630af15b0de94c18a409705b7496Tim Murray if (MI->isDebugValue() || MI->isKill()) 546b0812f114b83a32c4b90a4b553c7177c557558b5Dale Johannesen continue; 5472e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5482e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Check if this instruction has a dependence on the critical path that 5492e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // is an anti-dependence that we may be able to break. If it is, set 5502e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // AntiDepReg to the non-zero register associated with the anti-dependence. 5512e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // 5522e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // We limit our attention to the critical path as a heuristic to avoid 5532e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // breaking anti-dependence edges that aren't going to significantly 5542e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // impact the overall schedule. There are a limited number of registers 5552e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // and we want to save them for the important edges. 55601384ef159caa7eebff0e1d703638f2e2c862092Jim Grosbach // 5572e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // TODO: Instructions with multiple defs could have multiple 5582e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // anti-dependencies. The current code here only knows how to break one 5592e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // edge per instruction. Note that we'd have to be able to break all of 5602e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // the anti-dependencies in an instruction in order to be effective. 5612e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned AntiDepReg = 0; 5622e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (MI == CriticalPathMI) { 56366db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) { 56466db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman const SUnit *NextSU = Edge->getSUnit(); 5652e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 5662e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Only consider anti-dependence edges. 5672e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Edge->getKind() == SDep::Anti) { 5682e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = Edge->getReg(); 5692e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(AntiDepReg != 0 && "Anti-dependence on reg0?"); 57014d1dd95c7c969e07defebb6fe65df2fae1b30cfJakob Stoklund Olesen if (!MRI.isAllocatable(AntiDepReg)) 5712e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Don't break anti-dependencies on non-allocatable registers. 5722e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 573cff4ad768ec721b72498dc6b605d882e36c1fb14Benjamin Kramer else if (KeepRegs.test(AntiDepReg)) 574cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines // Don't break anti-dependencies if a use down below requires 5752e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // this exact register. 5762e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 5772e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin else { 5782e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If the SUnit has other dependencies on the SUnit that it 5792e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // anti-depends on, don't bother breaking the anti-dependency 5802e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // since those edges would prevent such units from being 5812e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // scheduled past each other regardless. 5822e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // 5832e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Also, if there are dependencies on other SUnits with the 5842e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // same register as the anti-dependency, don't attempt to 5852e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // break it. 58666db3a0f10e96ae190c8a46a1a8d5242928d068cDan Gohman for (SUnit::const_pred_iterator P = CriticalPathSU->Preds.begin(), 5872e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin PE = CriticalPathSU->Preds.end(); P != PE; ++P) 5882e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (P->getSUnit() == NextSU ? 5892e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) : 5902e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) { 5912e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 5922e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin break; 5932e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 5942e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 5952e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 5962e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin CriticalPathSU = NextSU; 5972e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin CriticalPathMI = CriticalPathSU->getInstr(); 5982e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } else { 5992e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // We've reached the end of the critical path. 600dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines CriticalPathSU = nullptr; 601dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines CriticalPathMI = nullptr; 6022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 6032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 6042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 6052e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin PrescanInstruction(MI); 6062e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 6075ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt SmallVector<unsigned, 2> ForbidRegs; 6085ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt 60946df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // If MI's defs have a special allocation requirement, don't allow 61046df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // any def registers to be changed. Also assume all registers 61146df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng // defined in a call must not be changed (ABI). 612cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(MI)) 6132e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If this instruction's defs have special allocation requirement, don't 6142e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // break this anti-dependency. 6152e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 6162e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin else if (AntiDepReg) { 6172e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // If this instruction has a use of AntiDepReg, breaking it 6185ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt // is invalid. If the instruction defines other registers, 6195ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt // save a list of them so that we don't pick a new register 6205ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt // that overlaps any of them. 6212e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 6222e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin MachineOperand &MO = MI->getOperand(i); 6232e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (!MO.isReg()) continue; 6242e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin unsigned Reg = MO.getReg(); 6252e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (Reg == 0) continue; 62646df4eb46e784036cf895db271fe29e1cf2a975aEvan Cheng if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { 6272e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 6282e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin break; 6292e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 6305ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt if (MO.isDef() && Reg != AntiDepReg) 6315ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt ForbidRegs.push_back(Reg); 6322e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 6332e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 6342e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 6352e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Determine AntiDepReg's register class, if it is live and is 6362e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // consistently used within a single class. 637dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] 638dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : nullptr; 639dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines assert((AntiDepReg == 0 || RC != nullptr) && 6402e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Register should be live if it's causing an anti-dependence!"); 6412e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (RC == reinterpret_cast<TargetRegisterClass *>(-1)) 6422e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin AntiDepReg = 0; 6432e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 64436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // Look for a suitable register to use to break the anti-dependence. 6452e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // 6462e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // TODO: Instead of picking the first free register, consider which might 6472e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // be the best. 6482e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin if (AntiDepReg != 0) { 64946388526963aba92344ee8ebd9e86d3556baa088Andrew Trick std::pair<std::multimap<unsigned, MachineOperand *>::iterator, 65046388526963aba92344ee8ebd9e86d3556baa088Andrew Trick std::multimap<unsigned, MachineOperand *>::iterator> 65146388526963aba92344ee8ebd9e86d3556baa088Andrew Trick Range = RegRefs.equal_range(AntiDepReg); 65246388526963aba92344ee8ebd9e86d3556baa088Andrew Trick if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second, 65346388526963aba92344ee8ebd9e86d3556baa088Andrew Trick AntiDepReg, 6542e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin LastNewReg[AntiDepReg], 6555ff776bfde2dd5d993e51f8f78904ce331b5528cBill Schmidt RC, ForbidRegs)) { 65689d6a2426256b56780c7934ddad24e6ecc4f690aDavid Greene DEBUG(dbgs() << "Breaking anti-dependence edge on " 6572e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin << TRI->getName(AntiDepReg) 6582e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin << " with " << RegRefs.count(AntiDepReg) << " references" 6592e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin << " using " << TRI->getName(NewReg) << "!\n"); 6602e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 6612e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // Update the references to the old register to refer to the new 6622e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // register. 6632e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin for (std::multimap<unsigned, MachineOperand *>::iterator 664533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach Q = Range.first, QE = Range.second; Q != QE; ++Q) { 6652e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Q->second->setReg(NewReg); 666533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach // If the SU for the instruction being updated has debug information 667533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach // related to the anti-dependency register, make sure to update that 668533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach // as well. 669533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach const SUnit *SU = MISUnitMap[Q->second->getParent()]; 670086723d244952aee690a8aa39485a0fa0d3a7700Jim Grosbach if (!SU) continue; 671e29e8e100ea38be1771e5f010a5511cbb990d515Devang Patel for (DbgValueVector::iterator DVI = DbgValues.begin(), 672e29e8e100ea38be1771e5f010a5511cbb990d515Devang Patel DVE = DbgValues.end(); DVI != DVE; ++DVI) 673e29e8e100ea38be1771e5f010a5511cbb990d515Devang Patel if (DVI->second == Q->second->getParent()) 674e29e8e100ea38be1771e5f010a5511cbb990d515Devang Patel UpdateDbgValue(DVI->first, AntiDepReg, NewReg); 675533934e06e99a86e8c93f8ec9b9d3b2c527b747eJim Grosbach } 6762e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 6772e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // We just went back in time and modified history; the 678f70007e89e7b252abc9dc175aab92191c09bebf7Bob Wilson // liveness information for the anti-dependence reg is now 6792e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin // inconsistent. Set the state as if it were dead. 6802e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin Classes[NewReg] = Classes[AntiDepReg]; 6812e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[NewReg] = DefIndices[AntiDepReg]; 6822e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[NewReg] = KillIndices[AntiDepReg]; 6832e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(((KillIndices[NewReg] == ~0u) != 6842e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (DefIndices[NewReg] == ~0u)) && 6852e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Kill and Def maps aren't consistent for NewReg!"); 6862e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 687dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Classes[AntiDepReg] = nullptr; 6882e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin DefIndices[AntiDepReg] = KillIndices[AntiDepReg]; 6892e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin KillIndices[AntiDepReg] = ~0u; 6902e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin assert(((KillIndices[AntiDepReg] == ~0u) != 6912e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin (DefIndices[AntiDepReg] == ~0u)) && 6922e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin "Kill and Def maps aren't consistent for AntiDepReg!"); 6932e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 6942e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin RegRefs.erase(AntiDepReg); 6952e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin LastNewReg[AntiDepReg] = NewReg; 6962e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin ++Broken; 6972e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 6982e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 6992e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 7002e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin ScanInstruction(MI, Count); 7012e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin } 7022e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin 7032e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin return Broken; 7042e7be612d5d0eb42ee3ae08194dbb03b750cc6bfDavid Goodwin} 705