MachineBasicBlock.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Collect the sequence of machine instructions for a basic block. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineBasicBlock.h" 15#include "llvm/ADT/SmallPtrSet.h" 16#include "llvm/ADT/SmallString.h" 17#include "llvm/CodeGen/LiveIntervalAnalysis.h" 18#include "llvm/CodeGen/LiveVariables.h" 19#include "llvm/CodeGen/MachineDominators.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineLoopInfo.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/CodeGen/SlotIndexes.h" 25#include "llvm/IR/BasicBlock.h" 26#include "llvm/IR/DataLayout.h" 27#include "llvm/IR/LeakDetector.h" 28#include "llvm/MC/MCAsmInfo.h" 29#include "llvm/MC/MCContext.h" 30#include "llvm/Support/Debug.h" 31#include "llvm/Support/raw_ostream.h" 32#include "llvm/Target/TargetInstrInfo.h" 33#include "llvm/Target/TargetMachine.h" 34#include "llvm/Target/TargetRegisterInfo.h" 35#include <algorithm> 36using namespace llvm; 37 38MachineBasicBlock::MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb) 39 : BB(bb), Number(-1), xParent(&mf), Alignment(0), IsLandingPad(false), 40 AddressTaken(false), CachedMCSymbol(NULL) { 41 Insts.Parent = this; 42} 43 44MachineBasicBlock::~MachineBasicBlock() { 45 LeakDetector::removeGarbageObject(this); 46} 47 48/// getSymbol - Return the MCSymbol for this basic block. 49/// 50MCSymbol *MachineBasicBlock::getSymbol() const { 51 if (!CachedMCSymbol) { 52 const MachineFunction *MF = getParent(); 53 MCContext &Ctx = MF->getContext(); 54 const TargetMachine &TM = MF->getTarget(); 55 const char *Prefix = TM.getDataLayout()->getPrivateGlobalPrefix(); 56 CachedMCSymbol = Ctx.GetOrCreateSymbol(Twine(Prefix) + "BB" + 57 Twine(MF->getFunctionNumber()) + 58 "_" + Twine(getNumber())); 59 } 60 61 return CachedMCSymbol; 62} 63 64 65raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) { 66 MBB.print(OS); 67 return OS; 68} 69 70/// addNodeToList (MBB) - When an MBB is added to an MF, we need to update the 71/// parent pointer of the MBB, the MBB numbering, and any instructions in the 72/// MBB to be on the right operand list for registers. 73/// 74/// MBBs start out as #-1. When a MBB is added to a MachineFunction, it 75/// gets the next available unique MBB number. If it is removed from a 76/// MachineFunction, it goes back to being #-1. 77void ilist_traits<MachineBasicBlock>::addNodeToList(MachineBasicBlock *N) { 78 MachineFunction &MF = *N->getParent(); 79 N->Number = MF.addToMBBNumbering(N); 80 81 // Make sure the instructions have their operands in the reginfo lists. 82 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 83 for (MachineBasicBlock::instr_iterator 84 I = N->instr_begin(), E = N->instr_end(); I != E; ++I) 85 I->AddRegOperandsToUseLists(RegInfo); 86 87 LeakDetector::removeGarbageObject(N); 88} 89 90void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock *N) { 91 N->getParent()->removeFromMBBNumbering(N->Number); 92 N->Number = -1; 93 LeakDetector::addGarbageObject(N); 94} 95 96 97/// addNodeToList (MI) - When we add an instruction to a basic block 98/// list, we update its parent pointer and add its operands from reg use/def 99/// lists if appropriate. 100void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) { 101 assert(N->getParent() == 0 && "machine instruction already in a basic block"); 102 N->setParent(Parent); 103 104 // Add the instruction's register operands to their corresponding 105 // use/def lists. 106 MachineFunction *MF = Parent->getParent(); 107 N->AddRegOperandsToUseLists(MF->getRegInfo()); 108 109 LeakDetector::removeGarbageObject(N); 110} 111 112/// removeNodeFromList (MI) - When we remove an instruction from a basic block 113/// list, we update its parent pointer and remove its operands from reg use/def 114/// lists if appropriate. 115void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) { 116 assert(N->getParent() != 0 && "machine instruction not in a basic block"); 117 118 // Remove from the use/def lists. 119 if (MachineFunction *MF = N->getParent()->getParent()) 120 N->RemoveRegOperandsFromUseLists(MF->getRegInfo()); 121 122 N->setParent(0); 123 124 LeakDetector::addGarbageObject(N); 125} 126 127/// transferNodesFromList (MI) - When moving a range of instructions from one 128/// MBB list to another, we need to update the parent pointers and the use/def 129/// lists. 130void ilist_traits<MachineInstr>:: 131transferNodesFromList(ilist_traits<MachineInstr> &fromList, 132 ilist_iterator<MachineInstr> first, 133 ilist_iterator<MachineInstr> last) { 134 assert(Parent->getParent() == fromList.Parent->getParent() && 135 "MachineInstr parent mismatch!"); 136 137 // Splice within the same MBB -> no change. 138 if (Parent == fromList.Parent) return; 139 140 // If splicing between two blocks within the same function, just update the 141 // parent pointers. 142 for (; first != last; ++first) 143 first->setParent(Parent); 144} 145 146void ilist_traits<MachineInstr>::deleteNode(MachineInstr* MI) { 147 assert(!MI->getParent() && "MI is still in a block!"); 148 Parent->getParent()->DeleteMachineInstr(MI); 149} 150 151MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() { 152 instr_iterator I = instr_begin(), E = instr_end(); 153 while (I != E && I->isPHI()) 154 ++I; 155 assert((I == E || !I->isInsideBundle()) && 156 "First non-phi MI cannot be inside a bundle!"); 157 return I; 158} 159 160MachineBasicBlock::iterator 161MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) { 162 iterator E = end(); 163 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue())) 164 ++I; 165 // FIXME: This needs to change if we wish to bundle labels / dbg_values 166 // inside the bundle. 167 assert((I == E || !I->isInsideBundle()) && 168 "First non-phi / non-label instruction is inside a bundle!"); 169 return I; 170} 171 172MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() { 173 iterator B = begin(), E = end(), I = E; 174 while (I != B && ((--I)->isTerminator() || I->isDebugValue())) 175 ; /*noop */ 176 while (I != E && !I->isTerminator()) 177 ++I; 178 return I; 179} 180 181MachineBasicBlock::const_iterator 182MachineBasicBlock::getFirstTerminator() const { 183 const_iterator B = begin(), E = end(), I = E; 184 while (I != B && ((--I)->isTerminator() || I->isDebugValue())) 185 ; /*noop */ 186 while (I != E && !I->isTerminator()) 187 ++I; 188 return I; 189} 190 191MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() { 192 instr_iterator B = instr_begin(), E = instr_end(), I = E; 193 while (I != B && ((--I)->isTerminator() || I->isDebugValue())) 194 ; /*noop */ 195 while (I != E && !I->isTerminator()) 196 ++I; 197 return I; 198} 199 200MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() { 201 // Skip over end-of-block dbg_value instructions. 202 instr_iterator B = instr_begin(), I = instr_end(); 203 while (I != B) { 204 --I; 205 // Return instruction that starts a bundle. 206 if (I->isDebugValue() || I->isInsideBundle()) 207 continue; 208 return I; 209 } 210 // The block is all debug values. 211 return end(); 212} 213 214MachineBasicBlock::const_iterator 215MachineBasicBlock::getLastNonDebugInstr() const { 216 // Skip over end-of-block dbg_value instructions. 217 const_instr_iterator B = instr_begin(), I = instr_end(); 218 while (I != B) { 219 --I; 220 // Return instruction that starts a bundle. 221 if (I->isDebugValue() || I->isInsideBundle()) 222 continue; 223 return I; 224 } 225 // The block is all debug values. 226 return end(); 227} 228 229const MachineBasicBlock *MachineBasicBlock::getLandingPadSuccessor() const { 230 // A block with a landing pad successor only has one other successor. 231 if (succ_size() > 2) 232 return 0; 233 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I) 234 if ((*I)->isLandingPad()) 235 return *I; 236 return 0; 237} 238 239#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 240void MachineBasicBlock::dump() const { 241 print(dbgs()); 242} 243#endif 244 245StringRef MachineBasicBlock::getName() const { 246 if (const BasicBlock *LBB = getBasicBlock()) 247 return LBB->getName(); 248 else 249 return "(null)"; 250} 251 252/// Return a hopefully unique identifier for this block. 253std::string MachineBasicBlock::getFullName() const { 254 std::string Name; 255 if (getParent()) 256 Name = (getParent()->getName() + ":").str(); 257 if (getBasicBlock()) 258 Name += getBasicBlock()->getName(); 259 else 260 Name += (Twine("BB") + Twine(getNumber())).str(); 261 return Name; 262} 263 264void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const { 265 const MachineFunction *MF = getParent(); 266 if (!MF) { 267 OS << "Can't print out MachineBasicBlock because parent MachineFunction" 268 << " is null\n"; 269 return; 270 } 271 272 if (Indexes) 273 OS << Indexes->getMBBStartIdx(this) << '\t'; 274 275 OS << "BB#" << getNumber() << ": "; 276 277 const char *Comma = ""; 278 if (const BasicBlock *LBB = getBasicBlock()) { 279 OS << Comma << "derived from LLVM BB "; 280 LBB->printAsOperand(OS, /*PrintType=*/false); 281 Comma = ", "; 282 } 283 if (isLandingPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; } 284 if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; } 285 if (Alignment) 286 OS << Comma << "Align " << Alignment << " (" << (1u << Alignment) 287 << " bytes)"; 288 289 OS << '\n'; 290 291 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 292 if (!livein_empty()) { 293 if (Indexes) OS << '\t'; 294 OS << " Live Ins:"; 295 for (livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I) 296 OS << ' ' << PrintReg(*I, TRI); 297 OS << '\n'; 298 } 299 // Print the preds of this block according to the CFG. 300 if (!pred_empty()) { 301 if (Indexes) OS << '\t'; 302 OS << " Predecessors according to CFG:"; 303 for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI) 304 OS << " BB#" << (*PI)->getNumber(); 305 OS << '\n'; 306 } 307 308 for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) { 309 if (Indexes) { 310 if (Indexes->hasIndex(I)) 311 OS << Indexes->getInstructionIndex(I); 312 OS << '\t'; 313 } 314 OS << '\t'; 315 if (I->isInsideBundle()) 316 OS << " * "; 317 I->print(OS, &getParent()->getTarget()); 318 } 319 320 // Print the successors of this block according to the CFG. 321 if (!succ_empty()) { 322 if (Indexes) OS << '\t'; 323 OS << " Successors according to CFG:"; 324 for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) { 325 OS << " BB#" << (*SI)->getNumber(); 326 if (!Weights.empty()) 327 OS << '(' << *getWeightIterator(SI) << ')'; 328 } 329 OS << '\n'; 330 } 331} 332 333void MachineBasicBlock::printAsOperand(raw_ostream &OS, bool /*PrintType*/) { 334 OS << "BB#" << getNumber(); 335} 336 337void MachineBasicBlock::removeLiveIn(unsigned Reg) { 338 std::vector<unsigned>::iterator I = 339 std::find(LiveIns.begin(), LiveIns.end(), Reg); 340 if (I != LiveIns.end()) 341 LiveIns.erase(I); 342} 343 344bool MachineBasicBlock::isLiveIn(unsigned Reg) const { 345 livein_iterator I = std::find(livein_begin(), livein_end(), Reg); 346 return I != livein_end(); 347} 348 349unsigned 350MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) { 351 assert(getParent() && "MBB must be inserted in function"); 352 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg"); 353 assert(RC && "Register class is required"); 354 assert((isLandingPad() || this == &getParent()->front()) && 355 "Only the entry block and landing pads can have physreg live ins"); 356 357 bool LiveIn = isLiveIn(PhysReg); 358 iterator I = SkipPHIsAndLabels(begin()), E = end(); 359 MachineRegisterInfo &MRI = getParent()->getRegInfo(); 360 const TargetInstrInfo &TII = *getParent()->getTarget().getInstrInfo(); 361 362 // Look for an existing copy. 363 if (LiveIn) 364 for (;I != E && I->isCopy(); ++I) 365 if (I->getOperand(1).getReg() == PhysReg) { 366 unsigned VirtReg = I->getOperand(0).getReg(); 367 if (!MRI.constrainRegClass(VirtReg, RC)) 368 llvm_unreachable("Incompatible live-in register class."); 369 return VirtReg; 370 } 371 372 // No luck, create a virtual register. 373 unsigned VirtReg = MRI.createVirtualRegister(RC); 374 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg) 375 .addReg(PhysReg, RegState::Kill); 376 if (!LiveIn) 377 addLiveIn(PhysReg); 378 return VirtReg; 379} 380 381void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) { 382 getParent()->splice(NewAfter, this); 383} 384 385void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) { 386 MachineFunction::iterator BBI = NewBefore; 387 getParent()->splice(++BBI, this); 388} 389 390void MachineBasicBlock::updateTerminator() { 391 const TargetInstrInfo *TII = getParent()->getTarget().getInstrInfo(); 392 // A block with no successors has no concerns with fall-through edges. 393 if (this->succ_empty()) return; 394 395 MachineBasicBlock *TBB = 0, *FBB = 0; 396 SmallVector<MachineOperand, 4> Cond; 397 DebugLoc dl; // FIXME: this is nowhere 398 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond); 399 (void) B; 400 assert(!B && "UpdateTerminators requires analyzable predecessors!"); 401 if (Cond.empty()) { 402 if (TBB) { 403 // The block has an unconditional branch. If its successor is now 404 // its layout successor, delete the branch. 405 if (isLayoutSuccessor(TBB)) 406 TII->RemoveBranch(*this); 407 } else { 408 // The block has an unconditional fallthrough. If its successor is not 409 // its layout successor, insert a branch. First we have to locate the 410 // only non-landing-pad successor, as that is the fallthrough block. 411 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) { 412 if ((*SI)->isLandingPad()) 413 continue; 414 assert(!TBB && "Found more than one non-landing-pad successor!"); 415 TBB = *SI; 416 } 417 418 // If there is no non-landing-pad successor, the block has no 419 // fall-through edges to be concerned with. 420 if (!TBB) 421 return; 422 423 // Finally update the unconditional successor to be reached via a branch 424 // if it would not be reached by fallthrough. 425 if (!isLayoutSuccessor(TBB)) 426 TII->InsertBranch(*this, TBB, 0, Cond, dl); 427 } 428 } else { 429 if (FBB) { 430 // The block has a non-fallthrough conditional branch. If one of its 431 // successors is its layout successor, rewrite it to a fallthrough 432 // conditional branch. 433 if (isLayoutSuccessor(TBB)) { 434 if (TII->ReverseBranchCondition(Cond)) 435 return; 436 TII->RemoveBranch(*this); 437 TII->InsertBranch(*this, FBB, 0, Cond, dl); 438 } else if (isLayoutSuccessor(FBB)) { 439 TII->RemoveBranch(*this); 440 TII->InsertBranch(*this, TBB, 0, Cond, dl); 441 } 442 } else { 443 // Walk through the successors and find the successor which is not 444 // a landing pad and is not the conditional branch destination (in TBB) 445 // as the fallthrough successor. 446 MachineBasicBlock *FallthroughBB = 0; 447 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) { 448 if ((*SI)->isLandingPad() || *SI == TBB) 449 continue; 450 assert(!FallthroughBB && "Found more than one fallthrough successor."); 451 FallthroughBB = *SI; 452 } 453 if (!FallthroughBB && canFallThrough()) { 454 // We fallthrough to the same basic block as the conditional jump 455 // targets. Remove the conditional jump, leaving unconditional 456 // fallthrough. 457 // FIXME: This does not seem like a reasonable pattern to support, but it 458 // has been seen in the wild coming out of degenerate ARM test cases. 459 TII->RemoveBranch(*this); 460 461 // Finally update the unconditional successor to be reached via a branch 462 // if it would not be reached by fallthrough. 463 if (!isLayoutSuccessor(TBB)) 464 TII->InsertBranch(*this, TBB, 0, Cond, dl); 465 return; 466 } 467 468 // The block has a fallthrough conditional branch. 469 if (isLayoutSuccessor(TBB)) { 470 if (TII->ReverseBranchCondition(Cond)) { 471 // We can't reverse the condition, add an unconditional branch. 472 Cond.clear(); 473 TII->InsertBranch(*this, FallthroughBB, 0, Cond, dl); 474 return; 475 } 476 TII->RemoveBranch(*this); 477 TII->InsertBranch(*this, FallthroughBB, 0, Cond, dl); 478 } else if (!isLayoutSuccessor(FallthroughBB)) { 479 TII->RemoveBranch(*this); 480 TII->InsertBranch(*this, TBB, FallthroughBB, Cond, dl); 481 } 482 } 483 } 484} 485 486void MachineBasicBlock::addSuccessor(MachineBasicBlock *succ, uint32_t weight) { 487 488 // If we see non-zero value for the first time it means we actually use Weight 489 // list, so we fill all Weights with 0's. 490 if (weight != 0 && Weights.empty()) 491 Weights.resize(Successors.size()); 492 493 if (weight != 0 || !Weights.empty()) 494 Weights.push_back(weight); 495 496 Successors.push_back(succ); 497 succ->addPredecessor(this); 498 } 499 500void MachineBasicBlock::removeSuccessor(MachineBasicBlock *succ) { 501 succ->removePredecessor(this); 502 succ_iterator I = std::find(Successors.begin(), Successors.end(), succ); 503 assert(I != Successors.end() && "Not a current successor!"); 504 505 // If Weight list is empty it means we don't use it (disabled optimization). 506 if (!Weights.empty()) { 507 weight_iterator WI = getWeightIterator(I); 508 Weights.erase(WI); 509 } 510 511 Successors.erase(I); 512} 513 514MachineBasicBlock::succ_iterator 515MachineBasicBlock::removeSuccessor(succ_iterator I) { 516 assert(I != Successors.end() && "Not a current successor!"); 517 518 // If Weight list is empty it means we don't use it (disabled optimization). 519 if (!Weights.empty()) { 520 weight_iterator WI = getWeightIterator(I); 521 Weights.erase(WI); 522 } 523 524 (*I)->removePredecessor(this); 525 return Successors.erase(I); 526} 527 528void MachineBasicBlock::replaceSuccessor(MachineBasicBlock *Old, 529 MachineBasicBlock *New) { 530 if (Old == New) 531 return; 532 533 succ_iterator E = succ_end(); 534 succ_iterator NewI = E; 535 succ_iterator OldI = E; 536 for (succ_iterator I = succ_begin(); I != E; ++I) { 537 if (*I == Old) { 538 OldI = I; 539 if (NewI != E) 540 break; 541 } 542 if (*I == New) { 543 NewI = I; 544 if (OldI != E) 545 break; 546 } 547 } 548 assert(OldI != E && "Old is not a successor of this block"); 549 Old->removePredecessor(this); 550 551 // If New isn't already a successor, let it take Old's place. 552 if (NewI == E) { 553 New->addPredecessor(this); 554 *OldI = New; 555 return; 556 } 557 558 // New is already a successor. 559 // Update its weight instead of adding a duplicate edge. 560 if (!Weights.empty()) { 561 weight_iterator OldWI = getWeightIterator(OldI); 562 *getWeightIterator(NewI) += *OldWI; 563 Weights.erase(OldWI); 564 } 565 Successors.erase(OldI); 566} 567 568void MachineBasicBlock::addPredecessor(MachineBasicBlock *pred) { 569 Predecessors.push_back(pred); 570} 571 572void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) { 573 pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), pred); 574 assert(I != Predecessors.end() && "Pred is not a predecessor of this block!"); 575 Predecessors.erase(I); 576} 577 578void MachineBasicBlock::transferSuccessors(MachineBasicBlock *fromMBB) { 579 if (this == fromMBB) 580 return; 581 582 while (!fromMBB->succ_empty()) { 583 MachineBasicBlock *Succ = *fromMBB->succ_begin(); 584 uint32_t Weight = 0; 585 586 // If Weight list is empty it means we don't use it (disabled optimization). 587 if (!fromMBB->Weights.empty()) 588 Weight = *fromMBB->Weights.begin(); 589 590 addSuccessor(Succ, Weight); 591 fromMBB->removeSuccessor(Succ); 592 } 593} 594 595void 596MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB) { 597 if (this == fromMBB) 598 return; 599 600 while (!fromMBB->succ_empty()) { 601 MachineBasicBlock *Succ = *fromMBB->succ_begin(); 602 uint32_t Weight = 0; 603 if (!fromMBB->Weights.empty()) 604 Weight = *fromMBB->Weights.begin(); 605 addSuccessor(Succ, Weight); 606 fromMBB->removeSuccessor(Succ); 607 608 // Fix up any PHI nodes in the successor. 609 for (MachineBasicBlock::instr_iterator MI = Succ->instr_begin(), 610 ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI) 611 for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) { 612 MachineOperand &MO = MI->getOperand(i); 613 if (MO.getMBB() == fromMBB) 614 MO.setMBB(this); 615 } 616 } 617} 618 619bool MachineBasicBlock::isPredecessor(const MachineBasicBlock *MBB) const { 620 return std::find(pred_begin(), pred_end(), MBB) != pred_end(); 621} 622 623bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const { 624 return std::find(succ_begin(), succ_end(), MBB) != succ_end(); 625} 626 627bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const { 628 MachineFunction::const_iterator I(this); 629 return std::next(I) == MachineFunction::const_iterator(MBB); 630} 631 632bool MachineBasicBlock::canFallThrough() { 633 MachineFunction::iterator Fallthrough = this; 634 ++Fallthrough; 635 // If FallthroughBlock is off the end of the function, it can't fall through. 636 if (Fallthrough == getParent()->end()) 637 return false; 638 639 // If FallthroughBlock isn't a successor, no fallthrough is possible. 640 if (!isSuccessor(Fallthrough)) 641 return false; 642 643 // Analyze the branches, if any, at the end of the block. 644 MachineBasicBlock *TBB = 0, *FBB = 0; 645 SmallVector<MachineOperand, 4> Cond; 646 const TargetInstrInfo *TII = getParent()->getTarget().getInstrInfo(); 647 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) { 648 // If we couldn't analyze the branch, examine the last instruction. 649 // If the block doesn't end in a known control barrier, assume fallthrough 650 // is possible. The isPredicated check is needed because this code can be 651 // called during IfConversion, where an instruction which is normally a 652 // Barrier is predicated and thus no longer an actual control barrier. 653 return empty() || !back().isBarrier() || TII->isPredicated(&back()); 654 } 655 656 // If there is no branch, control always falls through. 657 if (TBB == 0) return true; 658 659 // If there is some explicit branch to the fallthrough block, it can obviously 660 // reach, even though the branch should get folded to fall through implicitly. 661 if (MachineFunction::iterator(TBB) == Fallthrough || 662 MachineFunction::iterator(FBB) == Fallthrough) 663 return true; 664 665 // If it's an unconditional branch to some block not the fall through, it 666 // doesn't fall through. 667 if (Cond.empty()) return false; 668 669 // Otherwise, if it is conditional and has no explicit false block, it falls 670 // through. 671 return FBB == 0; 672} 673 674MachineBasicBlock * 675MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) { 676 // Splitting the critical edge to a landing pad block is non-trivial. Don't do 677 // it in this generic function. 678 if (Succ->isLandingPad()) 679 return NULL; 680 681 MachineFunction *MF = getParent(); 682 DebugLoc dl; // FIXME: this is nowhere 683 684 // Performance might be harmed on HW that implements branching using exec mask 685 // where both sides of the branches are always executed. 686 if (MF->getTarget().requiresStructuredCFG()) 687 return NULL; 688 689 // We may need to update this's terminator, but we can't do that if 690 // AnalyzeBranch fails. If this uses a jump table, we won't touch it. 691 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 692 MachineBasicBlock *TBB = 0, *FBB = 0; 693 SmallVector<MachineOperand, 4> Cond; 694 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) 695 return NULL; 696 697 // Avoid bugpoint weirdness: A block may end with a conditional branch but 698 // jumps to the same MBB is either case. We have duplicate CFG edges in that 699 // case that we can't handle. Since this never happens in properly optimized 700 // code, just skip those edges. 701 if (TBB && TBB == FBB) { 702 DEBUG(dbgs() << "Won't split critical edge after degenerate BB#" 703 << getNumber() << '\n'); 704 return NULL; 705 } 706 707 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock(); 708 MF->insert(std::next(MachineFunction::iterator(this)), NMBB); 709 DEBUG(dbgs() << "Splitting critical edge:" 710 " BB#" << getNumber() 711 << " -- BB#" << NMBB->getNumber() 712 << " -- BB#" << Succ->getNumber() << '\n'); 713 714 LiveIntervals *LIS = P->getAnalysisIfAvailable<LiveIntervals>(); 715 SlotIndexes *Indexes = P->getAnalysisIfAvailable<SlotIndexes>(); 716 if (LIS) 717 LIS->insertMBBInMaps(NMBB); 718 else if (Indexes) 719 Indexes->insertMBBInMaps(NMBB); 720 721 // On some targets like Mips, branches may kill virtual registers. Make sure 722 // that LiveVariables is properly updated after updateTerminator replaces the 723 // terminators. 724 LiveVariables *LV = P->getAnalysisIfAvailable<LiveVariables>(); 725 726 // Collect a list of virtual registers killed by the terminators. 727 SmallVector<unsigned, 4> KilledRegs; 728 if (LV) 729 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end(); 730 I != E; ++I) { 731 MachineInstr *MI = I; 732 for (MachineInstr::mop_iterator OI = MI->operands_begin(), 733 OE = MI->operands_end(); OI != OE; ++OI) { 734 if (!OI->isReg() || OI->getReg() == 0 || 735 !OI->isUse() || !OI->isKill() || OI->isUndef()) 736 continue; 737 unsigned Reg = OI->getReg(); 738 if (TargetRegisterInfo::isPhysicalRegister(Reg) || 739 LV->getVarInfo(Reg).removeKill(MI)) { 740 KilledRegs.push_back(Reg); 741 DEBUG(dbgs() << "Removing terminator kill: " << *MI); 742 OI->setIsKill(false); 743 } 744 } 745 } 746 747 SmallVector<unsigned, 4> UsedRegs; 748 if (LIS) { 749 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end(); 750 I != E; ++I) { 751 MachineInstr *MI = I; 752 753 for (MachineInstr::mop_iterator OI = MI->operands_begin(), 754 OE = MI->operands_end(); OI != OE; ++OI) { 755 if (!OI->isReg() || OI->getReg() == 0) 756 continue; 757 758 unsigned Reg = OI->getReg(); 759 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end()) 760 UsedRegs.push_back(Reg); 761 } 762 } 763 } 764 765 ReplaceUsesOfBlockWith(Succ, NMBB); 766 767 // If updateTerminator() removes instructions, we need to remove them from 768 // SlotIndexes. 769 SmallVector<MachineInstr*, 4> Terminators; 770 if (Indexes) { 771 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end(); 772 I != E; ++I) 773 Terminators.push_back(I); 774 } 775 776 updateTerminator(); 777 778 if (Indexes) { 779 SmallVector<MachineInstr*, 4> NewTerminators; 780 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end(); 781 I != E; ++I) 782 NewTerminators.push_back(I); 783 784 for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(), 785 E = Terminators.end(); I != E; ++I) { 786 if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) == 787 NewTerminators.end()) 788 Indexes->removeMachineInstrFromMaps(*I); 789 } 790 } 791 792 // Insert unconditional "jump Succ" instruction in NMBB if necessary. 793 NMBB->addSuccessor(Succ); 794 if (!NMBB->isLayoutSuccessor(Succ)) { 795 Cond.clear(); 796 MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, Succ, NULL, Cond, dl); 797 798 if (Indexes) { 799 for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end(); 800 I != E; ++I) { 801 // Some instructions may have been moved to NMBB by updateTerminator(), 802 // so we first remove any instruction that already has an index. 803 if (Indexes->hasIndex(I)) 804 Indexes->removeMachineInstrFromMaps(I); 805 Indexes->insertMachineInstrInMaps(I); 806 } 807 } 808 } 809 810 // Fix PHI nodes in Succ so they refer to NMBB instead of this 811 for (MachineBasicBlock::instr_iterator 812 i = Succ->instr_begin(),e = Succ->instr_end(); 813 i != e && i->isPHI(); ++i) 814 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2) 815 if (i->getOperand(ni+1).getMBB() == this) 816 i->getOperand(ni+1).setMBB(NMBB); 817 818 // Inherit live-ins from the successor 819 for (MachineBasicBlock::livein_iterator I = Succ->livein_begin(), 820 E = Succ->livein_end(); I != E; ++I) 821 NMBB->addLiveIn(*I); 822 823 // Update LiveVariables. 824 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 825 if (LV) { 826 // Restore kills of virtual registers that were killed by the terminators. 827 while (!KilledRegs.empty()) { 828 unsigned Reg = KilledRegs.pop_back_val(); 829 for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) { 830 if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false)) 831 continue; 832 if (TargetRegisterInfo::isVirtualRegister(Reg)) 833 LV->getVarInfo(Reg).Kills.push_back(I); 834 DEBUG(dbgs() << "Restored terminator kill: " << *I); 835 break; 836 } 837 } 838 // Update relevant live-through information. 839 LV->addNewBlock(NMBB, this, Succ); 840 } 841 842 if (LIS) { 843 // After splitting the edge and updating SlotIndexes, live intervals may be 844 // in one of two situations, depending on whether this block was the last in 845 // the function. If the original block was the last in the function, all live 846 // intervals will end prior to the beginning of the new split block. If the 847 // original block was not at the end of the function, all live intervals will 848 // extend to the end of the new split block. 849 850 bool isLastMBB = 851 std::next(MachineFunction::iterator(NMBB)) == getParent()->end(); 852 853 SlotIndex StartIndex = Indexes->getMBBEndIdx(this); 854 SlotIndex PrevIndex = StartIndex.getPrevSlot(); 855 SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB); 856 857 // Find the registers used from NMBB in PHIs in Succ. 858 SmallSet<unsigned, 8> PHISrcRegs; 859 for (MachineBasicBlock::instr_iterator 860 I = Succ->instr_begin(), E = Succ->instr_end(); 861 I != E && I->isPHI(); ++I) { 862 for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) { 863 if (I->getOperand(ni+1).getMBB() == NMBB) { 864 MachineOperand &MO = I->getOperand(ni); 865 unsigned Reg = MO.getReg(); 866 PHISrcRegs.insert(Reg); 867 if (MO.isUndef()) 868 continue; 869 870 LiveInterval &LI = LIS->getInterval(Reg); 871 VNInfo *VNI = LI.getVNInfoAt(PrevIndex); 872 assert(VNI && "PHI sources should be live out of their predecessors."); 873 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI)); 874 } 875 } 876 } 877 878 MachineRegisterInfo *MRI = &getParent()->getRegInfo(); 879 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 880 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 881 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg)) 882 continue; 883 884 LiveInterval &LI = LIS->getInterval(Reg); 885 if (!LI.liveAt(PrevIndex)) 886 continue; 887 888 bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ)); 889 if (isLiveOut && isLastMBB) { 890 VNInfo *VNI = LI.getVNInfoAt(PrevIndex); 891 assert(VNI && "LiveInterval should have VNInfo where it is live."); 892 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI)); 893 } else if (!isLiveOut && !isLastMBB) { 894 LI.removeSegment(StartIndex, EndIndex); 895 } 896 } 897 898 // Update all intervals for registers whose uses may have been modified by 899 // updateTerminator(). 900 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs); 901 } 902 903 if (MachineDominatorTree *MDT = 904 P->getAnalysisIfAvailable<MachineDominatorTree>()) { 905 // Update dominator information. 906 MachineDomTreeNode *SucccDTNode = MDT->getNode(Succ); 907 908 bool IsNewIDom = true; 909 for (const_pred_iterator PI = Succ->pred_begin(), E = Succ->pred_end(); 910 PI != E; ++PI) { 911 MachineBasicBlock *PredBB = *PI; 912 if (PredBB == NMBB) 913 continue; 914 if (!MDT->dominates(SucccDTNode, MDT->getNode(PredBB))) { 915 IsNewIDom = false; 916 break; 917 } 918 } 919 920 // We know "this" dominates the newly created basic block. 921 MachineDomTreeNode *NewDTNode = MDT->addNewBlock(NMBB, this); 922 923 // If all the other predecessors of "Succ" are dominated by "Succ" itself 924 // then the new block is the new immediate dominator of "Succ". Otherwise, 925 // the new block doesn't dominate anything. 926 if (IsNewIDom) 927 MDT->changeImmediateDominator(SucccDTNode, NewDTNode); 928 } 929 930 if (MachineLoopInfo *MLI = P->getAnalysisIfAvailable<MachineLoopInfo>()) 931 if (MachineLoop *TIL = MLI->getLoopFor(this)) { 932 // If one or the other blocks were not in a loop, the new block is not 933 // either, and thus LI doesn't need to be updated. 934 if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) { 935 if (TIL == DestLoop) { 936 // Both in the same loop, the NMBB joins loop. 937 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase()); 938 } else if (TIL->contains(DestLoop)) { 939 // Edge from an outer loop to an inner loop. Add to the outer loop. 940 TIL->addBasicBlockToLoop(NMBB, MLI->getBase()); 941 } else if (DestLoop->contains(TIL)) { 942 // Edge from an inner loop to an outer loop. Add to the outer loop. 943 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase()); 944 } else { 945 // Edge from two loops with no containment relation. Because these 946 // are natural loops, we know that the destination block must be the 947 // header of its loop (adding a branch into a loop elsewhere would 948 // create an irreducible loop). 949 assert(DestLoop->getHeader() == Succ && 950 "Should not create irreducible loops!"); 951 if (MachineLoop *P = DestLoop->getParentLoop()) 952 P->addBasicBlockToLoop(NMBB, MLI->getBase()); 953 } 954 } 955 } 956 957 return NMBB; 958} 959 960/// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's 961/// neighboring instructions so the bundle won't be broken by removing MI. 962static void unbundleSingleMI(MachineInstr *MI) { 963 // Removing the first instruction in a bundle. 964 if (MI->isBundledWithSucc() && !MI->isBundledWithPred()) 965 MI->unbundleFromSucc(); 966 // Removing the last instruction in a bundle. 967 if (MI->isBundledWithPred() && !MI->isBundledWithSucc()) 968 MI->unbundleFromPred(); 969 // If MI is not bundled, or if it is internal to a bundle, the neighbor flags 970 // are already fine. 971} 972 973MachineBasicBlock::instr_iterator 974MachineBasicBlock::erase(MachineBasicBlock::instr_iterator I) { 975 unbundleSingleMI(I); 976 return Insts.erase(I); 977} 978 979MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) { 980 unbundleSingleMI(MI); 981 MI->clearFlag(MachineInstr::BundledPred); 982 MI->clearFlag(MachineInstr::BundledSucc); 983 return Insts.remove(MI); 984} 985 986MachineBasicBlock::instr_iterator 987MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) { 988 assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() && 989 "Cannot insert instruction with bundle flags"); 990 // Set the bundle flags when inserting inside a bundle. 991 if (I != instr_end() && I->isBundledWithPred()) { 992 MI->setFlag(MachineInstr::BundledPred); 993 MI->setFlag(MachineInstr::BundledSucc); 994 } 995 return Insts.insert(I, MI); 996} 997 998/// removeFromParent - This method unlinks 'this' from the containing function, 999/// and returns it, but does not delete it. 1000MachineBasicBlock *MachineBasicBlock::removeFromParent() { 1001 assert(getParent() && "Not embedded in a function!"); 1002 getParent()->remove(this); 1003 return this; 1004} 1005 1006 1007/// eraseFromParent - This method unlinks 'this' from the containing function, 1008/// and deletes it. 1009void MachineBasicBlock::eraseFromParent() { 1010 assert(getParent() && "Not embedded in a function!"); 1011 getParent()->erase(this); 1012} 1013 1014 1015/// ReplaceUsesOfBlockWith - Given a machine basic block that branched to 1016/// 'Old', change the code and CFG so that it branches to 'New' instead. 1017void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old, 1018 MachineBasicBlock *New) { 1019 assert(Old != New && "Cannot replace self with self!"); 1020 1021 MachineBasicBlock::instr_iterator I = instr_end(); 1022 while (I != instr_begin()) { 1023 --I; 1024 if (!I->isTerminator()) break; 1025 1026 // Scan the operands of this machine instruction, replacing any uses of Old 1027 // with New. 1028 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) 1029 if (I->getOperand(i).isMBB() && 1030 I->getOperand(i).getMBB() == Old) 1031 I->getOperand(i).setMBB(New); 1032 } 1033 1034 // Update the successor information. 1035 replaceSuccessor(Old, New); 1036} 1037 1038/// CorrectExtraCFGEdges - Various pieces of code can cause excess edges in the 1039/// CFG to be inserted. If we have proven that MBB can only branch to DestA and 1040/// DestB, remove any other MBB successors from the CFG. DestA and DestB can be 1041/// null. 1042/// 1043/// Besides DestA and DestB, retain other edges leading to LandingPads 1044/// (currently there can be only one; we don't check or require that here). 1045/// Note it is possible that DestA and/or DestB are LandingPads. 1046bool MachineBasicBlock::CorrectExtraCFGEdges(MachineBasicBlock *DestA, 1047 MachineBasicBlock *DestB, 1048 bool isCond) { 1049 // The values of DestA and DestB frequently come from a call to the 1050 // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial 1051 // values from there. 1052 // 1053 // 1. If both DestA and DestB are null, then the block ends with no branches 1054 // (it falls through to its successor). 1055 // 2. If DestA is set, DestB is null, and isCond is false, then the block ends 1056 // with only an unconditional branch. 1057 // 3. If DestA is set, DestB is null, and isCond is true, then the block ends 1058 // with a conditional branch that falls through to a successor (DestB). 1059 // 4. If DestA and DestB is set and isCond is true, then the block ends with a 1060 // conditional branch followed by an unconditional branch. DestA is the 1061 // 'true' destination and DestB is the 'false' destination. 1062 1063 bool Changed = false; 1064 1065 MachineFunction::iterator FallThru = 1066 std::next(MachineFunction::iterator(this)); 1067 1068 if (DestA == 0 && DestB == 0) { 1069 // Block falls through to successor. 1070 DestA = FallThru; 1071 DestB = FallThru; 1072 } else if (DestA != 0 && DestB == 0) { 1073 if (isCond) 1074 // Block ends in conditional jump that falls through to successor. 1075 DestB = FallThru; 1076 } else { 1077 assert(DestA && DestB && isCond && 1078 "CFG in a bad state. Cannot correct CFG edges"); 1079 } 1080 1081 // Remove superfluous edges. I.e., those which aren't destinations of this 1082 // basic block, duplicate edges, or landing pads. 1083 SmallPtrSet<const MachineBasicBlock*, 8> SeenMBBs; 1084 MachineBasicBlock::succ_iterator SI = succ_begin(); 1085 while (SI != succ_end()) { 1086 const MachineBasicBlock *MBB = *SI; 1087 if (!SeenMBBs.insert(MBB) || 1088 (MBB != DestA && MBB != DestB && !MBB->isLandingPad())) { 1089 // This is a superfluous edge, remove it. 1090 SI = removeSuccessor(SI); 1091 Changed = true; 1092 } else { 1093 ++SI; 1094 } 1095 } 1096 1097 return Changed; 1098} 1099 1100/// findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping 1101/// any DBG_VALUE instructions. Return UnknownLoc if there is none. 1102DebugLoc 1103MachineBasicBlock::findDebugLoc(instr_iterator MBBI) { 1104 DebugLoc DL; 1105 instr_iterator E = instr_end(); 1106 if (MBBI == E) 1107 return DL; 1108 1109 // Skip debug declarations, we don't want a DebugLoc from them. 1110 while (MBBI != E && MBBI->isDebugValue()) 1111 MBBI++; 1112 if (MBBI != E) 1113 DL = MBBI->getDebugLoc(); 1114 return DL; 1115} 1116 1117/// getSuccWeight - Return weight of the edge from this block to MBB. 1118/// 1119uint32_t MachineBasicBlock::getSuccWeight(const_succ_iterator Succ) const { 1120 if (Weights.empty()) 1121 return 0; 1122 1123 return *getWeightIterator(Succ); 1124} 1125 1126/// Set successor weight of a given iterator. 1127void MachineBasicBlock::setSuccWeight(succ_iterator I, uint32_t weight) { 1128 if (Weights.empty()) 1129 return; 1130 *getWeightIterator(I) = weight; 1131} 1132 1133/// getWeightIterator - Return wight iterator corresonding to the I successor 1134/// iterator 1135MachineBasicBlock::weight_iterator MachineBasicBlock:: 1136getWeightIterator(MachineBasicBlock::succ_iterator I) { 1137 assert(Weights.size() == Successors.size() && "Async weight list!"); 1138 size_t index = std::distance(Successors.begin(), I); 1139 assert(index < Weights.size() && "Not a current successor!"); 1140 return Weights.begin() + index; 1141} 1142 1143/// getWeightIterator - Return wight iterator corresonding to the I successor 1144/// iterator 1145MachineBasicBlock::const_weight_iterator MachineBasicBlock:: 1146getWeightIterator(MachineBasicBlock::const_succ_iterator I) const { 1147 assert(Weights.size() == Successors.size() && "Async weight list!"); 1148 const size_t index = std::distance(Successors.begin(), I); 1149 assert(index < Weights.size() && "Not a current successor!"); 1150 return Weights.begin() + index; 1151} 1152 1153/// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed 1154/// as of just before "MI". 1155/// 1156/// Search is localised to a neighborhood of 1157/// Neighborhood instructions before (searching for defs or kills) and N 1158/// instructions after (searching just for defs) MI. 1159MachineBasicBlock::LivenessQueryResult 1160MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI, 1161 unsigned Reg, MachineInstr *MI, 1162 unsigned Neighborhood) { 1163 unsigned N = Neighborhood; 1164 MachineBasicBlock *MBB = MI->getParent(); 1165 1166 // Start by searching backwards from MI, looking for kills, reads or defs. 1167 1168 MachineBasicBlock::iterator I(MI); 1169 // If this is the first insn in the block, don't search backwards. 1170 if (I != MBB->begin()) { 1171 do { 1172 --I; 1173 1174 MachineOperandIteratorBase::PhysRegInfo Analysis = 1175 MIOperands(I).analyzePhysReg(Reg, TRI); 1176 1177 if (Analysis.Defines) 1178 // Outputs happen after inputs so they take precedence if both are 1179 // present. 1180 return Analysis.DefinesDead ? LQR_Dead : LQR_Live; 1181 1182 if (Analysis.Kills || Analysis.Clobbers) 1183 // Register killed, so isn't live. 1184 return LQR_Dead; 1185 1186 else if (Analysis.ReadsOverlap) 1187 // Defined or read without a previous kill - live. 1188 return Analysis.Reads ? LQR_Live : LQR_OverlappingLive; 1189 1190 } while (I != MBB->begin() && --N > 0); 1191 } 1192 1193 // Did we get to the start of the block? 1194 if (I == MBB->begin()) { 1195 // If so, the register's state is definitely defined by the live-in state. 1196 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true); 1197 RAI.isValid(); ++RAI) { 1198 if (MBB->isLiveIn(*RAI)) 1199 return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive; 1200 } 1201 1202 return LQR_Dead; 1203 } 1204 1205 N = Neighborhood; 1206 1207 // Try searching forwards from MI, looking for reads or defs. 1208 I = MachineBasicBlock::iterator(MI); 1209 // If this is the last insn in the block, don't search forwards. 1210 if (I != MBB->end()) { 1211 for (++I; I != MBB->end() && N > 0; ++I, --N) { 1212 MachineOperandIteratorBase::PhysRegInfo Analysis = 1213 MIOperands(I).analyzePhysReg(Reg, TRI); 1214 1215 if (Analysis.ReadsOverlap) 1216 // Used, therefore must have been live. 1217 return (Analysis.Reads) ? 1218 LQR_Live : LQR_OverlappingLive; 1219 1220 else if (Analysis.Clobbers || Analysis.Defines) 1221 // Defined (but not read) therefore cannot have been live. 1222 return LQR_Dead; 1223 } 1224 } 1225 1226 // At this point we have no idea of the liveness of the register. 1227 return LQR_Unknown; 1228} 1229