162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// Implementation of the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 15f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 1636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines#include "llvm/Support/raw_os_ostream.h" 1798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman#include "llvm/Target/TargetInstrInfo.h" 186d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen#include "llvm/Target/TargetMachine.h" 19a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen 2084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerusing namespace llvm; 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 22354362524a72b3fa43a6c09380b7ae3b2380cbbaJuergen Ributzka// Pin the vtable to this file. 23354362524a72b3fa43a6c09380b7ae3b2380cbbaJuergen Ributzkavoid MachineRegisterInfo::Delegate::anchor() {} 24354362524a72b3fa43a6c09380b7ae3b2380cbbaJuergen Ributzka 25d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill WendlingMachineRegisterInfo::MachineRegisterInfo(const TargetMachine &TM) 26dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : TM(TM), TheDelegate(nullptr), IsSSA(true), TracksLiveness(true) { 2784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner VRegInfo.reserve(256); 2890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints.reserve(256); 29d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling UsedRegUnits.resize(getTargetRegisterInfo()->getNumRegUnits()); 30d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs()); 31d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen 3262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Create the physreg use/def lists. 33d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling PhysRegUseDefLists = 34d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling new MachineOperand*[getTargetRegisterInfo()->getNumRegs()]; 35d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling memset(PhysRegUseDefLists, 0, 36d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling sizeof(MachineOperand*)*getTargetRegisterInfo()->getNumRegs()); 3762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 3862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 3962ed6b9ade63bf01717ce5274fa11e93e873d245Chris LattnerMachineRegisterInfo::~MachineRegisterInfo() { 4062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner delete [] PhysRegUseDefLists; 4162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 4262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 4333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// setRegClass - Set the register class of the specified virtual register. 4433f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// 4533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohmanvoid 4633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan GohmanMachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 47e8a3cc68782cc5d43d7b8e24c4afa94448905349Jakob Stoklund Olesen assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); 4833f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegInfo[Reg].first = RC; 4933f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman} 5033f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 51bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesenconst TargetRegisterClass * 52bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund OlesenMachineRegisterInfo::constrainRegClass(unsigned Reg, 5391fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen const TargetRegisterClass *RC, 5491fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen unsigned MinNumRegs) { 55bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *OldRC = getRegClass(Reg); 56bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen if (OldRC == RC) 57bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return RC; 58d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling const TargetRegisterClass *NewRC = 59d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling getTargetRegisterInfo()->getCommonSubClass(OldRC, RC); 6091fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen if (!NewRC || NewRC == OldRC) 6191fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen return NewRC; 6291fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen if (NewRC->getNumRegs() < MinNumRegs) 63dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 6491fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen setRegClass(Reg, NewRC); 65bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return NewRC; 66bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen} 67bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen 686d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesenbool 696d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund OlesenMachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { 706d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetInstrInfo *TII = TM.getInstrInfo(); 716d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetRegisterClass *OldRC = getRegClass(Reg); 72d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling const TargetRegisterClass *NewRC = 73d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC); 746d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 756d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen // Stop early if there is no room to grow. 766d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen if (NewRC == OldRC) 776d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return false; 786d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 796d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen // Accumulate constraints from all uses. 8036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (MachineOperand &MO : reg_nodbg_operands(Reg)) { 8136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // Apply the effect of the given operand to NewRC. 8236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineInstr *MI = MO.getParent(); 8336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned OpNo = &MO - &MI->getOperand(0); 8436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, 8536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines getTargetRegisterInfo()); 866d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen if (!NewRC || NewRC == OldRC) 876d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return false; 886d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen } 896d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen setRegClass(Reg, NewRC); 906d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return true; 916d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen} 926d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 932e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// createVirtualRegister - Create and return a new virtual register in the 942e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// function with the specified register class. 952e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// 962e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohmanunsigned 972e3e5bf42742a7421b513829101501f2de6d2b02Dan GohmanMachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 982e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman assert(RegClass && "Cannot create register without RegClass!"); 99f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen assert(RegClass->isAllocatable() && 100f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen "Virtual register RegClass must be allocatable."); 101994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen 102994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen // New virtual register number. 103994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 104994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VRegInfo.grow(Reg); 105994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VRegInfo[Reg].first = RegClass; 106994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen RegAllocHints.grow(Reg); 10703fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey if (TheDelegate) 10803fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey TheDelegate->MRI_NoteNewVirtualRegister(Reg); 109994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen return Reg; 1102e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman} 1112e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 11219273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick/// clearVirtRegs - Remove all virtual registers (after physreg assignment). 11319273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trickvoid MachineRegisterInfo::clearVirtRegs() { 11419273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick#ifndef NDEBUG 115a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { 116a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 117a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen if (!VRegInfo[Reg].second) 118a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen continue; 119a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen verifyUseList(Reg); 120a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen llvm_unreachable("Remaining virtual register operands"); 121a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen } 12219273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick#endif 12319273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick VRegInfo.clear(); 12419273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick} 12519273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick 126a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesenvoid MachineRegisterInfo::verifyUseList(unsigned Reg) const { 127a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen#ifndef NDEBUG 128a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen bool Valid = true; 12936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (MachineOperand &M : reg_operands(Reg)) { 13036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineOperand *MO = &M; 131a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen MachineInstr *MI = MO->getParent(); 132a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen if (!MI) { 133d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling errs() << PrintReg(Reg, getTargetRegisterInfo()) 134d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling << " use list MachineOperand " << MO 135a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen << " has no parent instruction.\n"; 136a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen Valid = false; 137a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen } 138a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen MachineOperand *MO0 = &MI->getOperand(0); 139a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen unsigned NumOps = MI->getNumOperands(); 140a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen if (!(MO >= MO0 && MO < MO0+NumOps)) { 141d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling errs() << PrintReg(Reg, getTargetRegisterInfo()) 142d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling << " use list MachineOperand " << MO 143a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen << " doesn't belong to parent MI: " << *MI; 144a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen Valid = false; 145a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen } 146a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen if (!MO->isReg()) { 147d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling errs() << PrintReg(Reg, getTargetRegisterInfo()) 148d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling << " MachineOperand " << MO << ": " << *MO 149a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen << " is not a register\n"; 150a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen Valid = false; 151a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen } 152a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen if (MO->getReg() != Reg) { 153d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling errs() << PrintReg(Reg, getTargetRegisterInfo()) 154d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling << " use-list MachineOperand " << MO << ": " 155a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen << *MO << " is the wrong register\n"; 156a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen Valid = false; 157a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen } 158a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen } 159a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen assert(Valid && "Invalid use list"); 160a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen#endif 161a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen} 162a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen 163a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesenvoid MachineRegisterInfo::verifyUseLists() const { 164a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen#ifndef NDEBUG 165a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 166a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen verifyUseList(TargetRegisterInfo::index2VirtReg(i)); 167d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i) 168a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen verifyUseList(i); 169a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen#endif 170a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen} 171a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen 172ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen/// Add MO to the linked list of operands for its register. 173ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesenvoid MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) { 174ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen assert(!MO->isOnRegUseList() && "Already on list"); 175c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 176c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *const Head = HeadRef; 177c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 178c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Head points to the first list element. 179c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Next is NULL on the last list element. 180c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Prev pointers are circular, so Head->Prev == Last. 181c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 182c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Head is NULL for an empty list. 183c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (!Head) { 184c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Prev = MO; 185dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MO->Contents.Reg.Next = nullptr; 186c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen HeadRef = MO; 187c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen return; 188c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen } 189c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(MO->getReg() == Head->getReg() && "Different regs on the same list!"); 190c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 191c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert MO between Last and Head in the circular Prev chain. 192c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *Last = Head->Contents.Reg.Prev; 193c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(Last && "Inconsistent use list"); 194c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(MO->getReg() == Last->getReg() && "Different regs on the same list!"); 195c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen Head->Contents.Reg.Prev = MO; 196c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Prev = Last; 197c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 198c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Def operands always precede uses. This allows def_iterator to stop early. 199c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert def operands at the front, and use operands at the back. 200c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (MO->isDef()) { 201c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert def at the front. 202c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Next = Head; 203c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen HeadRef = MO; 204c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen } else { 205c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert use at the end. 206dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MO->Contents.Reg.Next = nullptr; 207c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen Last->Contents.Reg.Next = MO; 20881a6995243380668e6f991fa4e11dd0a6e37e030Jakob Stoklund Olesen } 209ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen} 210ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 211ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen/// Remove MO from its use-def list. 212ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesenvoid MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) { 213ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen assert(MO->isOnRegUseList() && "Operand not on use list"); 214c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 215c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *const Head = HeadRef; 216c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(Head && "List already empty"); 217ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 218ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen // Unlink this from the doubly linked list of operands. 219c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *Next = MO->Contents.Reg.Next; 220c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *Prev = MO->Contents.Reg.Prev; 221c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 222c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Prev links are circular, next link is NULL instead of looping back to Head. 223c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (MO == Head) 224c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen HeadRef = Next; 225c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen else 226c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen Prev->Contents.Reg.Next = Next; 227c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 228c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen (Next ? Next : Head)->Contents.Reg.Prev = Prev; 229c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 230dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MO->Contents.Reg.Prev = nullptr; 231dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MO->Contents.Reg.Next = nullptr; 232ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen} 233ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 234bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// Move NumOps operands from Src to Dst, updating use-def lists as needed. 235bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// 236bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// The Dst range is assumed to be uninitialized memory. (Or it may contain 237bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// operands that won't be destroyed, which is OK because the MO destructor is 238bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// trivial anyway). 239bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// 240bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// The Src and Dst ranges may overlap. 241bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesenvoid MachineRegisterInfo::moveOperands(MachineOperand *Dst, 242bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *Src, 243bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen unsigned NumOps) { 244bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen assert(Src != Dst && NumOps && "Noop moveOperands"); 245bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 246bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Copy backwards if Dst is within the Src range. 247bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen int Stride = 1; 248bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen if (Dst >= Src && Dst < Src + NumOps) { 249bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Stride = -1; 250bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Dst += NumOps - 1; 251bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Src += NumOps - 1; 252bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen } 253bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 254bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Copy one operand at a time. 255bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen do { 256bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen new (Dst) MachineOperand(*Src); 257bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 258bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Dst takes Src's place in the use-def chain. 259bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen if (Src->isReg()) { 260bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *&Head = getRegUseDefListHead(Src->getReg()); 261bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *Prev = Src->Contents.Reg.Prev; 262bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *Next = Src->Contents.Reg.Next; 263bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen assert(Head && "List empty, but operand is chained"); 264bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen assert(Prev && "Operand was not on use-def list"); 265bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 266bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Prev links are circular, next link is NULL instead of looping back to 267bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Head. 268bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen if (Src == Head) 269bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Head = Dst; 270bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen else 271bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Prev->Contents.Reg.Next = Dst; 272bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 273bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Update Prev pointer. This also works when Src was pointing to itself 274bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // in a 1-element list. In that case Head == Dst. 275bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen (Next ? Next : Head)->Contents.Reg.Prev = Dst; 276bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen } 277bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 278bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Dst += Stride; 279bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Src += Stride; 280bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen } while (--NumOps); 281bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen} 282bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 283e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// replaceRegWith - Replace all instances of FromReg with ToReg in the 284e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 285e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// except that it also changes any definitions of the register as well. 286e138b3dd1ff02d826233482831318708a166ed93Chris Lattnervoid MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 287e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(FromReg != ToReg && "Cannot replace a reg with itself"); 288e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 289e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // TODO: This could be more efficient by bulk changing the operands. 290e138b3dd1ff02d826233482831318708a166ed93Chris Lattner for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 29136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineOperand &O = *I; 292e138b3dd1ff02d826233482831318708a166ed93Chris Lattner ++I; 293e138b3dd1ff02d826233482831318708a166ed93Chris Lattner O.setReg(ToReg); 294e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 295e138b3dd1ff02d826233482831318708a166ed93Chris Lattner} 296e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 297a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 298a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// getVRegDef - Return the machine instr that defines the specified virtual 299a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// register or null if none is found. This assumes that the code is in SSA 300a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// form, so there should only be one definition. 301a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris LattnerMachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 3022bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman // Since we are in SSA form, we can use the first definition. 30336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines def_instr_iterator I = def_instr_begin(Reg); 30436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines assert((I.atEnd() || std::next(I) == def_instr_end()) && 3055f917cd3fada4507c0f4b718dd6af24b5e7086f1Manman Ren "getVRegDef assumes a single definition or no definition"); 306dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return !I.atEnd() ? &*I : nullptr; 307a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner} 3081eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 30954d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren/// getUniqueVRegDef - Return the unique machine instr that defines the 31054d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren/// specified virtual register or null if none is found. If there are 31154d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren/// multiple definitions or no definition, return null. 31254d69668b22b8c37aa6e45f14445f3988cc430d4Manman RenMachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const { 313dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (def_empty(Reg)) return nullptr; 31436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines def_instr_iterator I = def_instr_begin(Reg); 31536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (std::next(I) != def_instr_end()) 316dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 31754d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren return &*I; 31854d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren} 31954d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren 3201423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Chengbool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 3211423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng use_nodbg_iterator UI = use_nodbg_begin(RegNo); 3221423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng if (UI == use_nodbg_end()) 3231423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return false; 3241423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return ++UI == use_nodbg_end(); 3251423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng} 3261eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 32749b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clearKillFlags - Iterate over all the uses of the given register and 32849b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clear the kill flag from the MachineOperand. This function is used by 32949b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// optimization passes which extend register lifetimes and need only 33049b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// preserve conservative kill flag information. 33149b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohmanvoid MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 33236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (MachineOperand &MO : use_operands(Reg)) 33336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MO.setIsKill(false); 33449b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman} 33549b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman 33613e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 33713e73f483ef2ba630962dad3125393292533b756Dan Gohman for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 33813e73f483ef2ba630962dad3125393292533b756Dan Gohman if (I->first == Reg || I->second == Reg) 33913e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 34013e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 34113e73f483ef2ba630962dad3125393292533b756Dan Gohman} 34213e73f483ef2ba630962dad3125393292533b756Dan Gohman 3432ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 3442ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// corresponding live-in physical register. 3452ad0fcf794924f618a7240741cc14a39be99d0f2Evan Chengunsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 3462ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 3472ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng if (I->second == VReg) 3482ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return I->first; 3492ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return 0; 3502ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng} 3512ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng 3523946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// getLiveInVirtReg - If PReg is a live-in physical register, return the 3533946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// corresponding live-in physical register. 3543946043a80a043b3cf43b34bf068feaadc46485bEvan Chengunsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 3553946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 3563946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng if (I->first == PReg) 3573946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return I->second; 3583946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return 0; 3593946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng} 3603946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng 36198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 36298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// into the given entry block. 36398708260f55cab997a5db77e930a2bd35f4172aaDan Gohmanvoid 36498708260f55cab997a5db77e930a2bd35f4172aaDan GohmanMachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 36598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 36698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII) { 367701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng // Emit the copies into the top of the block. 368fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 369fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman if (LiveIns[i].second) { 370fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman if (use_empty(LiveIns[i].second)) { 371fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // The livein has no uses. Drop it. 372fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // 373fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // It would be preferable to have isel avoid creating live-in 374fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // records for unused arguments in the first place, but it's 375fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // complicated by the debug info code for arguments. 376fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman LiveIns.erase(LiveIns.begin() + i); 377fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman --i; --e; 378fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } else { 379fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Emit a copy. 38068e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1Devang Patel BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 3811e1098c6f39590e1e74e5cb3c2a1652d8f3cb16aJakob Stoklund Olesen TII.get(TargetOpcode::COPY), LiveIns[i].second) 3821e1098c6f39590e1e74e5cb3c2a1652d8f3cb16aJakob Stoklund Olesen .addReg(LiveIns[i].first); 383fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman 384fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Add the register to the entry block live-in set. 385fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman EntryMBB->addLiveIn(LiveIns[i].first); 386fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } 387fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } else { 388fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Add the register to the entry block live-in set. 389fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman EntryMBB->addLiveIn(LiveIns[i].first); 390701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng } 39198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman} 39298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 3931eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 3941eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Chengvoid MachineRegisterInfo::dumpUses(unsigned Reg) const { 39536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (MachineInstr &I : use_instructions(Reg)) 39636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines I.dump(); 3971eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng} 3981eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 399d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 400d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesenvoid MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 401d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF); 402d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() && 403e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen "Invalid ReservedRegs vector from target"); 404d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen} 405c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 406c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesenbool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, 407c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen const MachineFunction &MF) const { 408c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 409c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 410e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen // Check if any overlapping register is modified, or allocatable so it may be 411e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen // used later. 412d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true); 413d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling AI.isValid(); ++AI) 414e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen if (!def_empty(*AI) || isAllocatable(*AI)) 415c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen return false; 416c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen return true; 417c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen} 41836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 41936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the 42036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines/// specified register as undefined which causes the DBG_VALUE to be 42136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines/// deleted during LiveDebugVariables analysis. 42236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hinesvoid MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const { 42336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.) 42436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineRegisterInfo::use_instr_iterator nextI; 42536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end(); 42636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines I != E; I = nextI) { 42736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines nextI = std::next(I); // I is invalidated by the setReg 42836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineInstr *UseMI = &*I; 42936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (UseMI->isDebugValue()) 43036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines UseMI->getOperand(0).setReg(0U); 43136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } 43236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines} 433