MachineRegisterInfo.cpp revision 03fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8
162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// Implementation of the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 15f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 1698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman#include "llvm/Target/TargetInstrInfo.h" 176d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen#include "llvm/Target/TargetMachine.h" 18a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen#include "llvm/Support/raw_os_ostream.h" 19a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen 2084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerusing namespace llvm; 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 22d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill WendlingMachineRegisterInfo::MachineRegisterInfo(const TargetMachine &TM) 2303fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey : TM(TM), TheDelegate(0), IsSSA(true), TracksLiveness(true) { 2484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner VRegInfo.reserve(256); 2590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints.reserve(256); 26d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling UsedRegUnits.resize(getTargetRegisterInfo()->getNumRegUnits()); 27d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs()); 28d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen 2962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Create the physreg use/def lists. 30d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling PhysRegUseDefLists = 31d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling new MachineOperand*[getTargetRegisterInfo()->getNumRegs()]; 32d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling memset(PhysRegUseDefLists, 0, 33d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling sizeof(MachineOperand*)*getTargetRegisterInfo()->getNumRegs()); 3462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 3562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 3662ed6b9ade63bf01717ce5274fa11e93e873d245Chris LattnerMachineRegisterInfo::~MachineRegisterInfo() { 3762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner delete [] PhysRegUseDefLists; 3862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 3962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 4033f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// setRegClass - Set the register class of the specified virtual register. 4133f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// 4233f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohmanvoid 4333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan GohmanMachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 44e8a3cc68782cc5d43d7b8e24c4afa94448905349Jakob Stoklund Olesen assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); 4533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegInfo[Reg].first = RC; 4633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman} 4733f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 48bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesenconst TargetRegisterClass * 49bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund OlesenMachineRegisterInfo::constrainRegClass(unsigned Reg, 5091fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen const TargetRegisterClass *RC, 5191fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen unsigned MinNumRegs) { 52bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *OldRC = getRegClass(Reg); 53bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen if (OldRC == RC) 54bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return RC; 55d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling const TargetRegisterClass *NewRC = 56d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling getTargetRegisterInfo()->getCommonSubClass(OldRC, RC); 5791fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen if (!NewRC || NewRC == OldRC) 5891fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen return NewRC; 5991fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen if (NewRC->getNumRegs() < MinNumRegs) 60bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return 0; 6191fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen setRegClass(Reg, NewRC); 62bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return NewRC; 63bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen} 64bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen 656d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesenbool 666d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund OlesenMachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { 676d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetInstrInfo *TII = TM.getInstrInfo(); 686d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetRegisterClass *OldRC = getRegClass(Reg); 69d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling const TargetRegisterClass *NewRC = 70d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC); 716d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 726d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen // Stop early if there is no room to grow. 736d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen if (NewRC == OldRC) 746d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return false; 756d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 766d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen // Accumulate constraints from all uses. 776d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; 786d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen ++I) { 796d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetRegisterClass *OpRC = 80d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling I->getRegClassConstraint(I.getOperandNo(), TII, 81d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling getTargetRegisterInfo()); 820488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen if (unsigned SubIdx = I.getOperand().getSubReg()) { 830488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen if (OpRC) 84d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling NewRC = getTargetRegisterInfo()->getMatchingSuperRegClass(NewRC, OpRC, 85d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling SubIdx); 860488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen else 87d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling NewRC = getTargetRegisterInfo()->getSubClassWithSubReg(NewRC, SubIdx); 880488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen } else if (OpRC) 89d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling NewRC = getTargetRegisterInfo()->getCommonSubClass(NewRC, OpRC); 906d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen if (!NewRC || NewRC == OldRC) 916d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return false; 926d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen } 936d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen setRegClass(Reg, NewRC); 946d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return true; 956d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen} 966d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 972e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// createVirtualRegister - Create and return a new virtual register in the 982e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// function with the specified register class. 992e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// 1002e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohmanunsigned 1012e3e5bf42742a7421b513829101501f2de6d2b02Dan GohmanMachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 1022e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman assert(RegClass && "Cannot create register without RegClass!"); 103f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen assert(RegClass->isAllocatable() && 104f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen "Virtual register RegClass must be allocatable."); 105994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen 106994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen // New virtual register number. 107994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 108994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VRegInfo.grow(Reg); 109994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VRegInfo[Reg].first = RegClass; 110994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen RegAllocHints.grow(Reg); 11103fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey if (TheDelegate) 11203fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey TheDelegate->MRI_NoteNewVirtualRegister(Reg); 113994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen return Reg; 1142e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman} 1152e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 11619273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick/// clearVirtRegs - Remove all virtual registers (after physreg assignment). 11719273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trickvoid MachineRegisterInfo::clearVirtRegs() { 11819273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick#ifndef NDEBUG 119a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { 120a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 121a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen if (!VRegInfo[Reg].second) 122a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen continue; 123a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen verifyUseList(Reg); 124a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen llvm_unreachable("Remaining virtual register operands"); 125a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen } 12619273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick#endif 12719273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick VRegInfo.clear(); 12819273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick} 12919273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick 130a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesenvoid MachineRegisterInfo::verifyUseList(unsigned Reg) const { 131a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen#ifndef NDEBUG 132a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen bool Valid = true; 133a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) { 134a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen MachineOperand *MO = &I.getOperand(); 135a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen MachineInstr *MI = MO->getParent(); 136a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen if (!MI) { 137d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling errs() << PrintReg(Reg, getTargetRegisterInfo()) 138d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling << " use list MachineOperand " << MO 139a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen << " has no parent instruction.\n"; 140a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen Valid = false; 141a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen } 142a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen MachineOperand *MO0 = &MI->getOperand(0); 143a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen unsigned NumOps = MI->getNumOperands(); 144a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen if (!(MO >= MO0 && MO < MO0+NumOps)) { 145d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling errs() << PrintReg(Reg, getTargetRegisterInfo()) 146d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling << " use list MachineOperand " << MO 147a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen << " doesn't belong to parent MI: " << *MI; 148a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen Valid = false; 149a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen } 150a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen if (!MO->isReg()) { 151d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling errs() << PrintReg(Reg, getTargetRegisterInfo()) 152d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling << " MachineOperand " << MO << ": " << *MO 153a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen << " is not a register\n"; 154a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen Valid = false; 155a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen } 156a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen if (MO->getReg() != Reg) { 157d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling errs() << PrintReg(Reg, getTargetRegisterInfo()) 158d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling << " use-list MachineOperand " << MO << ": " 159a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen << *MO << " is the wrong register\n"; 160a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen Valid = false; 161a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen } 162a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen } 163a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen assert(Valid && "Invalid use list"); 164a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen#endif 165a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen} 166a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen 167a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesenvoid MachineRegisterInfo::verifyUseLists() const { 168a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen#ifndef NDEBUG 169a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 170a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen verifyUseList(TargetRegisterInfo::index2VirtReg(i)); 171d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i) 172a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen verifyUseList(i); 173a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen#endif 174a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen} 175a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen 176ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen/// Add MO to the linked list of operands for its register. 177ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesenvoid MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) { 178ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen assert(!MO->isOnRegUseList() && "Already on list"); 179c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 180c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *const Head = HeadRef; 181c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 182c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Head points to the first list element. 183c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Next is NULL on the last list element. 184c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Prev pointers are circular, so Head->Prev == Last. 185c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 186c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Head is NULL for an empty list. 187c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (!Head) { 188c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Prev = MO; 189c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Next = 0; 190c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen HeadRef = MO; 191c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen return; 192c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen } 193c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(MO->getReg() == Head->getReg() && "Different regs on the same list!"); 194c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 195c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert MO between Last and Head in the circular Prev chain. 196c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *Last = Head->Contents.Reg.Prev; 197c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(Last && "Inconsistent use list"); 198c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(MO->getReg() == Last->getReg() && "Different regs on the same list!"); 199c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen Head->Contents.Reg.Prev = MO; 200c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Prev = Last; 201c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 202c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Def operands always precede uses. This allows def_iterator to stop early. 203c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert def operands at the front, and use operands at the back. 204c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (MO->isDef()) { 205c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert def at the front. 206c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Next = Head; 207c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen HeadRef = MO; 208c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen } else { 209c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert use at the end. 210c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Next = 0; 211c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen Last->Contents.Reg.Next = MO; 21281a6995243380668e6f991fa4e11dd0a6e37e030Jakob Stoklund Olesen } 213ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen} 214ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 215ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen/// Remove MO from its use-def list. 216ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesenvoid MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) { 217ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen assert(MO->isOnRegUseList() && "Operand not on use list"); 218c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 219c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *const Head = HeadRef; 220c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(Head && "List already empty"); 221ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 222ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen // Unlink this from the doubly linked list of operands. 223c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *Next = MO->Contents.Reg.Next; 224c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *Prev = MO->Contents.Reg.Prev; 225c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 226c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Prev links are circular, next link is NULL instead of looping back to Head. 227c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (MO == Head) 228c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen HeadRef = Next; 229c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen else 230c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen Prev->Contents.Reg.Next = Next; 231c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 232c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen (Next ? Next : Head)->Contents.Reg.Prev = Prev; 233c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 234ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen MO->Contents.Reg.Prev = 0; 235ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen MO->Contents.Reg.Next = 0; 236ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen} 237ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 238bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// Move NumOps operands from Src to Dst, updating use-def lists as needed. 239bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// 240bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// The Dst range is assumed to be uninitialized memory. (Or it may contain 241bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// operands that won't be destroyed, which is OK because the MO destructor is 242bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// trivial anyway). 243bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// 244bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// The Src and Dst ranges may overlap. 245bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesenvoid MachineRegisterInfo::moveOperands(MachineOperand *Dst, 246bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *Src, 247bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen unsigned NumOps) { 248bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen assert(Src != Dst && NumOps && "Noop moveOperands"); 249bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 250bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Copy backwards if Dst is within the Src range. 251bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen int Stride = 1; 252bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen if (Dst >= Src && Dst < Src + NumOps) { 253bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Stride = -1; 254bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Dst += NumOps - 1; 255bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Src += NumOps - 1; 256bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen } 257bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 258bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Copy one operand at a time. 259bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen do { 260bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen new (Dst) MachineOperand(*Src); 261bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 262bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Dst takes Src's place in the use-def chain. 263bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen if (Src->isReg()) { 264bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *&Head = getRegUseDefListHead(Src->getReg()); 265bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *Prev = Src->Contents.Reg.Prev; 266bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *Next = Src->Contents.Reg.Next; 267bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen assert(Head && "List empty, but operand is chained"); 268bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen assert(Prev && "Operand was not on use-def list"); 269bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 270bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Prev links are circular, next link is NULL instead of looping back to 271bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Head. 272bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen if (Src == Head) 273bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Head = Dst; 274bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen else 275bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Prev->Contents.Reg.Next = Dst; 276bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 277bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Update Prev pointer. This also works when Src was pointing to itself 278bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // in a 1-element list. In that case Head == Dst. 279bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen (Next ? Next : Head)->Contents.Reg.Prev = Dst; 280bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen } 281bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 282bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Dst += Stride; 283bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Src += Stride; 284bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen } while (--NumOps); 285bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen} 286bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 287e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// replaceRegWith - Replace all instances of FromReg with ToReg in the 288e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 289e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// except that it also changes any definitions of the register as well. 290e138b3dd1ff02d826233482831318708a166ed93Chris Lattnervoid MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 291e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(FromReg != ToReg && "Cannot replace a reg with itself"); 292e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 293e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // TODO: This could be more efficient by bulk changing the operands. 294e138b3dd1ff02d826233482831318708a166ed93Chris Lattner for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 295e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &O = I.getOperand(); 296e138b3dd1ff02d826233482831318708a166ed93Chris Lattner ++I; 297e138b3dd1ff02d826233482831318708a166ed93Chris Lattner O.setReg(ToReg); 298e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 299e138b3dd1ff02d826233482831318708a166ed93Chris Lattner} 300e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 301a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 302a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// getVRegDef - Return the machine instr that defines the specified virtual 303a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// register or null if none is found. This assumes that the code is in SSA 304a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// form, so there should only be one definition. 305a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris LattnerMachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 3062bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman // Since we are in SSA form, we can use the first definition. 3071e8db1a4faac5c9fdd486a6ddcdec1909f12e789Benjamin Kramer def_iterator I = def_begin(Reg); 3085f917cd3fada4507c0f4b718dd6af24b5e7086f1Manman Ren assert((I.atEnd() || llvm::next(I) == def_end()) && 3095f917cd3fada4507c0f4b718dd6af24b5e7086f1Manman Ren "getVRegDef assumes a single definition or no definition"); 3101e8db1a4faac5c9fdd486a6ddcdec1909f12e789Benjamin Kramer return !I.atEnd() ? &*I : 0; 311a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner} 3121eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 31354d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren/// getUniqueVRegDef - Return the unique machine instr that defines the 31454d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren/// specified virtual register or null if none is found. If there are 31554d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren/// multiple definitions or no definition, return null. 31654d69668b22b8c37aa6e45f14445f3988cc430d4Manman RenMachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const { 31754d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren if (def_empty(Reg)) return 0; 31854d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren def_iterator I = def_begin(Reg); 31954d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren if (llvm::next(I) != def_end()) 32054d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren return 0; 32154d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren return &*I; 32254d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren} 32354d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren 3241423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Chengbool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 3251423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng use_nodbg_iterator UI = use_nodbg_begin(RegNo); 3261423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng if (UI == use_nodbg_end()) 3271423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return false; 3281423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return ++UI == use_nodbg_end(); 3291423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng} 3301eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 33149b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clearKillFlags - Iterate over all the uses of the given register and 33249b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clear the kill flag from the MachineOperand. This function is used by 33349b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// optimization passes which extend register lifetimes and need only 33449b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// preserve conservative kill flag information. 33549b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohmanvoid MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 33649b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 33749b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman UI.getOperand().setIsKill(false); 33849b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman} 33949b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman 34013e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 34113e73f483ef2ba630962dad3125393292533b756Dan Gohman for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 34213e73f483ef2ba630962dad3125393292533b756Dan Gohman if (I->first == Reg || I->second == Reg) 34313e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 34413e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 34513e73f483ef2ba630962dad3125393292533b756Dan Gohman} 34613e73f483ef2ba630962dad3125393292533b756Dan Gohman 3472ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 3482ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// corresponding live-in physical register. 3492ad0fcf794924f618a7240741cc14a39be99d0f2Evan Chengunsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 3502ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 3512ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng if (I->second == VReg) 3522ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return I->first; 3532ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return 0; 3542ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng} 3552ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng 3563946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// getLiveInVirtReg - If PReg is a live-in physical register, return the 3573946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// corresponding live-in physical register. 3583946043a80a043b3cf43b34bf068feaadc46485bEvan Chengunsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 3593946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 3603946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng if (I->first == PReg) 3613946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return I->second; 3623946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return 0; 3633946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng} 3643946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng 36598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 36698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// into the given entry block. 36798708260f55cab997a5db77e930a2bd35f4172aaDan Gohmanvoid 36898708260f55cab997a5db77e930a2bd35f4172aaDan GohmanMachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 36998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 37098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII) { 371701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng // Emit the copies into the top of the block. 372fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 373fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman if (LiveIns[i].second) { 374fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman if (use_empty(LiveIns[i].second)) { 375fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // The livein has no uses. Drop it. 376fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // 377fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // It would be preferable to have isel avoid creating live-in 378fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // records for unused arguments in the first place, but it's 379fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // complicated by the debug info code for arguments. 380fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman LiveIns.erase(LiveIns.begin() + i); 381fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman --i; --e; 382fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } else { 383fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Emit a copy. 38468e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1Devang Patel BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 3851e1098c6f39590e1e74e5cb3c2a1652d8f3cb16aJakob Stoklund Olesen TII.get(TargetOpcode::COPY), LiveIns[i].second) 3861e1098c6f39590e1e74e5cb3c2a1652d8f3cb16aJakob Stoklund Olesen .addReg(LiveIns[i].first); 387fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman 388fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Add the register to the entry block live-in set. 389fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman EntryMBB->addLiveIn(LiveIns[i].first); 390fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } 391fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } else { 392fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Add the register to the entry block live-in set. 393fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman EntryMBB->addLiveIn(LiveIns[i].first); 394701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng } 39598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman} 39698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 3971eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 3981eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Chengvoid MachineRegisterInfo::dumpUses(unsigned Reg) const { 3991eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 4001eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng I.getOperand().getParent()->dump(); 4011eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng} 4021eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 403d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 404d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesenvoid MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 405d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF); 406d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() && 407e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen "Invalid ReservedRegs vector from target"); 408d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen} 409c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 410c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesenbool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, 411c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen const MachineFunction &MF) const { 412c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 413c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 414e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen // Check if any overlapping register is modified, or allocatable so it may be 415e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen // used later. 416d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true); 417d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling AI.isValid(); ++AI) 418e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen if (!def_empty(*AI) || isAllocatable(*AI)) 419c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen return false; 420c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen return true; 421c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen} 422