MachineRegisterInfo.cpp revision 19273aec441411b4d571fdb87c6daa0fbe7a33a0
162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// Implementation of the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 15f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 1698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman#include "llvm/Target/TargetInstrInfo.h" 176d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen#include "llvm/Target/TargetMachine.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerusing namespace llvm; 1984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2073e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund OlesenMachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) 21e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen : TRI(&TRI), IsSSA(true) { 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner VRegInfo.reserve(256); 2390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints.reserve(256); 246f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman UsedPhysRegs.resize(TRI.getNumRegs()); 25d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen UsedPhysRegMask.resize(TRI.getNumRegs()); 26d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen 2762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Create the physreg use/def lists. 286f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 296f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 3062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 3162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 3262ed6b9ade63bf01717ce5274fa11e93e873d245Chris LattnerMachineRegisterInfo::~MachineRegisterInfo() { 3362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#ifndef NDEBUG 3419273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick clearVirtRegs(); 3503bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 3603bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman assert(!PhysRegUseDefLists[i] && 3703bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman "PhysRegUseDefLists has entries after all instructions are deleted"); 3862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#endif 3962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner delete [] PhysRegUseDefLists; 4062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 4162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 4233f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// setRegClass - Set the register class of the specified virtual register. 4333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// 4433f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohmanvoid 4533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan GohmanMachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 4633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegInfo[Reg].first = RC; 4733f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman} 4833f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 49bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesenconst TargetRegisterClass * 50bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund OlesenMachineRegisterInfo::constrainRegClass(unsigned Reg, 5191fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen const TargetRegisterClass *RC, 5291fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen unsigned MinNumRegs) { 53bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *OldRC = getRegClass(Reg); 54bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen if (OldRC == RC) 55bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return RC; 56e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); 5791fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen if (!NewRC || NewRC == OldRC) 5891fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen return NewRC; 5991fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen if (NewRC->getNumRegs() < MinNumRegs) 60bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return 0; 6191fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen setRegClass(Reg, NewRC); 62bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return NewRC; 63bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen} 64bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen 656d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesenbool 666d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund OlesenMachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { 676d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetInstrInfo *TII = TM.getInstrInfo(); 686d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetRegisterClass *OldRC = getRegClass(Reg); 696d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); 706d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 716d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen // Stop early if there is no room to grow. 726d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen if (NewRC == OldRC) 736d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return false; 746d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 756d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen // Accumulate constraints from all uses. 766d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; 776d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen ++I) { 786d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetRegisterClass *OpRC = 79dee83c90bb7bda57f6d0db2d8f9138f411ecdbbcJakob Stoklund Olesen I->getRegClassConstraint(I.getOperandNo(), TII, TRI); 800488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen if (unsigned SubIdx = I.getOperand().getSubReg()) { 810488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen if (OpRC) 820488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx); 830488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen else 840488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx); 850488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen } else if (OpRC) 86e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen NewRC = TRI->getCommonSubClass(NewRC, OpRC); 876d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen if (!NewRC || NewRC == OldRC) 886d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return false; 896d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen } 906d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen setRegClass(Reg, NewRC); 916d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return true; 926d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen} 936d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 942e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// createVirtualRegister - Create and return a new virtual register in the 952e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// function with the specified register class. 962e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// 972e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohmanunsigned 982e3e5bf42742a7421b513829101501f2de6d2b02Dan GohmanMachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 992e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman assert(RegClass && "Cannot create register without RegClass!"); 100f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen assert(RegClass->isAllocatable() && 101f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen "Virtual register RegClass must be allocatable."); 102994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen 103994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen // New virtual register number. 104994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 105994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen 1062e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman // Add a reg, but keep track of whether the vector reallocated or not. 107994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0); 108994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg]; 109994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VRegInfo.grow(Reg); 110994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VRegInfo[Reg].first = RegClass; 111994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen RegAllocHints.grow(Reg); 1122e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 113994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase) 1142e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman // The vector reallocated, handle this now. 1152e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman HandleVRegListReallocation(); 116994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen return Reg; 1172e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman} 1182e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 11919273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick/// clearVirtRegs - Remove all virtual registers (after physreg assignment). 12019273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trickvoid MachineRegisterInfo::clearVirtRegs() { 12119273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick#ifndef NDEBUG 12219273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 12319273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 && 12419273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick "Vreg use list non-empty still?"); 12519273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick#endif 12619273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick VRegInfo.clear(); 12719273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick} 12819273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick 12962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// HandleVRegListReallocation - We just added a virtual register to the 13062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// VRegInfo info list and it reallocated. Update the use/def lists info 13162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// pointers. 13262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnervoid MachineRegisterInfo::HandleVRegListReallocation() { 13362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // The back pointers for the vreg lists point into the previous vector. 13462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Update them to point to their correct slots. 135994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { 136994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 137994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen MachineOperand *List = VRegInfo[Reg].second; 13862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner if (!List) continue; 13962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Update the back-pointer to be accurate once more. 140994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen List->Contents.Reg.Prev = &VRegInfo[Reg].second; 14162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 14284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} 143a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 144e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// replaceRegWith - Replace all instances of FromReg with ToReg in the 145e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 146e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// except that it also changes any definitions of the register as well. 147e138b3dd1ff02d826233482831318708a166ed93Chris Lattnervoid MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 148e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(FromReg != ToReg && "Cannot replace a reg with itself"); 149e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 150e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // TODO: This could be more efficient by bulk changing the operands. 151e138b3dd1ff02d826233482831318708a166ed93Chris Lattner for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 152e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &O = I.getOperand(); 153e138b3dd1ff02d826233482831318708a166ed93Chris Lattner ++I; 154e138b3dd1ff02d826233482831318708a166ed93Chris Lattner O.setReg(ToReg); 155e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 156e138b3dd1ff02d826233482831318708a166ed93Chris Lattner} 157e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 158a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 159a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// getVRegDef - Return the machine instr that defines the specified virtual 160a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// register or null if none is found. This assumes that the code is in SSA 161a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// form, so there should only be one definition. 162a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris LattnerMachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 1632bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman // Since we are in SSA form, we can use the first definition. 1642bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman if (!def_empty(Reg)) 1652bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman return &*def_begin(Reg); 166a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner return 0; 167a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner} 1681eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1691423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Chengbool MachineRegisterInfo::hasOneUse(unsigned RegNo) const { 1701423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng use_iterator UI = use_begin(RegNo); 1711423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng if (UI == use_end()) 1721423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return false; 1731423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return ++UI == use_end(); 1741423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng} 1751423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 1761423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Chengbool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 1771423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng use_nodbg_iterator UI = use_nodbg_begin(RegNo); 1781423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng if (UI == use_nodbg_end()) 1791423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return false; 1801423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return ++UI == use_nodbg_end(); 1811423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng} 1821eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 18349b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clearKillFlags - Iterate over all the uses of the given register and 18449b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clear the kill flag from the MachineOperand. This function is used by 18549b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// optimization passes which extend register lifetimes and need only 18649b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// preserve conservative kill flag information. 18749b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohmanvoid MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 18849b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 18949b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman UI.getOperand().setIsKill(false); 19049b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman} 19149b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman 19213e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 19313e73f483ef2ba630962dad3125393292533b756Dan Gohman for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 19413e73f483ef2ba630962dad3125393292533b756Dan Gohman if (I->first == Reg || I->second == Reg) 19513e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 19613e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 19713e73f483ef2ba630962dad3125393292533b756Dan Gohman} 19813e73f483ef2ba630962dad3125393292533b756Dan Gohman 19913e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 20013e73f483ef2ba630962dad3125393292533b756Dan Gohman for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 20113e73f483ef2ba630962dad3125393292533b756Dan Gohman if (*I == Reg) 20213e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 20313e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 20413e73f483ef2ba630962dad3125393292533b756Dan Gohman} 20513e73f483ef2ba630962dad3125393292533b756Dan Gohman 2062ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 2072ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// corresponding live-in physical register. 2082ad0fcf794924f618a7240741cc14a39be99d0f2Evan Chengunsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 2092ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 2102ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng if (I->second == VReg) 2112ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return I->first; 2122ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return 0; 2132ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng} 2142ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng 2153946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// getLiveInVirtReg - If PReg is a live-in physical register, return the 2163946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// corresponding live-in physical register. 2173946043a80a043b3cf43b34bf068feaadc46485bEvan Chengunsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 2183946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 2193946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng if (I->first == PReg) 2203946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return I->second; 2213946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return 0; 2223946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng} 2233946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng 22498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 22598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// into the given entry block. 22698708260f55cab997a5db77e930a2bd35f4172aaDan Gohmanvoid 22798708260f55cab997a5db77e930a2bd35f4172aaDan GohmanMachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 22898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 22998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII) { 230701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng // Emit the copies into the top of the block. 231fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 232fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman if (LiveIns[i].second) { 233fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman if (use_empty(LiveIns[i].second)) { 234fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // The livein has no uses. Drop it. 235fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // 236fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // It would be preferable to have isel avoid creating live-in 237fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // records for unused arguments in the first place, but it's 238fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // complicated by the debug info code for arguments. 239fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman LiveIns.erase(LiveIns.begin() + i); 240fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman --i; --e; 241fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } else { 242fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Emit a copy. 24368e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1Devang Patel BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 2441e1098c6f39590e1e74e5cb3c2a1652d8f3cb16aJakob Stoklund Olesen TII.get(TargetOpcode::COPY), LiveIns[i].second) 2451e1098c6f39590e1e74e5cb3c2a1652d8f3cb16aJakob Stoklund Olesen .addReg(LiveIns[i].first); 246fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman 247fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Add the register to the entry block live-in set. 248fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman EntryMBB->addLiveIn(LiveIns[i].first); 249fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } 250fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } else { 251fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Add the register to the entry block live-in set. 252fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman EntryMBB->addLiveIn(LiveIns[i].first); 253701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng } 25498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman} 25598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 2561eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 2571eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Chengvoid MachineRegisterInfo::dumpUses(unsigned Reg) const { 2581eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 2591eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng I.getOperand().getParent()->dump(); 2601eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng} 2611eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 262d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 263d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesenvoid MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 264d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen ReservedRegs = TRI->getReservedRegs(MF); 265d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen} 266c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 267c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesenbool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, 268c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen const MachineFunction &MF) const { 269c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 270c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 271c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen // Check if any overlapping register is modified. 272c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen for (const unsigned *R = TRI->getOverlaps(PhysReg); *R; ++R) 273c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen if (!def_empty(*R)) 274c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen return false; 275c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 276c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen // Check if any overlapping register is allocatable so it may be used later. 277c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen if (AllocatableRegs.empty()) 278c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen AllocatableRegs = TRI->getAllocatableSet(MF); 279c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen for (const unsigned *R = TRI->getOverlaps(PhysReg); *R; ++R) 280c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen if (AllocatableRegs.test(*R)) 281c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen return false; 282c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen return true; 283c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen} 284