MachineRegisterInfo.cpp revision 33f1c68cba4e905fdd2bf7d2848c52052d46fbff
162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// Implementation of the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 1584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerusing namespace llvm; 1684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan GohmanMachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner VRegInfo.reserve(256); 1911a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1. 206f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman UsedPhysRegs.resize(TRI.getNumRegs()); 2162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 2262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Create the physreg use/def lists. 236f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 246f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 2562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 2662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 2762ed6b9ade63bf01717ce5274fa11e93e873d245Chris LattnerMachineRegisterInfo::~MachineRegisterInfo() { 2862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#ifndef NDEBUG 2962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) 3062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?"); 3103bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 3203bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman assert(!PhysRegUseDefLists[i] && 3303bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman "PhysRegUseDefLists has entries after all instructions are deleted"); 3462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#endif 3562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner delete [] PhysRegUseDefLists; 3662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 3762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 3833f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// setRegClass - Set the register class of the specified virtual register. 3933f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// 4033f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohmanvoid 4133f1c68cba4e905fdd2bf7d2848c52052d46fbffDan GohmanMachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 4233f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman unsigned VR = Reg; 4333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman Reg -= TargetRegisterInfo::FirstVirtualRegister; 4433f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman assert(Reg < VRegInfo.size() && "Invalid vreg!"); 4533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman const TargetRegisterClass *OldRC = VRegInfo[Reg].first; 4633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegInfo[Reg].first = RC; 4733f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 4833f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // Remove from old register class's vregs list. This may be slow but 4933f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // fortunately this operation is rarely needed. 5033f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()]; 5133f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR); 5233f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegs.erase(I); 5333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 5433f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // Add to new register class's vregs list. 5533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman RegClass2VRegMap[RC->getID()].push_back(VR); 5633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman} 5733f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 582e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// createVirtualRegister - Create and return a new virtual register in the 592e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// function with the specified register class. 602e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// 612e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohmanunsigned 622e3e5bf42742a7421b513829101501f2de6d2b02Dan GohmanMachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 632e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman assert(RegClass && "Cannot create register without RegClass!"); 642e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman // Add a reg, but keep track of whether the vector reallocated or not. 652e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0]; 662e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0)); 672e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 682e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1))) 692e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman // The vector reallocated, handle this now. 702e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman HandleVRegListReallocation(); 712e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman unsigned VR = getLastVirtReg(); 722e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman RegClass2VRegMap[RegClass->getID()].push_back(VR); 732e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman return VR; 742e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman} 752e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 7662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// HandleVRegListReallocation - We just added a virtual register to the 7762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// VRegInfo info list and it reallocated. Update the use/def lists info 7862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// pointers. 7962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnervoid MachineRegisterInfo::HandleVRegListReallocation() { 8062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // The back pointers for the vreg lists point into the previous vector. 8162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Update them to point to their correct slots. 8262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) { 8362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *List = VRegInfo[i].second; 8462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner if (!List) continue; 8562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Update the back-pointer to be accurate once more. 8662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner List->Contents.Reg.Prev = &VRegInfo[i].second; 8762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 8884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} 89a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 90e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// replaceRegWith - Replace all instances of FromReg with ToReg in the 91e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 92e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// except that it also changes any definitions of the register as well. 93e138b3dd1ff02d826233482831318708a166ed93Chris Lattnervoid MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 94e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(FromReg != ToReg && "Cannot replace a reg with itself"); 95e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 96e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // TODO: This could be more efficient by bulk changing the operands. 97e138b3dd1ff02d826233482831318708a166ed93Chris Lattner for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 98e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &O = I.getOperand(); 99e138b3dd1ff02d826233482831318708a166ed93Chris Lattner ++I; 100e138b3dd1ff02d826233482831318708a166ed93Chris Lattner O.setReg(ToReg); 101e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 102e138b3dd1ff02d826233482831318708a166ed93Chris Lattner} 103e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 104a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 105a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// getVRegDef - Return the machine instr that defines the specified virtual 106a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// register or null if none is found. This assumes that the code is in SSA 107a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// form, so there should only be one definition. 108a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris LattnerMachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 1096f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() && 110a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner "Invalid vreg!"); 111a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) { 112a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner // Since we are in SSA form, we can stop at the first definition. 113e138b3dd1ff02d826233482831318708a166ed93Chris Lattner if (I.getOperand().isDef()) 114e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return &*I; 115a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner } 116a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner return 0; 117a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner} 1181eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1191eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1201eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 1211eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Chengvoid MachineRegisterInfo::dumpUses(unsigned Reg) const { 1221eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 1231eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng I.getOperand().getParent()->dump(); 1241eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng} 1251eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 126