MachineRegisterInfo.cpp revision 701d4d309f892d34428e3078f350d3d28d7d2a94
162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// Implementation of the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 15f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 1698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman#include "llvm/Target/TargetInstrInfo.h" 17f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng#include "llvm/Support/CommandLine.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerusing namespace llvm; 1984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 206f0d024a534af18d9e60b3ea757376cd8a3a980eDan GohmanMachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner VRegInfo.reserve(256); 2290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints.reserve(256); 2311a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1. 246f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman UsedPhysRegs.resize(TRI.getNumRegs()); 2562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 2662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Create the physreg use/def lists. 276f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 286f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 2962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 3062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 3162ed6b9ade63bf01717ce5274fa11e93e873d245Chris LattnerMachineRegisterInfo::~MachineRegisterInfo() { 3262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#ifndef NDEBUG 3362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) 3462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?"); 3503bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 3603bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman assert(!PhysRegUseDefLists[i] && 3703bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman "PhysRegUseDefLists has entries after all instructions are deleted"); 3862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#endif 3962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner delete [] PhysRegUseDefLists; 4062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 4162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 4233f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// setRegClass - Set the register class of the specified virtual register. 4333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// 4433f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohmanvoid 4533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan GohmanMachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 4633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman unsigned VR = Reg; 4733f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman Reg -= TargetRegisterInfo::FirstVirtualRegister; 4833f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman assert(Reg < VRegInfo.size() && "Invalid vreg!"); 4933f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman const TargetRegisterClass *OldRC = VRegInfo[Reg].first; 5033f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegInfo[Reg].first = RC; 5133f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 5233f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // Remove from old register class's vregs list. This may be slow but 5333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // fortunately this operation is rarely needed. 5433f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()]; 5533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR); 5633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegs.erase(I); 5733f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 5833f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // Add to new register class's vregs list. 5933f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman RegClass2VRegMap[RC->getID()].push_back(VR); 6033f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman} 6133f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 622e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// createVirtualRegister - Create and return a new virtual register in the 632e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// function with the specified register class. 642e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// 652e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohmanunsigned 662e3e5bf42742a7421b513829101501f2de6d2b02Dan GohmanMachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 672e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman assert(RegClass && "Cannot create register without RegClass!"); 682e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman // Add a reg, but keep track of whether the vector reallocated or not. 692e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0]; 702e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0)); 71358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng RegAllocHints.push_back(std::make_pair(0, 0)); 722e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 732e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1))) 742e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman // The vector reallocated, handle this now. 752e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman HandleVRegListReallocation(); 762e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman unsigned VR = getLastVirtReg(); 772e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman RegClass2VRegMap[RegClass->getID()].push_back(VR); 782e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman return VR; 792e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman} 802e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 8162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// HandleVRegListReallocation - We just added a virtual register to the 8262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// VRegInfo info list and it reallocated. Update the use/def lists info 8362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// pointers. 8462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnervoid MachineRegisterInfo::HandleVRegListReallocation() { 8562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // The back pointers for the vreg lists point into the previous vector. 8662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Update them to point to their correct slots. 8762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) { 8862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *List = VRegInfo[i].second; 8962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner if (!List) continue; 9062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Update the back-pointer to be accurate once more. 9162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner List->Contents.Reg.Prev = &VRegInfo[i].second; 9262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 9384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} 94a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 95e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// replaceRegWith - Replace all instances of FromReg with ToReg in the 96e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 97e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// except that it also changes any definitions of the register as well. 98e138b3dd1ff02d826233482831318708a166ed93Chris Lattnervoid MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 99e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(FromReg != ToReg && "Cannot replace a reg with itself"); 100e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 101e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // TODO: This could be more efficient by bulk changing the operands. 102e138b3dd1ff02d826233482831318708a166ed93Chris Lattner for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 103e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &O = I.getOperand(); 104e138b3dd1ff02d826233482831318708a166ed93Chris Lattner ++I; 105e138b3dd1ff02d826233482831318708a166ed93Chris Lattner O.setReg(ToReg); 106e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 107e138b3dd1ff02d826233482831318708a166ed93Chris Lattner} 108e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 109a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 110a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// getVRegDef - Return the machine instr that defines the specified virtual 111a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// register or null if none is found. This assumes that the code is in SSA 112a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// form, so there should only be one definition. 113a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris LattnerMachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 1146f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() && 115a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner "Invalid vreg!"); 1162bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman // Since we are in SSA form, we can use the first definition. 1172bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman if (!def_empty(Reg)) 1182bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman return &*def_begin(Reg); 119a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner return 0; 120a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner} 1211eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1221423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Chengbool MachineRegisterInfo::hasOneUse(unsigned RegNo) const { 1231423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng use_iterator UI = use_begin(RegNo); 1241423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng if (UI == use_end()) 1251423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return false; 1261423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return ++UI == use_end(); 1271423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng} 1281423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 1291423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Chengbool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 1301423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng use_nodbg_iterator UI = use_nodbg_begin(RegNo); 1311423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng if (UI == use_nodbg_end()) 1321423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return false; 1331423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return ++UI == use_nodbg_end(); 1341423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng} 1351eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 13649b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clearKillFlags - Iterate over all the uses of the given register and 13749b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clear the kill flag from the MachineOperand. This function is used by 13849b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// optimization passes which extend register lifetimes and need only 13949b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// preserve conservative kill flag information. 14049b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohmanvoid MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 14149b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 14249b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman UI.getOperand().setIsKill(false); 14349b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman} 14449b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman 14513e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 14613e73f483ef2ba630962dad3125393292533b756Dan Gohman for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 14713e73f483ef2ba630962dad3125393292533b756Dan Gohman if (I->first == Reg || I->second == Reg) 14813e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 14913e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 15013e73f483ef2ba630962dad3125393292533b756Dan Gohman} 15113e73f483ef2ba630962dad3125393292533b756Dan Gohman 15213e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 15313e73f483ef2ba630962dad3125393292533b756Dan Gohman for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 15413e73f483ef2ba630962dad3125393292533b756Dan Gohman if (*I == Reg) 15513e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 15613e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 15713e73f483ef2ba630962dad3125393292533b756Dan Gohman} 15813e73f483ef2ba630962dad3125393292533b756Dan Gohman 1592ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 1602ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// corresponding live-in physical register. 1612ad0fcf794924f618a7240741cc14a39be99d0f2Evan Chengunsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 1622ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 1632ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng if (I->second == VReg) 1642ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return I->first; 1652ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return 0; 1662ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng} 1672ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng 1683946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// getLiveInVirtReg - If PReg is a live-in physical register, return the 1693946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// corresponding live-in physical register. 1703946043a80a043b3cf43b34bf068feaadc46485bEvan Chengunsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 1713946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 1723946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng if (I->first == PReg) 1733946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return I->second; 1743946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return 0; 1753946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng} 1763946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng 17798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 17898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// physical register has only a single copy use, then coalesced the copy 17998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// if possible. 18098708260f55cab997a5db77e930a2bd35f4172aaDan Gohmanstatic void EmitLiveInCopy(MachineBasicBlock *MBB, 18198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman MachineBasicBlock::iterator &InsertPos, 18298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman unsigned VirtReg, unsigned PhysReg, 18398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterClass *RC, 18498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman DenseMap<MachineInstr*, unsigned> &CopyRegMap, 18598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const MachineRegisterInfo &MRI, 18698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 18798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII) { 18898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman unsigned NumUses = 0; 18998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman MachineInstr *UseMI = NULL; 19098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 19198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman UE = MRI.use_end(); UI != UE; ++UI) { 19298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman UseMI = &*UI; 19398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman if (++NumUses > 1) 19498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman break; 19598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman } 19698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 19798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // If the number of uses is not one, or the use is not a move instruction, 19898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // don't coalesce. Also, only coalesce away a virtual register to virtual 19998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // register copy. 20098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman bool Coalesced = false; 20198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 20298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman if (NumUses == 1 && 20398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 20498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman TargetRegisterInfo::isVirtualRegister(DstReg)) { 20598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman VirtReg = DstReg; 20698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman Coalesced = true; 20798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman } 20898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 20998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // Now find an ideal location to insert the copy. 21098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman MachineBasicBlock::iterator Pos = InsertPos; 21198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman while (Pos != MBB->begin()) { 21298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman MachineInstr *PrevMI = prior(Pos); 21398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 21498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // copyRegToReg might emit multiple instructions to do a copy. 21598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 21698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 21798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // This is what the BB looks like right now: 21898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // r1024 = mov r0 21998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // ... 22098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // r1 = mov r1024 22198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // 22298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // We want to insert "r1025 = mov r1". Inserting this copy below the 22398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // move to r1024 makes it impossible for that move to be coalesced. 22498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // 22598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // r1025 = mov r1 22698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // r1024 = mov r0 22798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // ... 22898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // r1 = mov 1024 22998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // r2 = mov 1025 23098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman break; // Woot! Found a good location. 23198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman --Pos; 23298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman } 23398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 23434dcc6fadca0a1117cdbd0e9b35c991a55b6e556Dan Gohman bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC, 23534dcc6fadca0a1117cdbd0e9b35c991a55b6e556Dan Gohman DebugLoc()); 23698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 23798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman (void) Emitted; 23898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 23998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 24098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman if (Coalesced) { 24198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman if (&*InsertPos == UseMI) ++InsertPos; 24298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman MBB->erase(UseMI); 24398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman } 24498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman} 24598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 24698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 24798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// into the given entry block. 24898708260f55cab997a5db77e930a2bd35f4172aaDan Gohmanvoid 24998708260f55cab997a5db77e930a2bd35f4172aaDan GohmanMachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 25098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 25198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII) { 252701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng // Emit the copies into the top of the block. 253701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng for (MachineRegisterInfo::livein_iterator LI = livein_begin(), 254701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng E = livein_end(); LI != E; ++LI) 255701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng if (LI->second) { 256701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng const TargetRegisterClass *RC = getRegClass(LI->second); 257701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 258701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng LI->second, LI->first, RC, RC, 259701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng DebugLoc()); 260701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 261701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng (void) Emitted; 262701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng } 263b13033f61c897224a0be2784faa721ff294c5254Dan Gohman 264b13033f61c897224a0be2784faa721ff294c5254Dan Gohman // Add function live-ins to entry block live-in set. 265b13033f61c897224a0be2784faa721ff294c5254Dan Gohman for (MachineRegisterInfo::livein_iterator I = livein_begin(), 266701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng E = livein_end(); I != E; ++I) 267b13033f61c897224a0be2784faa721ff294c5254Dan Gohman EntryMBB->addLiveIn(I->first); 26898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman} 26998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 27082b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesenvoid MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) { 27182b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen for (int i = UsedPhysRegs.find_first(); i >= 0; 27282b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen i = UsedPhysRegs.find_next(i)) 27382b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen for (const unsigned *SS = TRI.getSubRegisters(i); 27482b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen unsigned SubReg = *SS; ++SS) 2758e8b3cb9371e60b22d1f401ec63a774c6115e98dJakob Stoklund Olesen if (SubReg > unsigned(i)) 27682b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen UsedPhysRegs.set(SubReg); 27782b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen} 27882b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 2791eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 2801eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Chengvoid MachineRegisterInfo::dumpUses(unsigned Reg) const { 2811eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 2821eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng I.getOperand().getParent()->dump(); 2831eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng} 2841eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 285