MachineRegisterInfo.cpp revision 994c727b5790e5c976e32c75364d78eb9b22a568
162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// Implementation of the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 15f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 1698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman#include "llvm/Target/TargetInstrInfo.h" 17f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng#include "llvm/Support/CommandLine.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerusing namespace llvm; 1984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 206f0d024a534af18d9e60b3ea757376cd8a3a980eDan GohmanMachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner VRegInfo.reserve(256); 2290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints.reserve(256); 23a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman RegClass2VRegMap = new std::vector<unsigned>[TRI.getNumRegClasses()]; 246f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman UsedPhysRegs.resize(TRI.getNumRegs()); 2562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 2662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Create the physreg use/def lists. 276f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 286f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 2962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 3062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 3162ed6b9ade63bf01717ce5274fa11e93e873d245Chris LattnerMachineRegisterInfo::~MachineRegisterInfo() { 3262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#ifndef NDEBUG 33994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 34994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 && 35994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen "Vreg use list non-empty still?"); 3603bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 3703bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman assert(!PhysRegUseDefLists[i] && 3803bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman "PhysRegUseDefLists has entries after all instructions are deleted"); 3962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#endif 4062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner delete [] PhysRegUseDefLists; 4171f095b20a2b1710d35b81fced4ae8b2ca1a6f61Dan Gohman delete [] RegClass2VRegMap; 4262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 4362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 4433f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// setRegClass - Set the register class of the specified virtual register. 4533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// 4633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohmanvoid 4733f1c68cba4e905fdd2bf7d2848c52052d46fbffDan GohmanMachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 4833f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman const TargetRegisterClass *OldRC = VRegInfo[Reg].first; 4933f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegInfo[Reg].first = RC; 5033f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 5133f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // Remove from old register class's vregs list. This may be slow but 5233f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // fortunately this operation is rarely needed. 5333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()]; 54994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen std::vector<unsigned>::iterator I = 55994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen std::find(VRegs.begin(), VRegs.end(), Reg); 5633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegs.erase(I); 5733f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 5833f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // Add to new register class's vregs list. 59994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen RegClass2VRegMap[RC->getID()].push_back(Reg); 6033f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman} 6133f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 62bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesenconst TargetRegisterClass * 63bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund OlesenMachineRegisterInfo::constrainRegClass(unsigned Reg, 64bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *RC) { 65bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *OldRC = getRegClass(Reg); 66bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen if (OldRC == RC) 67bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return RC; 68bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *NewRC = getCommonSubClass(OldRC, RC); 69bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen if (!NewRC) 70bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return 0; 71bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen if (NewRC != OldRC) 72bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen setRegClass(Reg, NewRC); 73bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return NewRC; 74bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen} 75bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen 762e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// createVirtualRegister - Create and return a new virtual register in the 772e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// function with the specified register class. 782e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// 792e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohmanunsigned 802e3e5bf42742a7421b513829101501f2de6d2b02Dan GohmanMachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 812e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman assert(RegClass && "Cannot create register without RegClass!"); 82994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen 83994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen // New virtual register number. 84994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 85994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen 862e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman // Add a reg, but keep track of whether the vector reallocated or not. 87994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0); 88994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg]; 89994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VRegInfo.grow(Reg); 90994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VRegInfo[Reg].first = RegClass; 91994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen RegAllocHints.grow(Reg); 922e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 93994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase) 942e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman // The vector reallocated, handle this now. 952e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman HandleVRegListReallocation(); 96994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen RegClass2VRegMap[RegClass->getID()].push_back(Reg); 97994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen return Reg; 982e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman} 992e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 10062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// HandleVRegListReallocation - We just added a virtual register to the 10162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// VRegInfo info list and it reallocated. Update the use/def lists info 10262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// pointers. 10362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnervoid MachineRegisterInfo::HandleVRegListReallocation() { 10462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // The back pointers for the vreg lists point into the previous vector. 10562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Update them to point to their correct slots. 106994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { 107994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 108994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen MachineOperand *List = VRegInfo[Reg].second; 10962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner if (!List) continue; 11062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Update the back-pointer to be accurate once more. 111994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen List->Contents.Reg.Prev = &VRegInfo[Reg].second; 11262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 11384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} 114a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 115e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// replaceRegWith - Replace all instances of FromReg with ToReg in the 116e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 117e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// except that it also changes any definitions of the register as well. 118e138b3dd1ff02d826233482831318708a166ed93Chris Lattnervoid MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 119e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(FromReg != ToReg && "Cannot replace a reg with itself"); 120e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 121e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // TODO: This could be more efficient by bulk changing the operands. 122e138b3dd1ff02d826233482831318708a166ed93Chris Lattner for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 123e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &O = I.getOperand(); 124e138b3dd1ff02d826233482831318708a166ed93Chris Lattner ++I; 125e138b3dd1ff02d826233482831318708a166ed93Chris Lattner O.setReg(ToReg); 126e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 127e138b3dd1ff02d826233482831318708a166ed93Chris Lattner} 128e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 129a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 130a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// getVRegDef - Return the machine instr that defines the specified virtual 131a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// register or null if none is found. This assumes that the code is in SSA 132a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// form, so there should only be one definition. 133a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris LattnerMachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 1342bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman // Since we are in SSA form, we can use the first definition. 1352bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman if (!def_empty(Reg)) 1362bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman return &*def_begin(Reg); 137a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner return 0; 138a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner} 1391eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1401423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Chengbool MachineRegisterInfo::hasOneUse(unsigned RegNo) const { 1411423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng use_iterator UI = use_begin(RegNo); 1421423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng if (UI == use_end()) 1431423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return false; 1441423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return ++UI == use_end(); 1451423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng} 1461423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 1471423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Chengbool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 1481423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng use_nodbg_iterator UI = use_nodbg_begin(RegNo); 1491423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng if (UI == use_nodbg_end()) 1501423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return false; 1511423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return ++UI == use_nodbg_end(); 1521423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng} 1531eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 15449b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clearKillFlags - Iterate over all the uses of the given register and 15549b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clear the kill flag from the MachineOperand. This function is used by 15649b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// optimization passes which extend register lifetimes and need only 15749b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// preserve conservative kill flag information. 15849b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohmanvoid MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 15949b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 16049b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman UI.getOperand().setIsKill(false); 16149b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman} 16249b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman 16313e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 16413e73f483ef2ba630962dad3125393292533b756Dan Gohman for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 16513e73f483ef2ba630962dad3125393292533b756Dan Gohman if (I->first == Reg || I->second == Reg) 16613e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 16713e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 16813e73f483ef2ba630962dad3125393292533b756Dan Gohman} 16913e73f483ef2ba630962dad3125393292533b756Dan Gohman 17013e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 17113e73f483ef2ba630962dad3125393292533b756Dan Gohman for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 17213e73f483ef2ba630962dad3125393292533b756Dan Gohman if (*I == Reg) 17313e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 17413e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 17513e73f483ef2ba630962dad3125393292533b756Dan Gohman} 17613e73f483ef2ba630962dad3125393292533b756Dan Gohman 1772ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 1782ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// corresponding live-in physical register. 1792ad0fcf794924f618a7240741cc14a39be99d0f2Evan Chengunsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 1802ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 1812ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng if (I->second == VReg) 1822ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return I->first; 1832ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return 0; 1842ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng} 1852ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng 1863946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// getLiveInVirtReg - If PReg is a live-in physical register, return the 1873946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// corresponding live-in physical register. 1883946043a80a043b3cf43b34bf068feaadc46485bEvan Chengunsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 1893946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 1903946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng if (I->first == PReg) 1913946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return I->second; 1923946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return 0; 1933946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng} 1943946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng 19598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 19698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// into the given entry block. 19798708260f55cab997a5db77e930a2bd35f4172aaDan Gohmanvoid 19898708260f55cab997a5db77e930a2bd35f4172aaDan GohmanMachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 19998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 20098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII) { 201701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng // Emit the copies into the top of the block. 202fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 203fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman if (LiveIns[i].second) { 204fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman if (use_empty(LiveIns[i].second)) { 205fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // The livein has no uses. Drop it. 206fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // 207fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // It would be preferable to have isel avoid creating live-in 208fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // records for unused arguments in the first place, but it's 209fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // complicated by the debug info code for arguments. 210fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman LiveIns.erase(LiveIns.begin() + i); 211fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman --i; --e; 212fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } else { 213fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Emit a copy. 2141e1098c6f39590e1e74e5cb3c2a1652d8f3cb16aJakob Stoklund Olesen BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 2151e1098c6f39590e1e74e5cb3c2a1652d8f3cb16aJakob Stoklund Olesen TII.get(TargetOpcode::COPY), LiveIns[i].second) 2161e1098c6f39590e1e74e5cb3c2a1652d8f3cb16aJakob Stoklund Olesen .addReg(LiveIns[i].first); 217fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman 218fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Add the register to the entry block live-in set. 219fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman EntryMBB->addLiveIn(LiveIns[i].first); 220fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } 221fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } else { 222fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Add the register to the entry block live-in set. 223fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman EntryMBB->addLiveIn(LiveIns[i].first); 224701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng } 22598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman} 22698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 22782b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesenvoid MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) { 22882b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen for (int i = UsedPhysRegs.find_first(); i >= 0; 22982b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen i = UsedPhysRegs.find_next(i)) 23082b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen for (const unsigned *SS = TRI.getSubRegisters(i); 23182b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen unsigned SubReg = *SS; ++SS) 2328e8b3cb9371e60b22d1f401ec63a774c6115e98dJakob Stoklund Olesen if (SubReg > unsigned(i)) 23382b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen UsedPhysRegs.set(SubReg); 23482b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen} 23582b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 2361eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 2371eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Chengvoid MachineRegisterInfo::dumpUses(unsigned Reg) const { 2381eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 2391eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng I.getOperand().getParent()->dump(); 2401eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng} 2411eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 242