MachineRegisterInfo.cpp revision bced5cd924e47818d67e33b3ae1550ab96fc239a
162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// Implementation of the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 15f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 1698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman#include "llvm/Target/TargetInstrInfo.h" 176d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen#include "llvm/Target/TargetMachine.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerusing namespace llvm; 1984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2073e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund OlesenMachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) 21aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen : TRI(&TRI), IsSSA(true), TracksLiveness(true) { 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner VRegInfo.reserve(256); 2390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints.reserve(256); 244b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen UsedRegUnits.resize(TRI.getNumRegUnits()); 25d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen UsedPhysRegMask.resize(TRI.getNumRegs()); 26d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen 2762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Create the physreg use/def lists. 286f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 296f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 3062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 3162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 3262ed6b9ade63bf01717ce5274fa11e93e873d245Chris LattnerMachineRegisterInfo::~MachineRegisterInfo() { 3362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#ifndef NDEBUG 3419273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick clearVirtRegs(); 354b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) 3603bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman assert(!PhysRegUseDefLists[i] && 3703bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman "PhysRegUseDefLists has entries after all instructions are deleted"); 3862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#endif 3962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner delete [] PhysRegUseDefLists; 4062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 4162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 4233f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// setRegClass - Set the register class of the specified virtual register. 4333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// 4433f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohmanvoid 4533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan GohmanMachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 4633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegInfo[Reg].first = RC; 4733f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman} 4833f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 49bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesenconst TargetRegisterClass * 50bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund OlesenMachineRegisterInfo::constrainRegClass(unsigned Reg, 5191fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen const TargetRegisterClass *RC, 5291fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen unsigned MinNumRegs) { 53bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *OldRC = getRegClass(Reg); 54bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen if (OldRC == RC) 55bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return RC; 56e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); 5791fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen if (!NewRC || NewRC == OldRC) 5891fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen return NewRC; 5991fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen if (NewRC->getNumRegs() < MinNumRegs) 60bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return 0; 6191fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen setRegClass(Reg, NewRC); 62bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen return NewRC; 63bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen} 64bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen 656d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesenbool 666d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund OlesenMachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { 676d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetInstrInfo *TII = TM.getInstrInfo(); 686d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetRegisterClass *OldRC = getRegClass(Reg); 696d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); 706d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 716d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen // Stop early if there is no room to grow. 726d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen if (NewRC == OldRC) 736d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return false; 746d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 756d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen // Accumulate constraints from all uses. 766d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; 776d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen ++I) { 786d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen const TargetRegisterClass *OpRC = 79dee83c90bb7bda57f6d0db2d8f9138f411ecdbbcJakob Stoklund Olesen I->getRegClassConstraint(I.getOperandNo(), TII, TRI); 800488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen if (unsigned SubIdx = I.getOperand().getSubReg()) { 810488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen if (OpRC) 820488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx); 830488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen else 840488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx); 850488d6ee5deed63cc46efb5931d5761ab6f9c64cJakob Stoklund Olesen } else if (OpRC) 86e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen NewRC = TRI->getCommonSubClass(NewRC, OpRC); 876d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen if (!NewRC || NewRC == OldRC) 886d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return false; 896d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen } 906d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen setRegClass(Reg, NewRC); 916d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen return true; 926d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen} 936d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 942e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// createVirtualRegister - Create and return a new virtual register in the 952e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// function with the specified register class. 962e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// 972e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohmanunsigned 982e3e5bf42742a7421b513829101501f2de6d2b02Dan GohmanMachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 992e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman assert(RegClass && "Cannot create register without RegClass!"); 100f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen assert(RegClass->isAllocatable() && 101f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen "Virtual register RegClass must be allocatable."); 102994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen 103994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen // New virtual register number. 104994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 105994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VRegInfo.grow(Reg); 106994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VRegInfo[Reg].first = RegClass; 107994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen RegAllocHints.grow(Reg); 108994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen return Reg; 1092e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman} 1102e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 11119273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick/// clearVirtRegs - Remove all virtual registers (after physreg assignment). 11219273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trickvoid MachineRegisterInfo::clearVirtRegs() { 11319273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick#ifndef NDEBUG 11419273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 11519273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 && 11619273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick "Vreg use list non-empty still?"); 11719273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick#endif 11819273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick VRegInfo.clear(); 11919273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick} 12019273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick 121ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen/// Add MO to the linked list of operands for its register. 122ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesenvoid MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) { 123ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen assert(!MO->isOnRegUseList() && "Already on list"); 124c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 125c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *const Head = HeadRef; 126c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 127c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Head points to the first list element. 128c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Next is NULL on the last list element. 129c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Prev pointers are circular, so Head->Prev == Last. 130c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 131c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Head is NULL for an empty list. 132c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (!Head) { 133c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Prev = MO; 134c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Next = 0; 135c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen HeadRef = MO; 136c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen return; 137c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen } 138c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(MO->getReg() == Head->getReg() && "Different regs on the same list!"); 139c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 140c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert MO between Last and Head in the circular Prev chain. 141c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *Last = Head->Contents.Reg.Prev; 142c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(Last && "Inconsistent use list"); 143c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(MO->getReg() == Last->getReg() && "Different regs on the same list!"); 144c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen Head->Contents.Reg.Prev = MO; 145c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Prev = Last; 146c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 147c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Def operands always precede uses. This allows def_iterator to stop early. 148c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert def operands at the front, and use operands at the back. 149c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (MO->isDef()) { 150c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert def at the front. 151c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Next = Head; 152c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen HeadRef = MO; 153c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen } else { 154c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Insert use at the end. 155c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MO->Contents.Reg.Next = 0; 156c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen Last->Contents.Reg.Next = MO; 15781a6995243380668e6f991fa4e11dd0a6e37e030Jakob Stoklund Olesen } 158ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen} 159ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 160ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen/// Remove MO from its use-def list. 161ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesenvoid MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) { 162ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen assert(MO->isOnRegUseList() && "Operand not on use list"); 163c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 164c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *const Head = HeadRef; 165c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(Head && "List already empty"); 166ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 167ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen // Unlink this from the doubly linked list of operands. 168c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *Next = MO->Contents.Reg.Next; 169c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen MachineOperand *Prev = MO->Contents.Reg.Prev; 170c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 171c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // Prev links are circular, next link is NULL instead of looping back to Head. 172c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (MO == Head) 173c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen HeadRef = Next; 174c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen else 175c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen Prev->Contents.Reg.Next = Next; 176c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 177c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen (Next ? Next : Head)->Contents.Reg.Prev = Prev; 178c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen 179ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen MO->Contents.Reg.Prev = 0; 180ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen MO->Contents.Reg.Next = 0; 181ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen} 182ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 183bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// Move NumOps operands from Src to Dst, updating use-def lists as needed. 184bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// 185bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// The Dst range is assumed to be uninitialized memory. (Or it may contain 186bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// operands that won't be destroyed, which is OK because the MO destructor is 187bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// trivial anyway). 188bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// 189bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen/// The Src and Dst ranges may overlap. 190bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesenvoid MachineRegisterInfo::moveOperands(MachineOperand *Dst, 191bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *Src, 192bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen unsigned NumOps) { 193bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen assert(Src != Dst && NumOps && "Noop moveOperands"); 194bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 195bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Copy backwards if Dst is within the Src range. 196bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen int Stride = 1; 197bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen if (Dst >= Src && Dst < Src + NumOps) { 198bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Stride = -1; 199bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Dst += NumOps - 1; 200bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Src += NumOps - 1; 201bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen } 202bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 203bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Copy one operand at a time. 204bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen do { 205bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen new (Dst) MachineOperand(*Src); 206bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 207bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Dst takes Src's place in the use-def chain. 208bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen if (Src->isReg()) { 209bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *&Head = getRegUseDefListHead(Src->getReg()); 210bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *Prev = Src->Contents.Reg.Prev; 211bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen MachineOperand *Next = Src->Contents.Reg.Next; 212bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen assert(Head && "List empty, but operand is chained"); 213bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen assert(Prev && "Operand was not on use-def list"); 214bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 215bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Prev links are circular, next link is NULL instead of looping back to 216bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Head. 217bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen if (Src == Head) 218bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Head = Dst; 219bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen else 220bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Prev->Contents.Reg.Next = Dst; 221bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 222bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Update Prev pointer. This also works when Src was pointing to itself 223bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // in a 1-element list. In that case Head == Dst. 224bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen (Next ? Next : Head)->Contents.Reg.Prev = Dst; 225bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen } 226bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 227bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Dst += Stride; 228bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen Src += Stride; 229bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen } while (--NumOps); 230bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen} 231bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 232e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// replaceRegWith - Replace all instances of FromReg with ToReg in the 233e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 234e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// except that it also changes any definitions of the register as well. 235e138b3dd1ff02d826233482831318708a166ed93Chris Lattnervoid MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 236e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(FromReg != ToReg && "Cannot replace a reg with itself"); 237e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 238e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // TODO: This could be more efficient by bulk changing the operands. 239e138b3dd1ff02d826233482831318708a166ed93Chris Lattner for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 240e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &O = I.getOperand(); 241e138b3dd1ff02d826233482831318708a166ed93Chris Lattner ++I; 242e138b3dd1ff02d826233482831318708a166ed93Chris Lattner O.setReg(ToReg); 243e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 244e138b3dd1ff02d826233482831318708a166ed93Chris Lattner} 245e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 246a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 247a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// getVRegDef - Return the machine instr that defines the specified virtual 248a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// register or null if none is found. This assumes that the code is in SSA 249a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// form, so there should only be one definition. 250a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris LattnerMachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 2512bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman // Since we are in SSA form, we can use the first definition. 2521e8db1a4faac5c9fdd486a6ddcdec1909f12e789Benjamin Kramer def_iterator I = def_begin(Reg); 2535f917cd3fada4507c0f4b718dd6af24b5e7086f1Manman Ren assert((I.atEnd() || llvm::next(I) == def_end()) && 2545f917cd3fada4507c0f4b718dd6af24b5e7086f1Manman Ren "getVRegDef assumes a single definition or no definition"); 2551e8db1a4faac5c9fdd486a6ddcdec1909f12e789Benjamin Kramer return !I.atEnd() ? &*I : 0; 256a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner} 2571eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 25854d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren/// getUniqueVRegDef - Return the unique machine instr that defines the 25954d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren/// specified virtual register or null if none is found. If there are 26054d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren/// multiple definitions or no definition, return null. 26154d69668b22b8c37aa6e45f14445f3988cc430d4Manman RenMachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const { 26254d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren if (def_empty(Reg)) return 0; 26354d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren def_iterator I = def_begin(Reg); 26454d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren if (llvm::next(I) != def_end()) 26554d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren return 0; 26654d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren return &*I; 26754d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren} 26854d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren 2691423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Chengbool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 2701423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng use_nodbg_iterator UI = use_nodbg_begin(RegNo); 2711423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng if (UI == use_nodbg_end()) 2721423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return false; 2731423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return ++UI == use_nodbg_end(); 2741423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng} 2751eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 27649b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clearKillFlags - Iterate over all the uses of the given register and 27749b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// clear the kill flag from the MachineOperand. This function is used by 27849b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// optimization passes which extend register lifetimes and need only 27949b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman/// preserve conservative kill flag information. 28049b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohmanvoid MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 28149b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 28249b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman UI.getOperand().setIsKill(false); 28349b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman} 28449b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman 28513e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 28613e73f483ef2ba630962dad3125393292533b756Dan Gohman for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 28713e73f483ef2ba630962dad3125393292533b756Dan Gohman if (I->first == Reg || I->second == Reg) 28813e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 28913e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 29013e73f483ef2ba630962dad3125393292533b756Dan Gohman} 29113e73f483ef2ba630962dad3125393292533b756Dan Gohman 29213e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 29313e73f483ef2ba630962dad3125393292533b756Dan Gohman for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 29413e73f483ef2ba630962dad3125393292533b756Dan Gohman if (*I == Reg) 29513e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 29613e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 29713e73f483ef2ba630962dad3125393292533b756Dan Gohman} 29813e73f483ef2ba630962dad3125393292533b756Dan Gohman 2992ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 3002ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng/// corresponding live-in physical register. 3012ad0fcf794924f618a7240741cc14a39be99d0f2Evan Chengunsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 3022ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 3032ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng if (I->second == VReg) 3042ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return I->first; 3052ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng return 0; 3062ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng} 3072ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng 3083946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// getLiveInVirtReg - If PReg is a live-in physical register, return the 3093946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng/// corresponding live-in physical register. 3103946043a80a043b3cf43b34bf068feaadc46485bEvan Chengunsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 3113946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 3123946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng if (I->first == PReg) 3133946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return I->second; 3143946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng return 0; 3153946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng} 3163946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng 31798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 31898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// into the given entry block. 31998708260f55cab997a5db77e930a2bd35f4172aaDan Gohmanvoid 32098708260f55cab997a5db77e930a2bd35f4172aaDan GohmanMachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 32198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 32298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII) { 323701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng // Emit the copies into the top of the block. 324fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 325fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman if (LiveIns[i].second) { 326fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman if (use_empty(LiveIns[i].second)) { 327fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // The livein has no uses. Drop it. 328fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // 329fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // It would be preferable to have isel avoid creating live-in 330fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // records for unused arguments in the first place, but it's 331fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // complicated by the debug info code for arguments. 332fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman LiveIns.erase(LiveIns.begin() + i); 333fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman --i; --e; 334fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } else { 335fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Emit a copy. 33668e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1Devang Patel BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 3371e1098c6f39590e1e74e5cb3c2a1652d8f3cb16aJakob Stoklund Olesen TII.get(TargetOpcode::COPY), LiveIns[i].second) 3381e1098c6f39590e1e74e5cb3c2a1652d8f3cb16aJakob Stoklund Olesen .addReg(LiveIns[i].first); 339fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman 340fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Add the register to the entry block live-in set. 341fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman EntryMBB->addLiveIn(LiveIns[i].first); 342fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } 343fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman } else { 344fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman // Add the register to the entry block live-in set. 345fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cdDan Gohman EntryMBB->addLiveIn(LiveIns[i].first); 346701d4d309f892d34428e3078f350d3d28d7d2a94Evan Cheng } 34798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman} 34898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 3491eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 3501eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Chengvoid MachineRegisterInfo::dumpUses(unsigned Reg) const { 3511eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 3521eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng I.getOperand().getParent()->dump(); 3531eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng} 3541eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 355d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 356d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesenvoid MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 357d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen ReservedRegs = TRI->getReservedRegs(MF); 358e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen assert(ReservedRegs.size() == TRI->getNumRegs() && 359e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen "Invalid ReservedRegs vector from target"); 360d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen} 361c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 362c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesenbool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, 363c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen const MachineFunction &MF) const { 364c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 365c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 366e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen // Check if any overlapping register is modified, or allocatable so it may be 367e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen // used later. 368396618b43a85e12d290a90b181c6af5d7c0c5f11Jakob Stoklund Olesen for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) 369e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen if (!def_empty(*AI) || isAllocatable(*AI)) 370c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen return false; 371c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen return true; 372c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen} 373