MachineRegisterInfo.cpp revision f48023b3cf80f3a360cfef94b1e0d0084fd5d760
162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// Implementation of the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 15f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 1698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman#include "llvm/Target/TargetInstrInfo.h" 17f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng#include "llvm/Support/CommandLine.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerusing namespace llvm; 1984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 206f0d024a534af18d9e60b3ea757376cd8a3a980eDan GohmanMachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner VRegInfo.reserve(256); 2290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints.reserve(256); 2311a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1. 246f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman UsedPhysRegs.resize(TRI.getNumRegs()); 2562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 2662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Create the physreg use/def lists. 276f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 286f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 2962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 3062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 3162ed6b9ade63bf01717ce5274fa11e93e873d245Chris LattnerMachineRegisterInfo::~MachineRegisterInfo() { 3262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#ifndef NDEBUG 3362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) 3462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?"); 3503bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 3603bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman assert(!PhysRegUseDefLists[i] && 3703bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman "PhysRegUseDefLists has entries after all instructions are deleted"); 3862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#endif 3962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner delete [] PhysRegUseDefLists; 4062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner} 4162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 4233f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// setRegClass - Set the register class of the specified virtual register. 4333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman/// 4433f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohmanvoid 4533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan GohmanMachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 4633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman unsigned VR = Reg; 4733f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman Reg -= TargetRegisterInfo::FirstVirtualRegister; 4833f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman assert(Reg < VRegInfo.size() && "Invalid vreg!"); 4933f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman const TargetRegisterClass *OldRC = VRegInfo[Reg].first; 5033f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegInfo[Reg].first = RC; 5133f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 5233f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // Remove from old register class's vregs list. This may be slow but 5333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // fortunately this operation is rarely needed. 5433f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()]; 5533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR); 5633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman VRegs.erase(I); 5733f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 5833f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman // Add to new register class's vregs list. 5933f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman RegClass2VRegMap[RC->getID()].push_back(VR); 6033f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman} 6133f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman 622e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// createVirtualRegister - Create and return a new virtual register in the 632e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// function with the specified register class. 642e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman/// 652e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohmanunsigned 662e3e5bf42742a7421b513829101501f2de6d2b02Dan GohmanMachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 672e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman assert(RegClass && "Cannot create register without RegClass!"); 682e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman // Add a reg, but keep track of whether the vector reallocated or not. 692e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0]; 702e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0)); 71358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng RegAllocHints.push_back(std::make_pair(0, 0)); 722e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 732e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1))) 742e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman // The vector reallocated, handle this now. 752e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman HandleVRegListReallocation(); 762e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman unsigned VR = getLastVirtReg(); 772e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman RegClass2VRegMap[RegClass->getID()].push_back(VR); 782e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman return VR; 792e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman} 802e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman 8162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// HandleVRegListReallocation - We just added a virtual register to the 8262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// VRegInfo info list and it reallocated. Update the use/def lists info 8362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// pointers. 8462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnervoid MachineRegisterInfo::HandleVRegListReallocation() { 8562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // The back pointers for the vreg lists point into the previous vector. 8662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Update them to point to their correct slots. 8762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) { 8862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *List = VRegInfo[i].second; 8962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner if (!List) continue; 9062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Update the back-pointer to be accurate once more. 9162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner List->Contents.Reg.Prev = &VRegInfo[i].second; 9262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 9384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} 94a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 95e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// replaceRegWith - Replace all instances of FromReg with ToReg in the 96e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 97e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// except that it also changes any definitions of the register as well. 98e138b3dd1ff02d826233482831318708a166ed93Chris Lattnervoid MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 99e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(FromReg != ToReg && "Cannot replace a reg with itself"); 100e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 101e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // TODO: This could be more efficient by bulk changing the operands. 102e138b3dd1ff02d826233482831318708a166ed93Chris Lattner for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 103e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &O = I.getOperand(); 104e138b3dd1ff02d826233482831318708a166ed93Chris Lattner ++I; 105e138b3dd1ff02d826233482831318708a166ed93Chris Lattner O.setReg(ToReg); 106e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 107e138b3dd1ff02d826233482831318708a166ed93Chris Lattner} 108e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 109a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 110a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// getVRegDef - Return the machine instr that defines the specified virtual 111a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// register or null if none is found. This assumes that the code is in SSA 112a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// form, so there should only be one definition. 113a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris LattnerMachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 1146f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() && 115a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner "Invalid vreg!"); 1162bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman // Since we are in SSA form, we can use the first definition. 1172bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman if (!def_empty(Reg)) 1182bf0649e053d1589689d2e4cf32c7bf1e5e6ae12Dan Gohman return &*def_begin(Reg); 119a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner return 0; 120a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner} 1211eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1221423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Chengbool MachineRegisterInfo::hasOneUse(unsigned RegNo) const { 1231423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng use_iterator UI = use_begin(RegNo); 1241423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng if (UI == use_end()) 1251423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return false; 1261423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return ++UI == use_end(); 1271423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng} 1281423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 1291423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Chengbool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 1301423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng use_nodbg_iterator UI = use_nodbg_begin(RegNo); 1311423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng if (UI == use_nodbg_end()) 1321423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return false; 1331423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng return ++UI == use_nodbg_end(); 1341423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng} 1351eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 13613e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 13713e73f483ef2ba630962dad3125393292533b756Dan Gohman for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 13813e73f483ef2ba630962dad3125393292533b756Dan Gohman if (I->first == Reg || I->second == Reg) 13913e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 14013e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 14113e73f483ef2ba630962dad3125393292533b756Dan Gohman} 14213e73f483ef2ba630962dad3125393292533b756Dan Gohman 14313e73f483ef2ba630962dad3125393292533b756Dan Gohmanbool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 14413e73f483ef2ba630962dad3125393292533b756Dan Gohman for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 14513e73f483ef2ba630962dad3125393292533b756Dan Gohman if (*I == Reg) 14613e73f483ef2ba630962dad3125393292533b756Dan Gohman return true; 14713e73f483ef2ba630962dad3125393292533b756Dan Gohman return false; 14813e73f483ef2ba630962dad3125393292533b756Dan Gohman} 14913e73f483ef2ba630962dad3125393292533b756Dan Gohman 15098708260f55cab997a5db77e930a2bd35f4172aaDan Gohmanstatic cl::opt<bool> 15198708260f55cab997a5db77e930a2bd35f4172aaDan GohmanSchedLiveInCopies("schedule-livein-copies", cl::Hidden, 15298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman cl::desc("Schedule copies of livein registers"), 15398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman cl::init(false)); 15498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 15598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 15698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// physical register has only a single copy use, then coalesced the copy 15798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// if possible. 15898708260f55cab997a5db77e930a2bd35f4172aaDan Gohmanstatic void EmitLiveInCopy(MachineBasicBlock *MBB, 15998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman MachineBasicBlock::iterator &InsertPos, 16098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman unsigned VirtReg, unsigned PhysReg, 16198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterClass *RC, 16298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman DenseMap<MachineInstr*, unsigned> &CopyRegMap, 16398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const MachineRegisterInfo &MRI, 16498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 16598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII) { 16698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman unsigned NumUses = 0; 16798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman MachineInstr *UseMI = NULL; 16898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 16998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman UE = MRI.use_end(); UI != UE; ++UI) { 17098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman UseMI = &*UI; 17198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman if (++NumUses > 1) 17298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman break; 17398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman } 17498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 17598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // If the number of uses is not one, or the use is not a move instruction, 17698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // don't coalesce. Also, only coalesce away a virtual register to virtual 17798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // register copy. 17898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman bool Coalesced = false; 17998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 18098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman if (NumUses == 1 && 18198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 18298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman TargetRegisterInfo::isVirtualRegister(DstReg)) { 18398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman VirtReg = DstReg; 18498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman Coalesced = true; 18598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman } 18698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 18798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // Now find an ideal location to insert the copy. 18898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman MachineBasicBlock::iterator Pos = InsertPos; 18998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman while (Pos != MBB->begin()) { 19098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman MachineInstr *PrevMI = prior(Pos); 19198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 19298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // copyRegToReg might emit multiple instructions to do a copy. 19398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 19498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 19598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // This is what the BB looks like right now: 19698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // r1024 = mov r0 19798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // ... 19898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // r1 = mov r1024 19998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // 20098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // We want to insert "r1025 = mov r1". Inserting this copy below the 20198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // move to r1024 makes it impossible for that move to be coalesced. 20298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // 20398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // r1025 = mov r1 20498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // r1024 = mov r0 20598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // ... 20698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // r1 = mov 1024 20798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // r2 = mov 1025 20898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman break; // Woot! Found a good location. 20998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman --Pos; 21098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman } 21198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 21298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 21398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 21498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman (void) Emitted; 21598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 21698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 21798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman if (Coalesced) { 21898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman if (&*InsertPos == UseMI) ++InsertPos; 21998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman MBB->erase(UseMI); 22098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman } 22198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman} 22298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 223f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng/// InsertLiveInDbgValue - Insert a DBG_VALUE instruction for each live-in 224f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng/// register that has a corresponding source information metadata. e.g. 225f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng/// function parameters. 226f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Chengstatic void InsertLiveInDbgValue(MachineBasicBlock *MBB, 227f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng MachineBasicBlock::iterator InsertPos, 228f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng unsigned LiveInReg, unsigned VirtReg, 229f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng const MachineRegisterInfo &MRI, 230f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng const TargetInstrInfo &TII) { 231f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 232f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng UE = MRI.use_end(); UI != UE; ++UI) { 233f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng MachineInstr *UseMI = &*UI; 234f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng if (!UseMI->isDebugValue() || UseMI->getParent() != MBB) 235f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng continue; 236f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng // Found local dbg_value. FIXME: Verify it's not possible to have multiple 237f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng // dbg_value's which reference the vr in the same mbb. 238f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng uint64_t Offset = UseMI->getOperand(1).getImm(); 239f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng const MDNode *MDPtr = UseMI->getOperand(2).getMetadata(); 240f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng BuildMI(*MBB, InsertPos, InsertPos->getDebugLoc(), 241f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng TII.get(TargetOpcode::DBG_VALUE)) 242f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng .addReg(LiveInReg).addImm(Offset).addMetadata(MDPtr); 243f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng return; 244f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng } 245f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng} 246f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng 24798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 24898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman/// into the given entry block. 24998708260f55cab997a5db77e930a2bd35f4172aaDan Gohmanvoid 25098708260f55cab997a5db77e930a2bd35f4172aaDan GohmanMachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 25198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 25298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII) { 25398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman if (SchedLiveInCopies) { 25498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // Emit the copies at a heuristically-determined location in the block. 25598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman DenseMap<MachineInstr*, unsigned> CopyRegMap; 25698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 25798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman for (MachineRegisterInfo::livein_iterator LI = livein_begin(), 25898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman E = livein_end(); LI != E; ++LI) 25998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman if (LI->second) { 26098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterClass *RC = getRegClass(LI->second); 26198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 26298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman RC, CopyRegMap, *this, TRI, TII); 263f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng InsertLiveInDbgValue(EntryMBB, InsertPos, 264f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng LI->first, LI->second, *this, TII); 26598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman } 26698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman } else { 26798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman // Emit the copies into the top of the block. 26898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman for (MachineRegisterInfo::livein_iterator LI = livein_begin(), 26998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman E = livein_end(); LI != E; ++LI) 27098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman if (LI->second) { 27198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterClass *RC = getRegClass(LI->second); 27298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 27398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman LI->second, LI->first, RC, RC); 27498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 27598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman (void) Emitted; 276f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng InsertLiveInDbgValue(EntryMBB, EntryMBB->begin(), 277f48023b3cf80f3a360cfef94b1e0d0084fd5d760Evan Cheng LI->first, LI->second, *this, TII); 27898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman } 27998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman } 280b13033f61c897224a0be2784faa721ff294c5254Dan Gohman 281b13033f61c897224a0be2784faa721ff294c5254Dan Gohman // Add function live-ins to entry block live-in set. 282b13033f61c897224a0be2784faa721ff294c5254Dan Gohman for (MachineRegisterInfo::livein_iterator I = livein_begin(), 283b13033f61c897224a0be2784faa721ff294c5254Dan Gohman E = livein_end(); I != E; ++I) 284b13033f61c897224a0be2784faa721ff294c5254Dan Gohman EntryMBB->addLiveIn(I->first); 28598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman} 28698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 2871eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 2881eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Chengvoid MachineRegisterInfo::dumpUses(unsigned Reg) const { 2891eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 2901eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng I.getOperand().getParent()->dump(); 2911eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng} 2921eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 293