MachineRegisterInfo.cpp revision 19273aec441411b4d571fdb87c6daa0fbe7a33a0
15f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 25f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// 35f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// The LLVM Compiler Infrastructure 45f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// 50bc735ffcfb223c0186419547abaa5c84482663eChris Lattner// This file is distributed under the University of Illinois Open Source 60bc735ffcfb223c0186419547abaa5c84482663eChris Lattner// License. See LICENSE.TXT for details. 75f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// 85f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer//===----------------------------------------------------------------------===// 95f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// 105f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// Implementation of the MachineRegisterInfo class. 115f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer// 125f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer//===----------------------------------------------------------------------===// 135f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 145f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/CodeGen/MachineRegisterInfo.h" 155f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/CodeGen/MachineInstrBuilder.h" 165f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/Target/TargetInstrInfo.h" 175f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#include "llvm/Target/TargetMachine.h" 185f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencerusing namespace llvm; 195f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 20525a05093a4816af961fe2bc6b8a81c17e2e26c2Chris LattnerMachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) 213b8d116703db8018f855cbb4733ace426422623bNate Begeman : TRI(&TRI), IsSSA(true) { 22c5ae899b4bbf65488445316c63168079177db0edSteve Naroff VRegInfo.reserve(256); 235f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer RegAllocHints.reserve(256); 245f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer UsedPhysRegs.resize(TRI.getNumRegs()); 25590b6646ef747d2f7b42e5f40487ff07642d7b6fChris Lattner UsedPhysRegMask.resize(TRI.getNumRegs()); 26c44eec6dd29ee9415cbd38a35deff4c8b67abb6aAnders Carlsson 27c4a1dea2dc56bd1357ec91b829a0b9e68229a13eDaniel Dunbar // Create the physreg use/def lists. 28c4a1dea2dc56bd1357ec91b829a0b9e68229a13eDaniel Dunbar PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 29c4a1dea2dc56bd1357ec91b829a0b9e68229a13eDaniel Dunbar memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 308e9bebdea69c590dedfbf27374114cb76fe12fbdDouglas Gregor} 31c4a1dea2dc56bd1357ec91b829a0b9e68229a13eDaniel Dunbar 3256ee6896f2efebffb4a2cce5a7610cdf1eddbbbeSteve NaroffMachineRegisterInfo::~MachineRegisterInfo() { 33c44eec6dd29ee9415cbd38a35deff4c8b67abb6aAnders Carlsson#ifndef NDEBUG 345f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer clearVirtRegs(); 355f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 365f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer assert(!PhysRegUseDefLists[i] && 375f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer "PhysRegUseDefLists has entries after all instructions are deleted"); 385f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#endif 395f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer delete [] PhysRegUseDefLists; 405f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer} 41f7c2aa0b049272d8f318988c1965760dcb852578Douglas Gregor 42f7c2aa0b049272d8f318988c1965760dcb852578Douglas Gregor/// setRegClass - Set the register class of the specified virtual register. 43f7c2aa0b049272d8f318988c1965760dcb852578Douglas Gregor/// 44f7c2aa0b049272d8f318988c1965760dcb852578Douglas Gregorvoid 459d293dfc0ad7c44ae0b5eb9517f1ed8c8d8b7ff7Douglas GregorMachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 469d293dfc0ad7c44ae0b5eb9517f1ed8c8d8b7ff7Douglas Gregor VRegInfo[Reg].first = RC; 479d293dfc0ad7c44ae0b5eb9517f1ed8c8d8b7ff7Douglas Gregor} 489d293dfc0ad7c44ae0b5eb9517f1ed8c8d8b7ff7Douglas Gregor 499d293dfc0ad7c44ae0b5eb9517f1ed8c8d8b7ff7Douglas Gregorconst TargetRegisterClass * 509d293dfc0ad7c44ae0b5eb9517f1ed8c8d8b7ff7Douglas GregorMachineRegisterInfo::constrainRegClass(unsigned Reg, 519d293dfc0ad7c44ae0b5eb9517f1ed8c8d8b7ff7Douglas Gregor const TargetRegisterClass *RC, 52f7c2aa0b049272d8f318988c1965760dcb852578Douglas Gregor unsigned MinNumRegs) { 538320aaaa01d931aa234fc3bce05b399ef41898d5Daniel Dunbar const TargetRegisterClass *OldRC = getRegClass(Reg); 54f7c2aa0b049272d8f318988c1965760dcb852578Douglas Gregor if (OldRC == RC) 55f7c2aa0b049272d8f318988c1965760dcb852578Douglas Gregor return RC; 569d293dfc0ad7c44ae0b5eb9517f1ed8c8d8b7ff7Douglas Gregor const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); 5777ed8e4edf6ed78c53fb20ec3210aff2a59c9d87Ted Kremenek if (!NewRC || NewRC == OldRC) 585f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return NewRC; 595f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer if (NewRC->getNumRegs() < MinNumRegs) 605f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return 0; 615f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer setRegClass(Reg, NewRC); 625f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return NewRC; 635f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer} 645f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 655f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencerbool 665f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid SpencerMachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { 675f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer const TargetInstrInfo *TII = TM.getInstrInfo(); 685f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer const TargetRegisterClass *OldRC = getRegClass(Reg); 695f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); 705f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 715f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer // Stop early if there is no room to grow. 725f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer if (NewRC == OldRC) 735f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return false; 745f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 755f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer // Accumulate constraints from all uses. 765f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; 775f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer ++I) { 785f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer const TargetRegisterClass *OpRC = 795f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer I->getRegClassConstraint(I.getOperandNo(), TII, TRI); 8008ad47cbd1f81fcb31dbc731c13b885a07e12704Bill Wendling if (unsigned SubIdx = I.getOperand().getSubReg()) { 815f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer if (OpRC) 825f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx); 835f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer else 845f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx); 855f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer } else if (OpRC) 86fec0b49c3fa621fbf63e420f3d54a5bb3a0265d2Steve Naroff NewRC = TRI->getCommonSubClass(NewRC, OpRC); 875f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer if (!NewRC || NewRC == OldRC) 885f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return false; 8928be73f74c9e241a23ea24fe5756623de6bf1084Chris Lattner } 905f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer setRegClass(Reg, NewRC); 915f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return true; 925f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer} 935f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 945f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer/// createVirtualRegister - Create and return a new virtual register in the 955f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer/// function with the specified register class. 965f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer/// 975f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencerunsigned 985f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid SpencerMachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 995f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer assert(RegClass && "Cannot create register without RegClass!"); 100fec0b49c3fa621fbf63e420f3d54a5bb3a0265d2Steve Naroff assert(RegClass->isAllocatable() && 1015f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer "Virtual register RegClass must be allocatable."); 102ca354faa7e9b99af17070c82b9662a5fca76422cChris Lattner 1035f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer // New virtual register number. 1045f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 1054f6a7d7ead09b439216c32f2de806a998aeb222aSteve Naroff 1064f6a7d7ead09b439216c32f2de806a998aeb222aSteve Naroff // Add a reg, but keep track of whether the vector reallocated or not. 1075f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0); 10828be73f74c9e241a23ea24fe5756623de6bf1084Chris Lattner void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg]; 1095f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer VRegInfo.grow(Reg); 110590b6646ef747d2f7b42e5f40487ff07642d7b6fChris Lattner VRegInfo[Reg].first = RegClass; 11127c8dc06f65d7abcf6a7e7f64a7960c9a150ca01Douglas Gregor RegAllocHints.grow(Reg); 1125f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 113cd8f646eca128f52a7bce0103c51ff82ce96f374Daniel Dunbar if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase) 114cd8f646eca128f52a7bce0103c51ff82ce96f374Daniel Dunbar // The vector reallocated, handle this now. 115cd8f646eca128f52a7bce0103c51ff82ce96f374Daniel Dunbar HandleVRegListReallocation(); 116cd8f646eca128f52a7bce0103c51ff82ce96f374Daniel Dunbar return Reg; 1178070a8497c0fb3e6f70a557f788405d8945b1208Daniel Dunbar} 118cd8f646eca128f52a7bce0103c51ff82ce96f374Daniel Dunbar 119a5d1cb7ef3f0780540e7fd7180399fd220ef0210Daniel Dunbar/// clearVirtRegs - Remove all virtual registers (after physreg assignment). 120cd8f646eca128f52a7bce0103c51ff82ce96f374Daniel Dunbarvoid MachineRegisterInfo::clearVirtRegs() { 121cd8f646eca128f52a7bce0103c51ff82ce96f374Daniel Dunbar#ifndef NDEBUG 122cd8f646eca128f52a7bce0103c51ff82ce96f374Daniel Dunbar for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 123cd8f646eca128f52a7bce0103c51ff82ce96f374Daniel Dunbar assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 && 1245f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer "Vreg use list non-empty still?"); 1255f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#endif 1265f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer VRegInfo.clear(); 1275f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer} 128590b6646ef747d2f7b42e5f40487ff07642d7b6fChris Lattner 129590b6646ef747d2f7b42e5f40487ff07642d7b6fChris Lattner/// HandleVRegListReallocation - We just added a virtual register to the 1305f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer/// VRegInfo info list and it reallocated. Update the use/def lists info 131590b6646ef747d2f7b42e5f40487ff07642d7b6fChris Lattner/// pointers. 1328070a8497c0fb3e6f70a557f788405d8945b1208Daniel Dunbarvoid MachineRegisterInfo::HandleVRegListReallocation() { 133590b6646ef747d2f7b42e5f40487ff07642d7b6fChris Lattner // The back pointers for the vreg lists point into the previous vector. 1345f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer // Update them to point to their correct slots. 13538374b05791ee93300b9fbe8ceb3957f54184b37Steve Naroff for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { 13638374b05791ee93300b9fbe8ceb3957f54184b37Steve Naroff unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 1375f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer MachineOperand *List = VRegInfo[Reg].second; 1386ee7aa154e8bbb21a21254293410b944f78b0bfeChris Lattner if (!List) continue; 139019f4e858e78587f2241ff1a76c747d7bcd7578cChris Lattner // Update the back-pointer to be accurate once more. 140019f4e858e78587f2241ff1a76c747d7bcd7578cChris Lattner List->Contents.Reg.Prev = &VRegInfo[Reg].second; 141019f4e858e78587f2241ff1a76c747d7bcd7578cChris Lattner } 1426ee7aa154e8bbb21a21254293410b944f78b0bfeChris Lattner} 14345b6b9d080ac56917337d73d8f1cd6374b27b05dChris Lattner 1446ee7aa154e8bbb21a21254293410b944f78b0bfeChris Lattner/// replaceRegWith - Replace all instances of FromReg with ToReg in the 14545b6b9d080ac56917337d73d8f1cd6374b27b05dChris Lattner/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 14645b6b9d080ac56917337d73d8f1cd6374b27b05dChris Lattner/// except that it also changes any definitions of the register as well. 147c44eec6dd29ee9415cbd38a35deff4c8b67abb6aAnders Carlssonvoid MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 1482e5f54aa1dd15a62c34a9d1d24a5a0692f43934aTed Kremenek assert(FromReg != ToReg && "Cannot replace a reg with itself"); 1494cc627111453b75519d5130b57e06256da7b00e8Chris Lattner 1504cc627111453b75519d5130b57e06256da7b00e8Chris Lattner // TODO: This could be more efficient by bulk changing the operands. 1512e5f54aa1dd15a62c34a9d1d24a5a0692f43934aTed Kremenek for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 1524e99a5fc3b203397a91136c6e695e405fb8fc606Ted Kremenek MachineOperand &O = I.getOperand(); 1534e99a5fc3b203397a91136c6e695e405fb8fc606Ted Kremenek ++I; 1544e99a5fc3b203397a91136c6e695e405fb8fc606Ted Kremenek O.setReg(ToReg); 1554e99a5fc3b203397a91136c6e695e405fb8fc606Ted Kremenek } 1564e99a5fc3b203397a91136c6e695e405fb8fc606Ted Kremenek} 1574e99a5fc3b203397a91136c6e695e405fb8fc606Ted Kremenek 15856f349400c5932a196509c0480ff6f99a9a0b48fChris Lattner 15956f349400c5932a196509c0480ff6f99a9a0b48fChris Lattner/// getVRegDef - Return the machine instr that defines the specified virtual 16027c8dc06f65d7abcf6a7e7f64a7960c9a150ca01Douglas Gregor/// register or null if none is found. This assumes that the code is in SSA 16156f349400c5932a196509c0480ff6f99a9a0b48fChris Lattner/// form, so there should only be one definition. 1624e99a5fc3b203397a91136c6e695e405fb8fc606Ted KremenekMachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 1634e99a5fc3b203397a91136c6e695e405fb8fc606Ted Kremenek // Since we are in SSA form, we can use the first definition. 1644e99a5fc3b203397a91136c6e695e405fb8fc606Ted Kremenek if (!def_empty(Reg)) 1654e99a5fc3b203397a91136c6e695e405fb8fc606Ted Kremenek return &*def_begin(Reg); 16656f349400c5932a196509c0480ff6f99a9a0b48fChris Lattner return 0; 16756f349400c5932a196509c0480ff6f99a9a0b48fChris Lattner} 16856f349400c5932a196509c0480ff6f99a9a0b48fChris Lattner 16956f349400c5932a196509c0480ff6f99a9a0b48fChris Lattnerbool MachineRegisterInfo::hasOneUse(unsigned RegNo) const { 1705f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer use_iterator UI = use_begin(RegNo); 1715f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer if (UI == use_end()) 1725f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return false; 1735f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return ++UI == use_end(); 1745f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer} 1752e7d352dbec06755105237afba183492d31d03cbTed Kremenek 176e2563ca02a519c2ad6d64dfed87d6e86c5d3c072Sam Bishopbool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 177e2563ca02a519c2ad6d64dfed87d6e86c5d3c072Sam Bishop use_nodbg_iterator UI = use_nodbg_begin(RegNo); 1782e7d352dbec06755105237afba183492d31d03cbTed Kremenek if (UI == use_nodbg_end()) 1795f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return false; 1805f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return ++UI == use_nodbg_end(); 1815549976193e34417d4474a5f4a514268ef6666c7Ted Kremenek} 1825549976193e34417d4474a5f4a514268ef6666c7Ted Kremenek 1835f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer/// clearKillFlags - Iterate over all the uses of the given register and 1845f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer/// clear the kill flag from the MachineOperand. This function is used by 1855f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer/// optimization passes which extend register lifetimes and need only 1865f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer/// preserve conservative kill flag information. 1875f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencervoid MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 1885f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 1898e9bebdea69c590dedfbf27374114cb76fe12fbdDouglas Gregor UI.getOperand().setIsKill(false); 1905f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer} 1919e922b1663ecb95dc7eee03002fd66ed18fb3192Argyrios Kyrtzidis 1929e922b1663ecb95dc7eee03002fd66ed18fb3192Argyrios Kyrtzidisbool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 1938e9bebdea69c590dedfbf27374114cb76fe12fbdDouglas Gregor for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 1949e922b1663ecb95dc7eee03002fd66ed18fb3192Argyrios Kyrtzidis if (I->first == Reg || I->second == Reg) 1959e922b1663ecb95dc7eee03002fd66ed18fb3192Argyrios Kyrtzidis return true; 1965f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return false; 1978e9bebdea69c590dedfbf27374114cb76fe12fbdDouglas Gregor} 1985f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 1995f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencerbool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 2008e9bebdea69c590dedfbf27374114cb76fe12fbdDouglas Gregor for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 2018e9bebdea69c590dedfbf27374114cb76fe12fbdDouglas Gregor if (*I == Reg) 202904eed3f6148758d39a2d3c88f3133274460d645Douglas Gregor return true; 203904eed3f6148758d39a2d3c88f3133274460d645Douglas Gregor return false; 2049e922b1663ecb95dc7eee03002fd66ed18fb3192Argyrios Kyrtzidis} 2055f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 2065f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 2075f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer/// corresponding live-in physical register. 2089e922b1663ecb95dc7eee03002fd66ed18fb3192Argyrios Kyrtzidisunsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 2099e922b1663ecb95dc7eee03002fd66ed18fb3192Argyrios Kyrtzidis for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 2105f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer if (I->second == VReg) 2115f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return I->first; 21277ed8e4edf6ed78c53fb20ec3210aff2a59c9d87Ted Kremenek return 0; 21377ed8e4edf6ed78c53fb20ec3210aff2a59c9d87Ted Kremenek} 21477ed8e4edf6ed78c53fb20ec3210aff2a59c9d87Ted Kremenek 21577ed8e4edf6ed78c53fb20ec3210aff2a59c9d87Ted Kremenek/// getLiveInVirtReg - If PReg is a live-in physical register, return the 2162dc9ac73a8a34cabf261a81a1653d7379065ac61Ted Kremenek/// corresponding live-in physical register. 217ec0aa78745f7b3bc96c20fffd1115bf26aaa0eadTed Kremenekunsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 218e2563ca02a519c2ad6d64dfed87d6e86c5d3c072Sam Bishop for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 2195f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer if (I->first == PReg) 2205f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return I->second; 221d9f6910f4ef37c0e8eeee2a01287d9572c3176efChris Lattner return 0; 222d9f6910f4ef37c0e8eeee2a01287d9572c3176efChris Lattner} 223227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson 224227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 225227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson/// into the given entry block. 226227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlssonvoid 227cd9b46e5442a3ef17f83f75177d8545cb5b3e2b9Douglas GregorMachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 228227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson const TargetRegisterInfo &TRI, 229227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson const TargetInstrInfo &TII) { 230227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson // Emit the copies into the top of the block. 231227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 232227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson if (LiveIns[i].second) { 233227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson if (use_empty(LiveIns[i].second)) { 234d9f6910f4ef37c0e8eeee2a01287d9572c3176efChris Lattner // The livein has no uses. Drop it. 235d9f6910f4ef37c0e8eeee2a01287d9572c3176efChris Lattner // 236227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson // It would be preferable to have isel avoid creating live-in 237227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson // records for unused arguments in the first place, but it's 238227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson // complicated by the debug info code for arguments. 239227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson LiveIns.erase(LiveIns.begin() + i); 240227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson --i; --e; 241227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson } else { 242d9f6910f4ef37c0e8eeee2a01287d9572c3176efChris Lattner // Emit a copy. 243227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 244d9f6910f4ef37c0e8eeee2a01287d9572c3176efChris Lattner TII.get(TargetOpcode::COPY), LiveIns[i].second) 24577ed8e4edf6ed78c53fb20ec3210aff2a59c9d87Ted Kremenek .addReg(LiveIns[i].first); 24677ed8e4edf6ed78c53fb20ec3210aff2a59c9d87Ted Kremenek 24777ed8e4edf6ed78c53fb20ec3210aff2a59c9d87Ted Kremenek // Add the register to the entry block live-in set. 24877ed8e4edf6ed78c53fb20ec3210aff2a59c9d87Ted Kremenek EntryMBB->addLiveIn(LiveIns[i].first); 2491ba485e582edfc8636afc25a6d7453c869530688Ted Kremenek } 250ec0aa78745f7b3bc96c20fffd1115bf26aaa0eadTed Kremenek } else { 251d9f6910f4ef37c0e8eeee2a01287d9572c3176efChris Lattner // Add the register to the entry block live-in set. 252227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson EntryMBB->addLiveIn(LiveIns[i].first); 253227426661be33ff3e21f2b6b9f97971da2da044fAnders Carlsson } 2545f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer} 2555f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 2565f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#ifndef NDEBUG 2575f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencervoid MachineRegisterInfo::dumpUses(unsigned Reg) const { 2585f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 2595f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer I.getOperand().getParent()->dump(); 2605f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer} 2615f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer#endif 2625f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 2635f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencervoid MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 2645f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer ReservedRegs = TRI->getReservedRegs(MF); 2655f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer} 2665f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 2675f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencerbool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, 2685f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer const MachineFunction &MF) const { 2695f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 2705f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer 27177ed8e4edf6ed78c53fb20ec3210aff2a59c9d87Ted Kremenek // Check if any overlapping register is modified. 27277ed8e4edf6ed78c53fb20ec3210aff2a59c9d87Ted Kremenek for (const unsigned *R = TRI->getOverlaps(PhysReg); *R; ++R) 27377ed8e4edf6ed78c53fb20ec3210aff2a59c9d87Ted Kremenek if (!def_empty(*R)) 27477ed8e4edf6ed78c53fb20ec3210aff2a59c9d87Ted Kremenek return false; 2752dc9ac73a8a34cabf261a81a1653d7379065ac61Ted Kremenek 276ec0aa78745f7b3bc96c20fffd1115bf26aaa0eadTed Kremenek // Check if any overlapping register is allocatable so it may be used later. 277e2563ca02a519c2ad6d64dfed87d6e86c5d3c072Sam Bishop if (AllocatableRegs.empty()) 2785f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer AllocatableRegs = TRI->getAllocatableSet(MF); 2795f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer for (const unsigned *R = TRI->getOverlaps(PhysReg); *R; ++R) 2805f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer if (AllocatableRegs.test(*R)) 2815f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return false; 2825f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer return true; 283c250aae4f645833aed3a6321bc8598f7330dce8dChris Lattner} 2845f016e2cb5d11daeb237544de1c5d59f20fe1a6eReid Spencer