MachineRegisterInfo.cpp revision 33f1c68cba4e905fdd2bf7d2848c52052d46fbff 
1//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Implementation of the MachineRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineRegisterInfo.h"
15using namespace llvm;
16
17MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
18  VRegInfo.reserve(256);
19  RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1.
20  UsedPhysRegs.resize(TRI.getNumRegs());
21
22  // Create the physreg use/def lists.
23  PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
24  memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
25}
26
27MachineRegisterInfo::~MachineRegisterInfo() {
28#ifndef NDEBUG
29  for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
30    assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
31  for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
32    assert(!PhysRegUseDefLists[i] &&
33           "PhysRegUseDefLists has entries after all instructions are deleted");
34#endif
35  delete [] PhysRegUseDefLists;
36}
37
38/// setRegClass - Set the register class of the specified virtual register.
39///
40void
41MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
42  unsigned VR = Reg;
43  Reg -= TargetRegisterInfo::FirstVirtualRegister;
44  assert(Reg < VRegInfo.size() && "Invalid vreg!");
45  const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
46  VRegInfo[Reg].first = RC;
47
48  // Remove from old register class's vregs list. This may be slow but
49  // fortunately this operation is rarely needed.
50  std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
51  std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR);
52  VRegs.erase(I);
53
54  // Add to new register class's vregs list.
55  RegClass2VRegMap[RC->getID()].push_back(VR);
56}
57
58/// createVirtualRegister - Create and return a new virtual register in the
59/// function with the specified register class.
60///
61unsigned
62MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
63  assert(RegClass && "Cannot create register without RegClass!");
64  // Add a reg, but keep track of whether the vector reallocated or not.
65  void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
66  VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
67
68  if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
69    // The vector reallocated, handle this now.
70    HandleVRegListReallocation();
71  unsigned VR = getLastVirtReg();
72  RegClass2VRegMap[RegClass->getID()].push_back(VR);
73  return VR;
74}
75
76/// HandleVRegListReallocation - We just added a virtual register to the
77/// VRegInfo info list and it reallocated.  Update the use/def lists info
78/// pointers.
79void MachineRegisterInfo::HandleVRegListReallocation() {
80  // The back pointers for the vreg lists point into the previous vector.
81  // Update them to point to their correct slots.
82  for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
83    MachineOperand *List = VRegInfo[i].second;
84    if (!List) continue;
85    // Update the back-pointer to be accurate once more.
86    List->Contents.Reg.Prev = &VRegInfo[i].second;
87  }
88}
89
90/// replaceRegWith - Replace all instances of FromReg with ToReg in the
91/// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
92/// except that it also changes any definitions of the register as well.
93void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
94  assert(FromReg != ToReg && "Cannot replace a reg with itself");
95
96  // TODO: This could be more efficient by bulk changing the operands.
97  for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
98    MachineOperand &O = I.getOperand();
99    ++I;
100    O.setReg(ToReg);
101  }
102}
103
104
105/// getVRegDef - Return the machine instr that defines the specified virtual
106/// register or null if none is found.  This assumes that the code is in SSA
107/// form, so there should only be one definition.
108MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
109  assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
110         "Invalid vreg!");
111  for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
112    // Since we are in SSA form, we can stop at the first definition.
113    if (I.getOperand().isDef())
114      return &*I;
115  }
116  return 0;
117}
118
119
120#ifndef NDEBUG
121void MachineRegisterInfo::dumpUses(unsigned Reg) const {
122  for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
123    I.getOperand().getParent()->dump();
124}
125#endif
126