MachineRegisterInfo.cpp revision 8d20b5f9ff609e70fae5c865931ab0f29e639d9c
1cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 2cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// 3cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// The LLVM Compiler Infrastructure 4cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// 5cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 6cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// License. See LICENSE.TXT for details. 7cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// 8cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)//===----------------------------------------------------------------------===// 9cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// 10cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// Implementation of the MachineRegisterInfo class. 11cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)// 12cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)//===----------------------------------------------------------------------===// 13cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 14cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "llvm/CodeGen/MachineRegisterInfo.h" 15cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "llvm/CodeGen/MachineInstrBuilder.h" 16cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "llvm/Target/TargetInstrInfo.h" 17cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#include "llvm/Target/TargetMachine.h" 18cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)using namespace llvm; 19cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 20cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) 21cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) : TRI(&TRI), IsSSA(true), TracksLiveness(true) { 22cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) VRegInfo.reserve(256); 23cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) RegAllocHints.reserve(256); 24cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) UsedRegUnits.resize(TRI.getNumRegUnits()); 25cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) UsedPhysRegMask.resize(TRI.getNumRegs()); 26cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 27cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Create the physreg use/def lists. 28cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 29cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 30cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 31cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 32cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)MachineRegisterInfo::~MachineRegisterInfo() { 33cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#ifndef NDEBUG 34cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) clearVirtRegs(); 35cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) 36cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert(!PhysRegUseDefLists[i] && 37cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) "PhysRegUseDefLists has entries after all instructions are deleted"); 38cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#endif 39cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) delete [] PhysRegUseDefLists; 40cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 41cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 42cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// setRegClass - Set the register class of the specified virtual register. 43cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// 44cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)void 45cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 46cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) VRegInfo[Reg].first = RC; 47cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 48cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 49cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)const TargetRegisterClass * 50cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)MachineRegisterInfo::constrainRegClass(unsigned Reg, 51cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const TargetRegisterClass *RC, 52cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) unsigned MinNumRegs) { 53cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const TargetRegisterClass *OldRC = getRegClass(Reg); 54cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (OldRC == RC) 55cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return RC; 56cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); 57cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (!NewRC || NewRC == OldRC) 58cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return NewRC; 59cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (NewRC->getNumRegs() < MinNumRegs) 60cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return 0; 61cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) setRegClass(Reg, NewRC); 62cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return NewRC; 63cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 64cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 65cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)bool 66cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { 67cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const TargetInstrInfo *TII = TM.getInstrInfo(); 68cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const TargetRegisterClass *OldRC = getRegClass(Reg); 69cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); 70cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 71cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Stop early if there is no room to grow. 72cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (NewRC == OldRC) 73cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return false; 74cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 75cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Accumulate constraints from all uses. 76cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; 77cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) ++I) { 78cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const TargetRegisterClass *OpRC = 79cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) I->getRegClassConstraint(I.getOperandNo(), TII, TRI); 80cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (unsigned SubIdx = I.getOperand().getSubReg()) { 81cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (OpRC) 82cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx); 83cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) else 84cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx); 85cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } else if (OpRC) 86cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) NewRC = TRI->getCommonSubClass(NewRC, OpRC); 87cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (!NewRC || NewRC == OldRC) 88cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return false; 89cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } 90cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) setRegClass(Reg, NewRC); 91cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return true; 92cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 93cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 94cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// createVirtualRegister - Create and return a new virtual register in the 95cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// function with the specified register class. 96cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// 97cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)unsigned 98cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 99cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert(RegClass && "Cannot create register without RegClass!"); 100cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert(RegClass->isAllocatable() && 101cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) "Virtual register RegClass must be allocatable."); 102cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 103cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // New virtual register number. 104cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 105cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) VRegInfo.grow(Reg); 106cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) VRegInfo[Reg].first = RegClass; 107cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) RegAllocHints.grow(Reg); 108cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return Reg; 109cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 110cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 111cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// clearVirtRegs - Remove all virtual registers (after physreg assignment). 112cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)void MachineRegisterInfo::clearVirtRegs() { 113cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#ifndef NDEBUG 114cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 115cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 && 116cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) "Vreg use list non-empty still?"); 117cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#endif 118cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) VRegInfo.clear(); 119cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 120cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 121cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// Add MO to the linked list of operands for its register. 122cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) { 123cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert(!MO->isOnRegUseList() && "Already on list"); 124cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 125cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MachineOperand *const Head = HeadRef; 126cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 127cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Head points to the first list element. 128cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Next is NULL on the last list element. 129cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Prev pointers are circular, so Head->Prev == Last. 130cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 131cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Head is NULL for an empty list. 132cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (!Head) { 133cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MO->Contents.Reg.Prev = MO; 134cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MO->Contents.Reg.Next = 0; 135cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) HeadRef = MO; 136cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return; 137cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } 138cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert(MO->getReg() == Head->getReg() && "Different regs on the same list!"); 139cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 140cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Insert MO between Last and Head in the circular Prev chain. 141cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MachineOperand *Last = Head->Contents.Reg.Prev; 142cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert(Last && "Inconsistent use list"); 143cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert(MO->getReg() == Last->getReg() && "Different regs on the same list!"); 144cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) Head->Contents.Reg.Prev = MO; 145cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MO->Contents.Reg.Prev = Last; 146cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 147cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Def operands always precede uses. This allows def_iterator to stop early. 148cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Insert def operands at the front, and use operands at the back. 149cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (MO->isDef()) { 150cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Insert def at the front. 151cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MO->Contents.Reg.Next = Head; 152cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) HeadRef = MO; 153cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } else { 154cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Insert use at the end. 155cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MO->Contents.Reg.Next = 0; 156cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) Last->Contents.Reg.Next = MO; 157cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } 158cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 159cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 160cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// Remove MO from its use-def list. 161cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) { 162cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert(MO->isOnRegUseList() && "Operand not on use list"); 163cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 164cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MachineOperand *const Head = HeadRef; 165cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert(Head && "List already empty"); 166cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 167cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Unlink this from the doubly linked list of operands. 168cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MachineOperand *Next = MO->Contents.Reg.Next; 169cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MachineOperand *Prev = MO->Contents.Reg.Prev; 170cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 171cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Prev links are circular, next link is NULL instead of looping back to Head. 172cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (MO == Head) 173cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) HeadRef = Next; 174cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) else 175cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) Prev->Contents.Reg.Next = Next; 176cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 177cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) (Next ? Next : Head)->Contents.Reg.Prev = Prev; 178cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 179cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MO->Contents.Reg.Prev = 0; 180cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MO->Contents.Reg.Next = 0; 181cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 182cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 183cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// replaceRegWith - Replace all instances of FromReg with ToReg in the 184cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 185cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// except that it also changes any definitions of the register as well. 186cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 187cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert(FromReg != ToReg && "Cannot replace a reg with itself"); 188cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 189cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // TODO: This could be more efficient by bulk changing the operands. 190cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 191cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) MachineOperand &O = I.getOperand(); 192cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) ++I; 193cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) O.setReg(ToReg); 194cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } 195cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 196cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 197cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 198cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// getVRegDef - Return the machine instr that defines the specified virtual 199cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// register or null if none is found. This assumes that the code is in SSA 200cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// form, so there should only be one definition. 201cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 202cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Since we are in SSA form, we can use the first definition. 203cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) def_iterator I = def_begin(Reg); 204cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert((I.atEnd() || llvm::next(I) == def_end()) && 205cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) "getVRegDef assumes a single definition or no definition"); 206cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return !I.atEnd() ? &*I : 0; 207cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 208cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 209cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// getUniqueVRegDef - Return the unique machine instr that defines the 210cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// specified virtual register or null if none is found. If there are 211cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// multiple definitions or no definition, return null. 212cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const { 213cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (def_empty(Reg)) return 0; 214cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) def_iterator I = def_begin(Reg); 215cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (llvm::next(I) != def_end()) 216cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return 0; 217cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return &*I; 218cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 219cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 220cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 221cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) use_nodbg_iterator UI = use_nodbg_begin(RegNo); 222cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (UI == use_nodbg_end()) 223cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return false; 224cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return ++UI == use_nodbg_end(); 225cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 226cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 227cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// clearKillFlags - Iterate over all the uses of the given register and 228cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// clear the kill flag from the MachineOperand. This function is used by 229cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// optimization passes which extend register lifetimes and need only 230cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// preserve conservative kill flag information. 231cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 232cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 233cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) UI.getOperand().setIsKill(false); 234cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 235cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 236cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 237cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 238cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (I->first == Reg || I->second == Reg) 239cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return true; 240cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return false; 241cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 242cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 243cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)bool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 244cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 245cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (*I == Reg) 246cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return true; 247cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return false; 248cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 249cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 250cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 251cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// corresponding live-in physical register. 252cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 253cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 254cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (I->second == VReg) 255cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return I->first; 256cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return 0; 257cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 258cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 259cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// getLiveInVirtReg - If PReg is a live-in physical register, return the 260cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// corresponding live-in physical register. 261cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 262cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 263cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (I->first == PReg) 264cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return I->second; 265cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return 0; 266cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 267cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 268cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 269cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)/// into the given entry block. 270cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)void 271cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 272cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const TargetRegisterInfo &TRI, 273cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const TargetInstrInfo &TII) { 274cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Emit the copies into the top of the block. 275cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 276cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (LiveIns[i].second) { 277cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (use_empty(LiveIns[i].second)) { 278cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // The livein has no uses. Drop it. 279cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // 280cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // It would be preferable to have isel avoid creating live-in 281cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // records for unused arguments in the first place, but it's 282cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // complicated by the debug info code for arguments. 283cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) LiveIns.erase(LiveIns.begin() + i); 284cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) --i; --e; 285cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } else { 286cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Emit a copy. 287cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 288cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) TII.get(TargetOpcode::COPY), LiveIns[i].second) 289cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) .addReg(LiveIns[i].first); 290cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 291cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Add the register to the entry block live-in set. 292cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) EntryMBB->addLiveIn(LiveIns[i].first); 293cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } 294cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } else { 295cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Add the register to the entry block live-in set. 296cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) EntryMBB->addLiveIn(LiveIns[i].first); 297cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } 298cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 299cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 300cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#ifndef NDEBUG 301cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)void MachineRegisterInfo::dumpUses(unsigned Reg) const { 302cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 303cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) I.getOperand().getParent()->dump(); 304cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 305cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#endif 306cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 307cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 308cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert (!reservedRegsFrozen() && 309cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) "freezeReservedRegs should only be called once!"); 310cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) ReservedRegs = TRI->getReservedRegs(MF); 311cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert(ReservedRegs.size() == TRI->getNumRegs() && 312cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) "Invalid ReservedRegs vector from target"); 313cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 314cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 315cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, 316cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const MachineFunction &MF) const { 317 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 318 319 // Check if any overlapping register is modified, or allocatable so it may be 320 // used later. 321 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) 322 if (!def_empty(*AI) || isAllocatable(*AI)) 323 return false; 324 return true; 325} 326