MachineRegisterInfo.cpp revision aba6559370c3d453588103fb667ffa3b11b76652
1424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 2424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)// 3424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)// The LLVM Compiler Infrastructure 4a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)// 5424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 6424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)// License. See LICENSE.TXT for details. 7424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)// 8a02191e04bc25c4935f804f2c080ae28663d096dBen Murdoch//===----------------------------------------------------------------------===// 95f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)// 10424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)// Implementation of the MachineRegisterInfo class. 11424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)// 12a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)//===----------------------------------------------------------------------===// 13a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) 14a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)#include "llvm/CodeGen/MachineRegisterInfo.h" 15424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)#include "llvm/CodeGen/MachineInstrBuilder.h" 16424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)#include "llvm/Target/TargetInstrInfo.h" 17424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)#include "llvm/Target/TargetMachine.h" 18424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)using namespace llvm; 19a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) 20a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) 21424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) : TRI(&TRI), IsSSA(true), TracksLiveness(true) { 22424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) VRegInfo.reserve(256); 23424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) RegAllocHints.reserve(256); 24424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) UsedPhysRegs.resize(TRI.getNumRegs()); 25424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) UsedPhysRegMask.resize(TRI.getNumRegs()); 26424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 27424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) // Create the physreg use/def lists. 28424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 29424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 30424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)} 31424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 32424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)MachineRegisterInfo::~MachineRegisterInfo() { 33424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)#ifndef NDEBUG 34424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) clearVirtRegs(); 35424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 36a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) assert(!PhysRegUseDefLists[i] && 37a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) "PhysRegUseDefLists has entries after all instructions are deleted"); 38a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)#endif 39a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) delete [] PhysRegUseDefLists; 40a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)} 411320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci 42a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)/// setRegClass - Set the register class of the specified virtual register. 43a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)/// 44a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)void 45a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 46a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) VRegInfo[Reg].first = RC; 47a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)} 481320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci 495d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)const TargetRegisterClass * 505d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)MachineRegisterInfo::constrainRegClass(unsigned Reg, 51a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) const TargetRegisterClass *RC, 52a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) unsigned MinNumRegs) { 53a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) const TargetRegisterClass *OldRC = getRegClass(Reg); 541320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci if (OldRC == RC) 551320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci return RC; 56a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); 57a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) if (!NewRC || NewRC == OldRC) 58cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return NewRC; 59cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (NewRC->getNumRegs() < MinNumRegs) 60cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return 0; 61424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) setRegClass(Reg, NewRC); 62010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return NewRC; 63010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)} 64010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 65010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)bool 66010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { 67010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) const TargetInstrInfo *TII = TM.getInstrInfo(); 68010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) const TargetRegisterClass *OldRC = getRegClass(Reg); 69010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); 70010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 71010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) // Stop early if there is no room to grow. 72010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) if (NewRC == OldRC) 73010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return false; 74010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 75010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) // Accumulate constraints from all uses. 76cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; 77cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) ++I) { 78cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) const TargetRegisterClass *OpRC = 79cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) I->getRegClassConstraint(I.getOperandNo(), TII, TRI); 801320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci if (unsigned SubIdx = I.getOperand().getSubReg()) { 811320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci if (OpRC) 821320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx); 831320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci else 841320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx); 851320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci } else if (OpRC) 861320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci NewRC = TRI->getCommonSubClass(NewRC, OpRC); 87cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) if (!NewRC || NewRC == OldRC) 88cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return false; 89cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) } 90cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) setRegClass(Reg, NewRC); 91cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return true; 92cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 93010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 94010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)/// createVirtualRegister - Create and return a new virtual register in the 95a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)/// function with the specified register class. 96424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)/// 97a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)unsigned 98424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 99424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) assert(RegClass && "Cannot create register without RegClass!"); 100cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) assert(RegClass->isAllocatable() && 101424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) "Virtual register RegClass must be allocatable."); 102a02191e04bc25c4935f804f2c080ae28663d096dBen Murdoch 103a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) // New virtual register number. 104effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 105424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 106a02191e04bc25c4935f804f2c080ae28663d096dBen Murdoch // Add a reg, but keep track of whether the vector reallocated or not. 107a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0); 108cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg]; 109424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) VRegInfo.grow(Reg); 110a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) VRegInfo[Reg].first = RegClass; 111a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) RegAllocHints.grow(Reg); 112a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 113a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase) 114a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // The vector reallocated, handle this now. 115a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) HandleVRegListReallocation(); 116a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) return Reg; 117a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)} 118a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 119a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)/// clearVirtRegs - Remove all virtual registers (after physreg assignment). 120a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)void MachineRegisterInfo::clearVirtRegs() { 121a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)#ifndef NDEBUG 122116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 1231320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 && 124116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch "Vreg use list non-empty still?"); 125a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)#endif 126a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) VRegInfo.clear(); 127a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)} 128424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 129424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)/// HandleVRegListReallocation - We just added a virtual register to the 130424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)/// VRegInfo info list and it reallocated. Update the use/def lists info 131a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)/// pointers. 132424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)void MachineRegisterInfo::HandleVRegListReallocation() { 13323730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) // The back pointers for the vreg lists point into the previous vector. 134424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) // Update them to point to their correct slots. 135424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { 136a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 137424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) MachineOperand *List = VRegInfo[Reg].second; 13823730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) if (!List) continue; 139424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) // Update the back-pointer to be accurate once more. 140424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) List->Contents.Reg.Prev = &VRegInfo[Reg].second; 141a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) } 142424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)} 143424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 144a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)/// replaceRegWith - Replace all instances of FromReg with ToReg in the 145424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 146424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)/// except that it also changes any definitions of the register as well. 147a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 148a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) assert(FromReg != ToReg && "Cannot replace a reg with itself"); 149a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 150424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) // TODO: This could be more efficient by bulk changing the operands. 151010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 152424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) MachineOperand &O = I.getOperand(); 153424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) ++I; 154424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) O.setReg(ToReg); 155424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) } 1565f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)} 1575f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 158424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 159424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)/// getVRegDef - Return the machine instr that defines the specified virtual 160010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)/// register or null if none is found. This assumes that the code is in SSA 161424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)/// form, so there should only be one definition. 1626e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles)MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 1635f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) // Since we are in SSA form, we can use the first definition. 164f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) def_iterator I = def_begin(Reg); 1655f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) return !I.atEnd() ? &*I : 0; 166010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)} 167f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) 168010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const { 169a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) use_iterator UI = use_begin(RegNo); 170f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) if (UI == use_end()) 171f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) return false; 172f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) return ++UI == use_end(); 173424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)} 174a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 175a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 176a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) use_nodbg_iterator UI = use_nodbg_begin(RegNo); 177010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) if (UI == use_nodbg_end()) 178a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) return false; 179a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) return ++UI == use_nodbg_end(); 180a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)} 1815f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 1825f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// clearKillFlags - Iterate over all the uses of the given register and 183a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)/// clear the kill flag from the MachineOperand. This function is used by 1846e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles)/// optimization passes which extend register lifetimes and need only 1855f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// preserve conservative kill flag information. 186a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 1875f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 188010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) UI.getOperand().setIsKill(false); 189010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)} 190a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 191a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 19223730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 193a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) if (I->first == Reg || I->second == Reg) 194010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return true; 195010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return false; 196010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)} 197010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 198010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)bool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 199010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 200010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) if (*I == Reg) 201010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return true; 202010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return false; 203010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)} 204010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 205010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 2065f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/// corresponding live-in physical register. 2075f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 208010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 2096e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles) if (I->second == VReg) 2105f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) return I->first; 211010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return 0; 2125f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)} 213010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 214010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)/// getLiveInVirtReg - If PReg is a live-in physical register, return the 215010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)/// corresponding live-in physical register. 216010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 217010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 218010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) if (I->first == PReg) 219010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return I->second; 220010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) return 0; 221010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)} 222010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) 223010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 224010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)/// into the given entry block. 225010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles)void 226a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 2271320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci const TargetRegisterInfo &TRI, 2281320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci const TargetInstrInfo &TII) { 2291320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci // Emit the copies into the top of the block. 2301320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 2311320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci if (LiveIns[i].second) { 2321320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci if (use_empty(LiveIns[i].second)) { 2331320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci // The livein has no uses. Drop it. 2341320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci // 2351320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci // It would be preferable to have isel avoid creating live-in 2361320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci // records for unused arguments in the first place, but it's 2371320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci // complicated by the debug info code for arguments. 2381320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci LiveIns.erase(LiveIns.begin() + i); 2391320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci --i; --e; 240 } else { 241 // Emit a copy. 242 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 243 TII.get(TargetOpcode::COPY), LiveIns[i].second) 244 .addReg(LiveIns[i].first); 245 246 // Add the register to the entry block live-in set. 247 EntryMBB->addLiveIn(LiveIns[i].first); 248 } 249 } else { 250 // Add the register to the entry block live-in set. 251 EntryMBB->addLiveIn(LiveIns[i].first); 252 } 253} 254 255#ifndef NDEBUG 256void MachineRegisterInfo::dumpUses(unsigned Reg) const { 257 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 258 I.getOperand().getParent()->dump(); 259} 260#endif 261 262void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 263 ReservedRegs = TRI->getReservedRegs(MF); 264} 265 266bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, 267 const MachineFunction &MF) const { 268 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 269 270 // Check if any overlapping register is modified. 271 for (const uint16_t *R = TRI->getOverlaps(PhysReg); *R; ++R) 272 if (!def_empty(*R)) 273 return false; 274 275 // Check if any overlapping register is allocatable so it may be used later. 276 if (AllocatableRegs.empty()) 277 AllocatableRegs = TRI->getAllocatableSet(MF); 278 for (const uint16_t *R = TRI->getOverlaps(PhysReg); *R; ++R) 279 if (AllocatableRegs.test(*R)) 280 return false; 281 return true; 282} 283