MachineVerifier.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Pass to verify generated machine code. The following is checked: 11// 12// Operand counts: All explicit operands must be present. 13// 14// Register classes: All physical and virtual register operands must be 15// compatible with the register class required by the instruction descriptor. 16// 17// Register live intervals: Registers must be defined only once, and must be 18// defined before use. 19// 20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the 21// command-line option -verify-machineinstrs, or by defining the environment 22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive 23// the verifier errors. 24//===----------------------------------------------------------------------===// 25 26#include "llvm/CodeGen/Passes.h" 27#include "llvm/ADT/DenseSet.h" 28#include "llvm/ADT/DepthFirstIterator.h" 29#include "llvm/ADT/SetOperations.h" 30#include "llvm/ADT/SmallVector.h" 31#include "llvm/CodeGen/LiveIntervalAnalysis.h" 32#include "llvm/CodeGen/LiveStackAnalysis.h" 33#include "llvm/CodeGen/LiveVariables.h" 34#include "llvm/CodeGen/MachineFrameInfo.h" 35#include "llvm/CodeGen/MachineFunctionPass.h" 36#include "llvm/CodeGen/MachineInstrBundle.h" 37#include "llvm/CodeGen/MachineMemOperand.h" 38#include "llvm/CodeGen/MachineRegisterInfo.h" 39#include "llvm/IR/BasicBlock.h" 40#include "llvm/IR/InlineAsm.h" 41#include "llvm/IR/Instructions.h" 42#include "llvm/MC/MCAsmInfo.h" 43#include "llvm/Support/Debug.h" 44#include "llvm/Support/ErrorHandling.h" 45#include "llvm/Support/raw_ostream.h" 46#include "llvm/Target/TargetInstrInfo.h" 47#include "llvm/Target/TargetMachine.h" 48#include "llvm/Target/TargetRegisterInfo.h" 49using namespace llvm; 50 51namespace { 52 struct MachineVerifier { 53 54 MachineVerifier(Pass *pass, const char *b) : 55 PASS(pass), 56 Banner(b), 57 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS")) 58 {} 59 60 bool runOnMachineFunction(MachineFunction &MF); 61 62 Pass *const PASS; 63 const char *Banner; 64 const char *const OutFileName; 65 raw_ostream *OS; 66 const MachineFunction *MF; 67 const TargetMachine *TM; 68 const TargetInstrInfo *TII; 69 const TargetRegisterInfo *TRI; 70 const MachineRegisterInfo *MRI; 71 72 unsigned foundErrors; 73 74 typedef SmallVector<unsigned, 16> RegVector; 75 typedef SmallVector<const uint32_t*, 4> RegMaskVector; 76 typedef DenseSet<unsigned> RegSet; 77 typedef DenseMap<unsigned, const MachineInstr*> RegMap; 78 typedef SmallPtrSet<const MachineBasicBlock*, 8> BlockSet; 79 80 const MachineInstr *FirstTerminator; 81 BlockSet FunctionBlocks; 82 83 BitVector regsReserved; 84 RegSet regsLive; 85 RegVector regsDefined, regsDead, regsKilled; 86 RegMaskVector regMasks; 87 RegSet regsLiveInButUnused; 88 89 SlotIndex lastIndex; 90 91 // Add Reg and any sub-registers to RV 92 void addRegWithSubRegs(RegVector &RV, unsigned Reg) { 93 RV.push_back(Reg); 94 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 95 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 96 RV.push_back(*SubRegs); 97 } 98 99 struct BBInfo { 100 // Is this MBB reachable from the MF entry point? 101 bool reachable; 102 103 // Vregs that must be live in because they are used without being 104 // defined. Map value is the user. 105 RegMap vregsLiveIn; 106 107 // Regs killed in MBB. They may be defined again, and will then be in both 108 // regsKilled and regsLiveOut. 109 RegSet regsKilled; 110 111 // Regs defined in MBB and live out. Note that vregs passing through may 112 // be live out without being mentioned here. 113 RegSet regsLiveOut; 114 115 // Vregs that pass through MBB untouched. This set is disjoint from 116 // regsKilled and regsLiveOut. 117 RegSet vregsPassed; 118 119 // Vregs that must pass through MBB because they are needed by a successor 120 // block. This set is disjoint from regsLiveOut. 121 RegSet vregsRequired; 122 123 // Set versions of block's predecessor and successor lists. 124 BlockSet Preds, Succs; 125 126 BBInfo() : reachable(false) {} 127 128 // Add register to vregsPassed if it belongs there. Return true if 129 // anything changed. 130 bool addPassed(unsigned Reg) { 131 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 132 return false; 133 if (regsKilled.count(Reg) || regsLiveOut.count(Reg)) 134 return false; 135 return vregsPassed.insert(Reg).second; 136 } 137 138 // Same for a full set. 139 bool addPassed(const RegSet &RS) { 140 bool changed = false; 141 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) 142 if (addPassed(*I)) 143 changed = true; 144 return changed; 145 } 146 147 // Add register to vregsRequired if it belongs there. Return true if 148 // anything changed. 149 bool addRequired(unsigned Reg) { 150 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 151 return false; 152 if (regsLiveOut.count(Reg)) 153 return false; 154 return vregsRequired.insert(Reg).second; 155 } 156 157 // Same for a full set. 158 bool addRequired(const RegSet &RS) { 159 bool changed = false; 160 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) 161 if (addRequired(*I)) 162 changed = true; 163 return changed; 164 } 165 166 // Same for a full map. 167 bool addRequired(const RegMap &RM) { 168 bool changed = false; 169 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I) 170 if (addRequired(I->first)) 171 changed = true; 172 return changed; 173 } 174 175 // Live-out registers are either in regsLiveOut or vregsPassed. 176 bool isLiveOut(unsigned Reg) const { 177 return regsLiveOut.count(Reg) || vregsPassed.count(Reg); 178 } 179 }; 180 181 // Extra register info per MBB. 182 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap; 183 184 bool isReserved(unsigned Reg) { 185 return Reg < regsReserved.size() && regsReserved.test(Reg); 186 } 187 188 bool isAllocatable(unsigned Reg) { 189 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg); 190 } 191 192 // Analysis information if available 193 LiveVariables *LiveVars; 194 LiveIntervals *LiveInts; 195 LiveStacks *LiveStks; 196 SlotIndexes *Indexes; 197 198 void visitMachineFunctionBefore(); 199 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB); 200 void visitMachineBundleBefore(const MachineInstr *MI); 201 void visitMachineInstrBefore(const MachineInstr *MI); 202 void visitMachineOperand(const MachineOperand *MO, unsigned MONum); 203 void visitMachineInstrAfter(const MachineInstr *MI); 204 void visitMachineBundleAfter(const MachineInstr *MI); 205 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB); 206 void visitMachineFunctionAfter(); 207 208 void report(const char *msg, const MachineFunction *MF); 209 void report(const char *msg, const MachineBasicBlock *MBB); 210 void report(const char *msg, const MachineInstr *MI); 211 void report(const char *msg, const MachineOperand *MO, unsigned MONum); 212 void report(const char *msg, const MachineFunction *MF, 213 const LiveInterval &LI); 214 void report(const char *msg, const MachineBasicBlock *MBB, 215 const LiveInterval &LI); 216 void report(const char *msg, const MachineFunction *MF, 217 const LiveRange &LR); 218 void report(const char *msg, const MachineBasicBlock *MBB, 219 const LiveRange &LR); 220 221 void verifyInlineAsm(const MachineInstr *MI); 222 223 void checkLiveness(const MachineOperand *MO, unsigned MONum); 224 void markReachable(const MachineBasicBlock *MBB); 225 void calcRegsPassed(); 226 void checkPHIOps(const MachineBasicBlock *MBB); 227 228 void calcRegsRequired(); 229 void verifyLiveVariables(); 230 void verifyLiveIntervals(); 231 void verifyLiveInterval(const LiveInterval&); 232 void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned); 233 void verifyLiveRangeSegment(const LiveRange&, 234 const LiveRange::const_iterator I, unsigned); 235 void verifyLiveRange(const LiveRange&, unsigned); 236 237 void verifyStackFrame(); 238 }; 239 240 struct MachineVerifierPass : public MachineFunctionPass { 241 static char ID; // Pass ID, replacement for typeid 242 const char *const Banner; 243 244 MachineVerifierPass(const char *b = 0) 245 : MachineFunctionPass(ID), Banner(b) { 246 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry()); 247 } 248 249 void getAnalysisUsage(AnalysisUsage &AU) const override { 250 AU.setPreservesAll(); 251 MachineFunctionPass::getAnalysisUsage(AU); 252 } 253 254 bool runOnMachineFunction(MachineFunction &MF) override { 255 MF.verify(this, Banner); 256 return false; 257 } 258 }; 259 260} 261 262char MachineVerifierPass::ID = 0; 263INITIALIZE_PASS(MachineVerifierPass, "machineverifier", 264 "Verify generated machine code", false, false) 265 266FunctionPass *llvm::createMachineVerifierPass(const char *Banner) { 267 return new MachineVerifierPass(Banner); 268} 269 270void MachineFunction::verify(Pass *p, const char *Banner) const { 271 MachineVerifier(p, Banner) 272 .runOnMachineFunction(const_cast<MachineFunction&>(*this)); 273} 274 275bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) { 276 raw_ostream *OutFile = 0; 277 if (OutFileName) { 278 std::string ErrorInfo; 279 OutFile = new raw_fd_ostream(OutFileName, ErrorInfo, 280 sys::fs::F_Append | sys::fs::F_Text); 281 if (!ErrorInfo.empty()) { 282 errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n'; 283 exit(1); 284 } 285 286 OS = OutFile; 287 } else { 288 OS = &errs(); 289 } 290 291 foundErrors = 0; 292 293 this->MF = &MF; 294 TM = &MF.getTarget(); 295 TII = TM->getInstrInfo(); 296 TRI = TM->getRegisterInfo(); 297 MRI = &MF.getRegInfo(); 298 299 LiveVars = NULL; 300 LiveInts = NULL; 301 LiveStks = NULL; 302 Indexes = NULL; 303 if (PASS) { 304 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>(); 305 // We don't want to verify LiveVariables if LiveIntervals is available. 306 if (!LiveInts) 307 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>(); 308 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>(); 309 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>(); 310 } 311 312 visitMachineFunctionBefore(); 313 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end(); 314 MFI!=MFE; ++MFI) { 315 visitMachineBasicBlockBefore(MFI); 316 // Keep track of the current bundle header. 317 const MachineInstr *CurBundle = 0; 318 // Do we expect the next instruction to be part of the same bundle? 319 bool InBundle = false; 320 321 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(), 322 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) { 323 if (MBBI->getParent() != MFI) { 324 report("Bad instruction parent pointer", MFI); 325 *OS << "Instruction: " << *MBBI; 326 continue; 327 } 328 329 // Check for consistent bundle flags. 330 if (InBundle && !MBBI->isBundledWithPred()) 331 report("Missing BundledPred flag, " 332 "BundledSucc was set on predecessor", MBBI); 333 if (!InBundle && MBBI->isBundledWithPred()) 334 report("BundledPred flag is set, " 335 "but BundledSucc not set on predecessor", MBBI); 336 337 // Is this a bundle header? 338 if (!MBBI->isInsideBundle()) { 339 if (CurBundle) 340 visitMachineBundleAfter(CurBundle); 341 CurBundle = MBBI; 342 visitMachineBundleBefore(CurBundle); 343 } else if (!CurBundle) 344 report("No bundle header", MBBI); 345 visitMachineInstrBefore(MBBI); 346 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) 347 visitMachineOperand(&MBBI->getOperand(I), I); 348 visitMachineInstrAfter(MBBI); 349 350 // Was this the last bundled instruction? 351 InBundle = MBBI->isBundledWithSucc(); 352 } 353 if (CurBundle) 354 visitMachineBundleAfter(CurBundle); 355 if (InBundle) 356 report("BundledSucc flag set on last instruction in block", &MFI->back()); 357 visitMachineBasicBlockAfter(MFI); 358 } 359 visitMachineFunctionAfter(); 360 361 if (OutFile) 362 delete OutFile; 363 else if (foundErrors) 364 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors."); 365 366 // Clean up. 367 regsLive.clear(); 368 regsDefined.clear(); 369 regsDead.clear(); 370 regsKilled.clear(); 371 regMasks.clear(); 372 regsLiveInButUnused.clear(); 373 MBBInfoMap.clear(); 374 375 return false; // no changes 376} 377 378void MachineVerifier::report(const char *msg, const MachineFunction *MF) { 379 assert(MF); 380 *OS << '\n'; 381 if (!foundErrors++) { 382 if (Banner) 383 *OS << "# " << Banner << '\n'; 384 MF->print(*OS, Indexes); 385 } 386 *OS << "*** Bad machine code: " << msg << " ***\n" 387 << "- function: " << MF->getName() << "\n"; 388} 389 390void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) { 391 assert(MBB); 392 report(msg, MBB->getParent()); 393 *OS << "- basic block: BB#" << MBB->getNumber() 394 << ' ' << MBB->getName() 395 << " (" << (const void*)MBB << ')'; 396 if (Indexes) 397 *OS << " [" << Indexes->getMBBStartIdx(MBB) 398 << ';' << Indexes->getMBBEndIdx(MBB) << ')'; 399 *OS << '\n'; 400} 401 402void MachineVerifier::report(const char *msg, const MachineInstr *MI) { 403 assert(MI); 404 report(msg, MI->getParent()); 405 *OS << "- instruction: "; 406 if (Indexes && Indexes->hasIndex(MI)) 407 *OS << Indexes->getInstructionIndex(MI) << '\t'; 408 MI->print(*OS, TM); 409} 410 411void MachineVerifier::report(const char *msg, 412 const MachineOperand *MO, unsigned MONum) { 413 assert(MO); 414 report(msg, MO->getParent()); 415 *OS << "- operand " << MONum << ": "; 416 MO->print(*OS, TM); 417 *OS << "\n"; 418} 419 420void MachineVerifier::report(const char *msg, const MachineFunction *MF, 421 const LiveInterval &LI) { 422 report(msg, MF); 423 *OS << "- interval: " << LI << '\n'; 424} 425 426void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB, 427 const LiveInterval &LI) { 428 report(msg, MBB); 429 *OS << "- interval: " << LI << '\n'; 430} 431 432void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB, 433 const LiveRange &LR) { 434 report(msg, MBB); 435 *OS << "- liverange: " << LR << "\n"; 436} 437 438void MachineVerifier::report(const char *msg, const MachineFunction *MF, 439 const LiveRange &LR) { 440 report(msg, MF); 441 *OS << "- liverange: " << LR << "\n"; 442} 443 444void MachineVerifier::markReachable(const MachineBasicBlock *MBB) { 445 BBInfo &MInfo = MBBInfoMap[MBB]; 446 if (!MInfo.reachable) { 447 MInfo.reachable = true; 448 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), 449 SuE = MBB->succ_end(); SuI != SuE; ++SuI) 450 markReachable(*SuI); 451 } 452} 453 454void MachineVerifier::visitMachineFunctionBefore() { 455 lastIndex = SlotIndex(); 456 regsReserved = MRI->getReservedRegs(); 457 458 // A sub-register of a reserved register is also reserved 459 for (int Reg = regsReserved.find_first(); Reg>=0; 460 Reg = regsReserved.find_next(Reg)) { 461 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { 462 // FIXME: This should probably be: 463 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register"); 464 regsReserved.set(*SubRegs); 465 } 466 } 467 468 markReachable(&MF->front()); 469 470 // Build a set of the basic blocks in the function. 471 FunctionBlocks.clear(); 472 for (MachineFunction::const_iterator 473 I = MF->begin(), E = MF->end(); I != E; ++I) { 474 FunctionBlocks.insert(I); 475 BBInfo &MInfo = MBBInfoMap[I]; 476 477 MInfo.Preds.insert(I->pred_begin(), I->pred_end()); 478 if (MInfo.Preds.size() != I->pred_size()) 479 report("MBB has duplicate entries in its predecessor list.", I); 480 481 MInfo.Succs.insert(I->succ_begin(), I->succ_end()); 482 if (MInfo.Succs.size() != I->succ_size()) 483 report("MBB has duplicate entries in its successor list.", I); 484 } 485 486 // Check that the register use lists are sane. 487 MRI->verifyUseLists(); 488 489 verifyStackFrame(); 490} 491 492// Does iterator point to a and b as the first two elements? 493static bool matchPair(MachineBasicBlock::const_succ_iterator i, 494 const MachineBasicBlock *a, const MachineBasicBlock *b) { 495 if (*i == a) 496 return *++i == b; 497 if (*i == b) 498 return *++i == a; 499 return false; 500} 501 502void 503MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { 504 FirstTerminator = 0; 505 506 if (MRI->isSSA()) { 507 // If this block has allocatable physical registers live-in, check that 508 // it is an entry block or landing pad. 509 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(), 510 LE = MBB->livein_end(); 511 LI != LE; ++LI) { 512 unsigned reg = *LI; 513 if (isAllocatable(reg) && !MBB->isLandingPad() && 514 MBB != MBB->getParent()->begin()) { 515 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB); 516 } 517 } 518 } 519 520 // Count the number of landing pad successors. 521 SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs; 522 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(), 523 E = MBB->succ_end(); I != E; ++I) { 524 if ((*I)->isLandingPad()) 525 LandingPadSuccs.insert(*I); 526 if (!FunctionBlocks.count(*I)) 527 report("MBB has successor that isn't part of the function.", MBB); 528 if (!MBBInfoMap[*I].Preds.count(MBB)) { 529 report("Inconsistent CFG", MBB); 530 *OS << "MBB is not in the predecessor list of the successor BB#" 531 << (*I)->getNumber() << ".\n"; 532 } 533 } 534 535 // Check the predecessor list. 536 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(), 537 E = MBB->pred_end(); I != E; ++I) { 538 if (!FunctionBlocks.count(*I)) 539 report("MBB has predecessor that isn't part of the function.", MBB); 540 if (!MBBInfoMap[*I].Succs.count(MBB)) { 541 report("Inconsistent CFG", MBB); 542 *OS << "MBB is not in the successor list of the predecessor BB#" 543 << (*I)->getNumber() << ".\n"; 544 } 545 } 546 547 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo(); 548 const BasicBlock *BB = MBB->getBasicBlock(); 549 if (LandingPadSuccs.size() > 1 && 550 !(AsmInfo && 551 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj && 552 BB && isa<SwitchInst>(BB->getTerminator()))) 553 report("MBB has more than one landing pad successor", MBB); 554 555 // Call AnalyzeBranch. If it succeeds, there several more conditions to check. 556 MachineBasicBlock *TBB = 0, *FBB = 0; 557 SmallVector<MachineOperand, 4> Cond; 558 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB), 559 TBB, FBB, Cond)) { 560 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's 561 // check whether its answers match up with reality. 562 if (!TBB && !FBB) { 563 // Block falls through to its successor. 564 MachineFunction::const_iterator MBBI = MBB; 565 ++MBBI; 566 if (MBBI == MF->end()) { 567 // It's possible that the block legitimately ends with a noreturn 568 // call or an unreachable, in which case it won't actually fall 569 // out the bottom of the function. 570 } else if (MBB->succ_size() == LandingPadSuccs.size()) { 571 // It's possible that the block legitimately ends with a noreturn 572 // call or an unreachable, in which case it won't actuall fall 573 // out of the block. 574 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) { 575 report("MBB exits via unconditional fall-through but doesn't have " 576 "exactly one CFG successor!", MBB); 577 } else if (!MBB->isSuccessor(MBBI)) { 578 report("MBB exits via unconditional fall-through but its successor " 579 "differs from its CFG successor!", MBB); 580 } 581 if (!MBB->empty() && getBundleStart(&MBB->back())->isBarrier() && 582 !TII->isPredicated(getBundleStart(&MBB->back()))) { 583 report("MBB exits via unconditional fall-through but ends with a " 584 "barrier instruction!", MBB); 585 } 586 if (!Cond.empty()) { 587 report("MBB exits via unconditional fall-through but has a condition!", 588 MBB); 589 } 590 } else if (TBB && !FBB && Cond.empty()) { 591 // Block unconditionally branches somewhere. 592 if (MBB->succ_size() != 1+LandingPadSuccs.size()) { 593 report("MBB exits via unconditional branch but doesn't have " 594 "exactly one CFG successor!", MBB); 595 } else if (!MBB->isSuccessor(TBB)) { 596 report("MBB exits via unconditional branch but the CFG " 597 "successor doesn't match the actual successor!", MBB); 598 } 599 if (MBB->empty()) { 600 report("MBB exits via unconditional branch but doesn't contain " 601 "any instructions!", MBB); 602 } else if (!getBundleStart(&MBB->back())->isBarrier()) { 603 report("MBB exits via unconditional branch but doesn't end with a " 604 "barrier instruction!", MBB); 605 } else if (!getBundleStart(&MBB->back())->isTerminator()) { 606 report("MBB exits via unconditional branch but the branch isn't a " 607 "terminator instruction!", MBB); 608 } 609 } else if (TBB && !FBB && !Cond.empty()) { 610 // Block conditionally branches somewhere, otherwise falls through. 611 MachineFunction::const_iterator MBBI = MBB; 612 ++MBBI; 613 if (MBBI == MF->end()) { 614 report("MBB conditionally falls through out of function!", MBB); 615 } else if (MBB->succ_size() == 1) { 616 // A conditional branch with only one successor is weird, but allowed. 617 if (&*MBBI != TBB) 618 report("MBB exits via conditional branch/fall-through but only has " 619 "one CFG successor!", MBB); 620 else if (TBB != *MBB->succ_begin()) 621 report("MBB exits via conditional branch/fall-through but the CFG " 622 "successor don't match the actual successor!", MBB); 623 } else if (MBB->succ_size() != 2) { 624 report("MBB exits via conditional branch/fall-through but doesn't have " 625 "exactly two CFG successors!", MBB); 626 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) { 627 report("MBB exits via conditional branch/fall-through but the CFG " 628 "successors don't match the actual successors!", MBB); 629 } 630 if (MBB->empty()) { 631 report("MBB exits via conditional branch/fall-through but doesn't " 632 "contain any instructions!", MBB); 633 } else if (getBundleStart(&MBB->back())->isBarrier()) { 634 report("MBB exits via conditional branch/fall-through but ends with a " 635 "barrier instruction!", MBB); 636 } else if (!getBundleStart(&MBB->back())->isTerminator()) { 637 report("MBB exits via conditional branch/fall-through but the branch " 638 "isn't a terminator instruction!", MBB); 639 } 640 } else if (TBB && FBB) { 641 // Block conditionally branches somewhere, otherwise branches 642 // somewhere else. 643 if (MBB->succ_size() == 1) { 644 // A conditional branch with only one successor is weird, but allowed. 645 if (FBB != TBB) 646 report("MBB exits via conditional branch/branch through but only has " 647 "one CFG successor!", MBB); 648 else if (TBB != *MBB->succ_begin()) 649 report("MBB exits via conditional branch/branch through but the CFG " 650 "successor don't match the actual successor!", MBB); 651 } else if (MBB->succ_size() != 2) { 652 report("MBB exits via conditional branch/branch but doesn't have " 653 "exactly two CFG successors!", MBB); 654 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) { 655 report("MBB exits via conditional branch/branch but the CFG " 656 "successors don't match the actual successors!", MBB); 657 } 658 if (MBB->empty()) { 659 report("MBB exits via conditional branch/branch but doesn't " 660 "contain any instructions!", MBB); 661 } else if (!getBundleStart(&MBB->back())->isBarrier()) { 662 report("MBB exits via conditional branch/branch but doesn't end with a " 663 "barrier instruction!", MBB); 664 } else if (!getBundleStart(&MBB->back())->isTerminator()) { 665 report("MBB exits via conditional branch/branch but the branch " 666 "isn't a terminator instruction!", MBB); 667 } 668 if (Cond.empty()) { 669 report("MBB exits via conditinal branch/branch but there's no " 670 "condition!", MBB); 671 } 672 } else { 673 report("AnalyzeBranch returned invalid data!", MBB); 674 } 675 } 676 677 regsLive.clear(); 678 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), 679 E = MBB->livein_end(); I != E; ++I) { 680 if (!TargetRegisterInfo::isPhysicalRegister(*I)) { 681 report("MBB live-in list contains non-physical register", MBB); 682 continue; 683 } 684 for (MCSubRegIterator SubRegs(*I, TRI, /*IncludeSelf=*/true); 685 SubRegs.isValid(); ++SubRegs) 686 regsLive.insert(*SubRegs); 687 } 688 regsLiveInButUnused = regsLive; 689 690 const MachineFrameInfo *MFI = MF->getFrameInfo(); 691 assert(MFI && "Function has no frame info"); 692 BitVector PR = MFI->getPristineRegs(MBB); 693 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) { 694 for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true); 695 SubRegs.isValid(); ++SubRegs) 696 regsLive.insert(*SubRegs); 697 } 698 699 regsKilled.clear(); 700 regsDefined.clear(); 701 702 if (Indexes) 703 lastIndex = Indexes->getMBBStartIdx(MBB); 704} 705 706// This function gets called for all bundle headers, including normal 707// stand-alone unbundled instructions. 708void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) { 709 if (Indexes && Indexes->hasIndex(MI)) { 710 SlotIndex idx = Indexes->getInstructionIndex(MI); 711 if (!(idx > lastIndex)) { 712 report("Instruction index out of order", MI); 713 *OS << "Last instruction was at " << lastIndex << '\n'; 714 } 715 lastIndex = idx; 716 } 717 718 // Ensure non-terminators don't follow terminators. 719 // Ignore predicated terminators formed by if conversion. 720 // FIXME: If conversion shouldn't need to violate this rule. 721 if (MI->isTerminator() && !TII->isPredicated(MI)) { 722 if (!FirstTerminator) 723 FirstTerminator = MI; 724 } else if (FirstTerminator) { 725 report("Non-terminator instruction after the first terminator", MI); 726 *OS << "First terminator was:\t" << *FirstTerminator; 727 } 728} 729 730// The operands on an INLINEASM instruction must follow a template. 731// Verify that the flag operands make sense. 732void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) { 733 // The first two operands on INLINEASM are the asm string and global flags. 734 if (MI->getNumOperands() < 2) { 735 report("Too few operands on inline asm", MI); 736 return; 737 } 738 if (!MI->getOperand(0).isSymbol()) 739 report("Asm string must be an external symbol", MI); 740 if (!MI->getOperand(1).isImm()) 741 report("Asm flags must be an immediate", MI); 742 // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2, 743 // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16. 744 if (!isUInt<5>(MI->getOperand(1).getImm())) 745 report("Unknown asm flags", &MI->getOperand(1), 1); 746 747 assert(InlineAsm::MIOp_FirstOperand == 2 && "Asm format changed"); 748 749 unsigned OpNo = InlineAsm::MIOp_FirstOperand; 750 unsigned NumOps; 751 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) { 752 const MachineOperand &MO = MI->getOperand(OpNo); 753 // There may be implicit ops after the fixed operands. 754 if (!MO.isImm()) 755 break; 756 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm()); 757 } 758 759 if (OpNo > MI->getNumOperands()) 760 report("Missing operands in last group", MI); 761 762 // An optional MDNode follows the groups. 763 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata()) 764 ++OpNo; 765 766 // All trailing operands must be implicit registers. 767 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) { 768 const MachineOperand &MO = MI->getOperand(OpNo); 769 if (!MO.isReg() || !MO.isImplicit()) 770 report("Expected implicit register after groups", &MO, OpNo); 771 } 772} 773 774void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { 775 const MCInstrDesc &MCID = MI->getDesc(); 776 if (MI->getNumOperands() < MCID.getNumOperands()) { 777 report("Too few operands", MI); 778 *OS << MCID.getNumOperands() << " operands expected, but " 779 << MI->getNumOperands() << " given.\n"; 780 } 781 782 // Check the tied operands. 783 if (MI->isInlineAsm()) 784 verifyInlineAsm(MI); 785 786 // Check the MachineMemOperands for basic consistency. 787 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), 788 E = MI->memoperands_end(); I != E; ++I) { 789 if ((*I)->isLoad() && !MI->mayLoad()) 790 report("Missing mayLoad flag", MI); 791 if ((*I)->isStore() && !MI->mayStore()) 792 report("Missing mayStore flag", MI); 793 } 794 795 // Debug values must not have a slot index. 796 // Other instructions must have one, unless they are inside a bundle. 797 if (LiveInts) { 798 bool mapped = !LiveInts->isNotInMIMap(MI); 799 if (MI->isDebugValue()) { 800 if (mapped) 801 report("Debug instruction has a slot index", MI); 802 } else if (MI->isInsideBundle()) { 803 if (mapped) 804 report("Instruction inside bundle has a slot index", MI); 805 } else { 806 if (!mapped) 807 report("Missing slot index", MI); 808 } 809 } 810 811 StringRef ErrorInfo; 812 if (!TII->verifyInstruction(MI, ErrorInfo)) 813 report(ErrorInfo.data(), MI); 814} 815 816void 817MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { 818 const MachineInstr *MI = MO->getParent(); 819 const MCInstrDesc &MCID = MI->getDesc(); 820 821 // The first MCID.NumDefs operands must be explicit register defines 822 if (MONum < MCID.getNumDefs()) { 823 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; 824 if (!MO->isReg()) 825 report("Explicit definition must be a register", MO, MONum); 826 else if (!MO->isDef() && !MCOI.isOptionalDef()) 827 report("Explicit definition marked as use", MO, MONum); 828 else if (MO->isImplicit()) 829 report("Explicit definition marked as implicit", MO, MONum); 830 } else if (MONum < MCID.getNumOperands()) { 831 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; 832 // Don't check if it's the last operand in a variadic instruction. See, 833 // e.g., LDM_RET in the arm back end. 834 if (MO->isReg() && 835 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) { 836 if (MO->isDef() && !MCOI.isOptionalDef()) 837 report("Explicit operand marked as def", MO, MONum); 838 if (MO->isImplicit()) 839 report("Explicit operand marked as implicit", MO, MONum); 840 } 841 842 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO); 843 if (TiedTo != -1) { 844 if (!MO->isReg()) 845 report("Tied use must be a register", MO, MONum); 846 else if (!MO->isTied()) 847 report("Operand should be tied", MO, MONum); 848 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum)) 849 report("Tied def doesn't match MCInstrDesc", MO, MONum); 850 } else if (MO->isReg() && MO->isTied()) 851 report("Explicit operand should not be tied", MO, MONum); 852 } else { 853 // ARM adds %reg0 operands to indicate predicates. We'll allow that. 854 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg()) 855 report("Extra explicit operand on non-variadic instruction", MO, MONum); 856 } 857 858 switch (MO->getType()) { 859 case MachineOperand::MO_Register: { 860 const unsigned Reg = MO->getReg(); 861 if (!Reg) 862 return; 863 if (MRI->tracksLiveness() && !MI->isDebugValue()) 864 checkLiveness(MO, MONum); 865 866 // Verify the consistency of tied operands. 867 if (MO->isTied()) { 868 unsigned OtherIdx = MI->findTiedOperandIdx(MONum); 869 const MachineOperand &OtherMO = MI->getOperand(OtherIdx); 870 if (!OtherMO.isReg()) 871 report("Must be tied to a register", MO, MONum); 872 if (!OtherMO.isTied()) 873 report("Missing tie flags on tied operand", MO, MONum); 874 if (MI->findTiedOperandIdx(OtherIdx) != MONum) 875 report("Inconsistent tie links", MO, MONum); 876 if (MONum < MCID.getNumDefs()) { 877 if (OtherIdx < MCID.getNumOperands()) { 878 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO)) 879 report("Explicit def tied to explicit use without tie constraint", 880 MO, MONum); 881 } else { 882 if (!OtherMO.isImplicit()) 883 report("Explicit def should be tied to implicit use", MO, MONum); 884 } 885 } 886 } 887 888 // Verify two-address constraints after leaving SSA form. 889 unsigned DefIdx; 890 if (!MRI->isSSA() && MO->isUse() && 891 MI->isRegTiedToDefOperand(MONum, &DefIdx) && 892 Reg != MI->getOperand(DefIdx).getReg()) 893 report("Two-address instruction operands must be identical", MO, MONum); 894 895 // Check register classes. 896 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) { 897 unsigned SubIdx = MO->getSubReg(); 898 899 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 900 if (SubIdx) { 901 report("Illegal subregister index for physical register", MO, MONum); 902 return; 903 } 904 if (const TargetRegisterClass *DRC = 905 TII->getRegClass(MCID, MONum, TRI, *MF)) { 906 if (!DRC->contains(Reg)) { 907 report("Illegal physical register for instruction", MO, MONum); 908 *OS << TRI->getName(Reg) << " is not a " 909 << DRC->getName() << " register.\n"; 910 } 911 } 912 } else { 913 // Virtual register. 914 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 915 if (SubIdx) { 916 const TargetRegisterClass *SRC = 917 TRI->getSubClassWithSubReg(RC, SubIdx); 918 if (!SRC) { 919 report("Invalid subregister index for virtual register", MO, MONum); 920 *OS << "Register class " << RC->getName() 921 << " does not support subreg index " << SubIdx << "\n"; 922 return; 923 } 924 if (RC != SRC) { 925 report("Invalid register class for subregister index", MO, MONum); 926 *OS << "Register class " << RC->getName() 927 << " does not fully support subreg index " << SubIdx << "\n"; 928 return; 929 } 930 } 931 if (const TargetRegisterClass *DRC = 932 TII->getRegClass(MCID, MONum, TRI, *MF)) { 933 if (SubIdx) { 934 const TargetRegisterClass *SuperRC = 935 TRI->getLargestLegalSuperClass(RC); 936 if (!SuperRC) { 937 report("No largest legal super class exists.", MO, MONum); 938 return; 939 } 940 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); 941 if (!DRC) { 942 report("No matching super-reg register class.", MO, MONum); 943 return; 944 } 945 } 946 if (!RC->hasSuperClassEq(DRC)) { 947 report("Illegal virtual register for instruction", MO, MONum); 948 *OS << "Expected a " << DRC->getName() << " register, but got a " 949 << RC->getName() << " register\n"; 950 } 951 } 952 } 953 } 954 break; 955 } 956 957 case MachineOperand::MO_RegisterMask: 958 regMasks.push_back(MO->getRegMask()); 959 break; 960 961 case MachineOperand::MO_MachineBasicBlock: 962 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent())) 963 report("PHI operand is not in the CFG", MO, MONum); 964 break; 965 966 case MachineOperand::MO_FrameIndex: 967 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) && 968 LiveInts && !LiveInts->isNotInMIMap(MI)) { 969 LiveInterval &LI = LiveStks->getInterval(MO->getIndex()); 970 SlotIndex Idx = LiveInts->getInstructionIndex(MI); 971 if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) { 972 report("Instruction loads from dead spill slot", MO, MONum); 973 *OS << "Live stack: " << LI << '\n'; 974 } 975 if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) { 976 report("Instruction stores to dead spill slot", MO, MONum); 977 *OS << "Live stack: " << LI << '\n'; 978 } 979 } 980 break; 981 982 default: 983 break; 984 } 985} 986 987void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) { 988 const MachineInstr *MI = MO->getParent(); 989 const unsigned Reg = MO->getReg(); 990 991 // Both use and def operands can read a register. 992 if (MO->readsReg()) { 993 regsLiveInButUnused.erase(Reg); 994 995 if (MO->isKill()) 996 addRegWithSubRegs(regsKilled, Reg); 997 998 // Check that LiveVars knows this kill. 999 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) && 1000 MO->isKill()) { 1001 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); 1002 if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end()) 1003 report("Kill missing from LiveVariables", MO, MONum); 1004 } 1005 1006 // Check LiveInts liveness and kill. 1007 if (LiveInts && !LiveInts->isNotInMIMap(MI)) { 1008 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI); 1009 // Check the cached regunit intervals. 1010 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) { 1011 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) { 1012 if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units)) { 1013 LiveQueryResult LRQ = LR->Query(UseIdx); 1014 if (!LRQ.valueIn()) { 1015 report("No live segment at use", MO, MONum); 1016 *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI) 1017 << ' ' << *LR << '\n'; 1018 } 1019 if (MO->isKill() && !LRQ.isKill()) { 1020 report("Live range continues after kill flag", MO, MONum); 1021 *OS << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n'; 1022 } 1023 } 1024 } 1025 } 1026 1027 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 1028 if (LiveInts->hasInterval(Reg)) { 1029 // This is a virtual register interval. 1030 const LiveInterval &LI = LiveInts->getInterval(Reg); 1031 LiveQueryResult LRQ = LI.Query(UseIdx); 1032 if (!LRQ.valueIn()) { 1033 report("No live segment at use", MO, MONum); 1034 *OS << UseIdx << " is not live in " << LI << '\n'; 1035 } 1036 // Check for extra kill flags. 1037 // Note that we allow missing kill flags for now. 1038 if (MO->isKill() && !LRQ.isKill()) { 1039 report("Live range continues after kill flag", MO, MONum); 1040 *OS << "Live range: " << LI << '\n'; 1041 } 1042 } else { 1043 report("Virtual register has no live interval", MO, MONum); 1044 } 1045 } 1046 } 1047 1048 // Use of a dead register. 1049 if (!regsLive.count(Reg)) { 1050 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 1051 // Reserved registers may be used even when 'dead'. 1052 if (!isReserved(Reg)) 1053 report("Using an undefined physical register", MO, MONum); 1054 } else if (MRI->def_empty(Reg)) { 1055 report("Reading virtual register without a def", MO, MONum); 1056 } else { 1057 BBInfo &MInfo = MBBInfoMap[MI->getParent()]; 1058 // We don't know which virtual registers are live in, so only complain 1059 // if vreg was killed in this MBB. Otherwise keep track of vregs that 1060 // must be live in. PHI instructions are handled separately. 1061 if (MInfo.regsKilled.count(Reg)) 1062 report("Using a killed virtual register", MO, MONum); 1063 else if (!MI->isPHI()) 1064 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI)); 1065 } 1066 } 1067 } 1068 1069 if (MO->isDef()) { 1070 // Register defined. 1071 // TODO: verify that earlyclobber ops are not used. 1072 if (MO->isDead()) 1073 addRegWithSubRegs(regsDead, Reg); 1074 else 1075 addRegWithSubRegs(regsDefined, Reg); 1076 1077 // Verify SSA form. 1078 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) && 1079 std::next(MRI->def_begin(Reg)) != MRI->def_end()) 1080 report("Multiple virtual register defs in SSA form", MO, MONum); 1081 1082 // Check LiveInts for a live segment, but only for virtual registers. 1083 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) && 1084 !LiveInts->isNotInMIMap(MI)) { 1085 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI); 1086 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber()); 1087 if (LiveInts->hasInterval(Reg)) { 1088 const LiveInterval &LI = LiveInts->getInterval(Reg); 1089 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) { 1090 assert(VNI && "NULL valno is not allowed"); 1091 if (VNI->def != DefIdx) { 1092 report("Inconsistent valno->def", MO, MONum); 1093 *OS << "Valno " << VNI->id << " is not defined at " 1094 << DefIdx << " in " << LI << '\n'; 1095 } 1096 } else { 1097 report("No live segment at def", MO, MONum); 1098 *OS << DefIdx << " is not live in " << LI << '\n'; 1099 } 1100 // Check that, if the dead def flag is present, LiveInts agree. 1101 if (MO->isDead()) { 1102 LiveQueryResult LRQ = LI.Query(DefIdx); 1103 if (!LRQ.isDeadDef()) { 1104 report("Live range continues after dead def flag", MO, MONum); 1105 *OS << "Live range: " << LI << '\n'; 1106 } 1107 } 1108 } else { 1109 report("Virtual register has no Live interval", MO, MONum); 1110 } 1111 } 1112 } 1113} 1114 1115void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) { 1116} 1117 1118// This function gets called after visiting all instructions in a bundle. The 1119// argument points to the bundle header. 1120// Normal stand-alone instructions are also considered 'bundles', and this 1121// function is called for all of them. 1122void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) { 1123 BBInfo &MInfo = MBBInfoMap[MI->getParent()]; 1124 set_union(MInfo.regsKilled, regsKilled); 1125 set_subtract(regsLive, regsKilled); regsKilled.clear(); 1126 // Kill any masked registers. 1127 while (!regMasks.empty()) { 1128 const uint32_t *Mask = regMasks.pop_back_val(); 1129 for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I) 1130 if (TargetRegisterInfo::isPhysicalRegister(*I) && 1131 MachineOperand::clobbersPhysReg(Mask, *I)) 1132 regsDead.push_back(*I); 1133 } 1134 set_subtract(regsLive, regsDead); regsDead.clear(); 1135 set_union(regsLive, regsDefined); regsDefined.clear(); 1136} 1137 1138void 1139MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) { 1140 MBBInfoMap[MBB].regsLiveOut = regsLive; 1141 regsLive.clear(); 1142 1143 if (Indexes) { 1144 SlotIndex stop = Indexes->getMBBEndIdx(MBB); 1145 if (!(stop > lastIndex)) { 1146 report("Block ends before last instruction index", MBB); 1147 *OS << "Block ends at " << stop 1148 << " last instruction was at " << lastIndex << '\n'; 1149 } 1150 lastIndex = stop; 1151 } 1152} 1153 1154// Calculate the largest possible vregsPassed sets. These are the registers that 1155// can pass through an MBB live, but may not be live every time. It is assumed 1156// that all vregsPassed sets are empty before the call. 1157void MachineVerifier::calcRegsPassed() { 1158 // First push live-out regs to successors' vregsPassed. Remember the MBBs that 1159 // have any vregsPassed. 1160 SmallPtrSet<const MachineBasicBlock*, 8> todo; 1161 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 1162 MFI != MFE; ++MFI) { 1163 const MachineBasicBlock &MBB(*MFI); 1164 BBInfo &MInfo = MBBInfoMap[&MBB]; 1165 if (!MInfo.reachable) 1166 continue; 1167 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(), 1168 SuE = MBB.succ_end(); SuI != SuE; ++SuI) { 1169 BBInfo &SInfo = MBBInfoMap[*SuI]; 1170 if (SInfo.addPassed(MInfo.regsLiveOut)) 1171 todo.insert(*SuI); 1172 } 1173 } 1174 1175 // Iteratively push vregsPassed to successors. This will converge to the same 1176 // final state regardless of DenseSet iteration order. 1177 while (!todo.empty()) { 1178 const MachineBasicBlock *MBB = *todo.begin(); 1179 todo.erase(MBB); 1180 BBInfo &MInfo = MBBInfoMap[MBB]; 1181 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(), 1182 SuE = MBB->succ_end(); SuI != SuE; ++SuI) { 1183 if (*SuI == MBB) 1184 continue; 1185 BBInfo &SInfo = MBBInfoMap[*SuI]; 1186 if (SInfo.addPassed(MInfo.vregsPassed)) 1187 todo.insert(*SuI); 1188 } 1189 } 1190} 1191 1192// Calculate the set of virtual registers that must be passed through each basic 1193// block in order to satisfy the requirements of successor blocks. This is very 1194// similar to calcRegsPassed, only backwards. 1195void MachineVerifier::calcRegsRequired() { 1196 // First push live-in regs to predecessors' vregsRequired. 1197 SmallPtrSet<const MachineBasicBlock*, 8> todo; 1198 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 1199 MFI != MFE; ++MFI) { 1200 const MachineBasicBlock &MBB(*MFI); 1201 BBInfo &MInfo = MBBInfoMap[&MBB]; 1202 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(), 1203 PrE = MBB.pred_end(); PrI != PrE; ++PrI) { 1204 BBInfo &PInfo = MBBInfoMap[*PrI]; 1205 if (PInfo.addRequired(MInfo.vregsLiveIn)) 1206 todo.insert(*PrI); 1207 } 1208 } 1209 1210 // Iteratively push vregsRequired to predecessors. This will converge to the 1211 // same final state regardless of DenseSet iteration order. 1212 while (!todo.empty()) { 1213 const MachineBasicBlock *MBB = *todo.begin(); 1214 todo.erase(MBB); 1215 BBInfo &MInfo = MBBInfoMap[MBB]; 1216 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), 1217 PrE = MBB->pred_end(); PrI != PrE; ++PrI) { 1218 if (*PrI == MBB) 1219 continue; 1220 BBInfo &SInfo = MBBInfoMap[*PrI]; 1221 if (SInfo.addRequired(MInfo.vregsRequired)) 1222 todo.insert(*PrI); 1223 } 1224 } 1225} 1226 1227// Check PHI instructions at the beginning of MBB. It is assumed that 1228// calcRegsPassed has been run so BBInfo::isLiveOut is valid. 1229void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) { 1230 SmallPtrSet<const MachineBasicBlock*, 8> seen; 1231 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end(); 1232 BBI != BBE && BBI->isPHI(); ++BBI) { 1233 seen.clear(); 1234 1235 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) { 1236 unsigned Reg = BBI->getOperand(i).getReg(); 1237 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB(); 1238 if (!Pre->isSuccessor(MBB)) 1239 continue; 1240 seen.insert(Pre); 1241 BBInfo &PrInfo = MBBInfoMap[Pre]; 1242 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg)) 1243 report("PHI operand is not live-out from predecessor", 1244 &BBI->getOperand(i), i); 1245 } 1246 1247 // Did we see all predecessors? 1248 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(), 1249 PrE = MBB->pred_end(); PrI != PrE; ++PrI) { 1250 if (!seen.count(*PrI)) { 1251 report("Missing PHI operand", BBI); 1252 *OS << "BB#" << (*PrI)->getNumber() 1253 << " is a predecessor according to the CFG.\n"; 1254 } 1255 } 1256 } 1257} 1258 1259void MachineVerifier::visitMachineFunctionAfter() { 1260 calcRegsPassed(); 1261 1262 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 1263 MFI != MFE; ++MFI) { 1264 BBInfo &MInfo = MBBInfoMap[MFI]; 1265 1266 // Skip unreachable MBBs. 1267 if (!MInfo.reachable) 1268 continue; 1269 1270 checkPHIOps(MFI); 1271 } 1272 1273 // Now check liveness info if available 1274 calcRegsRequired(); 1275 1276 // Check for killed virtual registers that should be live out. 1277 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 1278 MFI != MFE; ++MFI) { 1279 BBInfo &MInfo = MBBInfoMap[MFI]; 1280 for (RegSet::iterator 1281 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E; 1282 ++I) 1283 if (MInfo.regsKilled.count(*I)) { 1284 report("Virtual register killed in block, but needed live out.", MFI); 1285 *OS << "Virtual register " << PrintReg(*I) 1286 << " is used after the block.\n"; 1287 } 1288 } 1289 1290 if (!MF->empty()) { 1291 BBInfo &MInfo = MBBInfoMap[&MF->front()]; 1292 for (RegSet::iterator 1293 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E; 1294 ++I) 1295 report("Virtual register def doesn't dominate all uses.", 1296 MRI->getVRegDef(*I)); 1297 } 1298 1299 if (LiveVars) 1300 verifyLiveVariables(); 1301 if (LiveInts) 1302 verifyLiveIntervals(); 1303} 1304 1305void MachineVerifier::verifyLiveVariables() { 1306 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars"); 1307 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 1308 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 1309 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg); 1310 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end(); 1311 MFI != MFE; ++MFI) { 1312 BBInfo &MInfo = MBBInfoMap[MFI]; 1313 1314 // Our vregsRequired should be identical to LiveVariables' AliveBlocks 1315 if (MInfo.vregsRequired.count(Reg)) { 1316 if (!VI.AliveBlocks.test(MFI->getNumber())) { 1317 report("LiveVariables: Block missing from AliveBlocks", MFI); 1318 *OS << "Virtual register " << PrintReg(Reg) 1319 << " must be live through the block.\n"; 1320 } 1321 } else { 1322 if (VI.AliveBlocks.test(MFI->getNumber())) { 1323 report("LiveVariables: Block should not be in AliveBlocks", MFI); 1324 *OS << "Virtual register " << PrintReg(Reg) 1325 << " is not needed live through the block.\n"; 1326 } 1327 } 1328 } 1329 } 1330} 1331 1332void MachineVerifier::verifyLiveIntervals() { 1333 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts"); 1334 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 1335 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 1336 1337 // Spilling and splitting may leave unused registers around. Skip them. 1338 if (MRI->reg_nodbg_empty(Reg)) 1339 continue; 1340 1341 if (!LiveInts->hasInterval(Reg)) { 1342 report("Missing live interval for virtual register", MF); 1343 *OS << PrintReg(Reg, TRI) << " still has defs or uses\n"; 1344 continue; 1345 } 1346 1347 const LiveInterval &LI = LiveInts->getInterval(Reg); 1348 assert(Reg == LI.reg && "Invalid reg to interval mapping"); 1349 verifyLiveInterval(LI); 1350 } 1351 1352 // Verify all the cached regunit intervals. 1353 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i) 1354 if (const LiveRange *LR = LiveInts->getCachedRegUnit(i)) 1355 verifyLiveRange(*LR, i); 1356} 1357 1358void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR, 1359 const VNInfo *VNI, 1360 unsigned Reg) { 1361 if (VNI->isUnused()) 1362 return; 1363 1364 const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def); 1365 1366 if (!DefVNI) { 1367 report("Valno not live at def and not marked unused", MF, LR); 1368 *OS << "Valno #" << VNI->id << '\n'; 1369 return; 1370 } 1371 1372 if (DefVNI != VNI) { 1373 report("Live segment at def has different valno", MF, LR); 1374 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def 1375 << " where valno #" << DefVNI->id << " is live\n"; 1376 return; 1377 } 1378 1379 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def); 1380 if (!MBB) { 1381 report("Invalid definition index", MF, LR); 1382 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def 1383 << " in " << LR << '\n'; 1384 return; 1385 } 1386 1387 if (VNI->isPHIDef()) { 1388 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) { 1389 report("PHIDef value is not defined at MBB start", MBB, LR); 1390 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def 1391 << ", not at the beginning of BB#" << MBB->getNumber() << '\n'; 1392 } 1393 return; 1394 } 1395 1396 // Non-PHI def. 1397 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def); 1398 if (!MI) { 1399 report("No instruction at def index", MBB, LR); 1400 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n'; 1401 return; 1402 } 1403 1404 if (Reg != 0) { 1405 bool hasDef = false; 1406 bool isEarlyClobber = false; 1407 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) { 1408 if (!MOI->isReg() || !MOI->isDef()) 1409 continue; 1410 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 1411 if (MOI->getReg() != Reg) 1412 continue; 1413 } else { 1414 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) || 1415 !TRI->hasRegUnit(MOI->getReg(), Reg)) 1416 continue; 1417 } 1418 hasDef = true; 1419 if (MOI->isEarlyClobber()) 1420 isEarlyClobber = true; 1421 } 1422 1423 if (!hasDef) { 1424 report("Defining instruction does not modify register", MI); 1425 *OS << "Valno #" << VNI->id << " in " << LR << '\n'; 1426 } 1427 1428 // Early clobber defs begin at USE slots, but other defs must begin at 1429 // DEF slots. 1430 if (isEarlyClobber) { 1431 if (!VNI->def.isEarlyClobber()) { 1432 report("Early clobber def must be at an early-clobber slot", MBB, LR); 1433 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n'; 1434 } 1435 } else if (!VNI->def.isRegister()) { 1436 report("Non-PHI, non-early clobber def must be at a register slot", 1437 MBB, LR); 1438 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n'; 1439 } 1440 } 1441} 1442 1443void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR, 1444 const LiveRange::const_iterator I, 1445 unsigned Reg) { 1446 const LiveRange::Segment &S = *I; 1447 const VNInfo *VNI = S.valno; 1448 assert(VNI && "Live segment has no valno"); 1449 1450 if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) { 1451 report("Foreign valno in live segment", MF, LR); 1452 *OS << S << " has a bad valno\n"; 1453 } 1454 1455 if (VNI->isUnused()) { 1456 report("Live segment valno is marked unused", MF, LR); 1457 *OS << S << '\n'; 1458 } 1459 1460 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start); 1461 if (!MBB) { 1462 report("Bad start of live segment, no basic block", MF, LR); 1463 *OS << S << '\n'; 1464 return; 1465 } 1466 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB); 1467 if (S.start != MBBStartIdx && S.start != VNI->def) { 1468 report("Live segment must begin at MBB entry or valno def", MBB, LR); 1469 *OS << S << '\n'; 1470 } 1471 1472 const MachineBasicBlock *EndMBB = 1473 LiveInts->getMBBFromIndex(S.end.getPrevSlot()); 1474 if (!EndMBB) { 1475 report("Bad end of live segment, no basic block", MF, LR); 1476 *OS << S << '\n'; 1477 return; 1478 } 1479 1480 // No more checks for live-out segments. 1481 if (S.end == LiveInts->getMBBEndIdx(EndMBB)) 1482 return; 1483 1484 // RegUnit intervals are allowed dead phis. 1485 if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() && 1486 S.start == VNI->def && S.end == VNI->def.getDeadSlot()) 1487 return; 1488 1489 // The live segment is ending inside EndMBB 1490 const MachineInstr *MI = 1491 LiveInts->getInstructionFromIndex(S.end.getPrevSlot()); 1492 if (!MI) { 1493 report("Live segment doesn't end at a valid instruction", EndMBB, LR); 1494 *OS << S << '\n'; 1495 return; 1496 } 1497 1498 // The block slot must refer to a basic block boundary. 1499 if (S.end.isBlock()) { 1500 report("Live segment ends at B slot of an instruction", EndMBB, LR); 1501 *OS << S << '\n'; 1502 } 1503 1504 if (S.end.isDead()) { 1505 // Segment ends on the dead slot. 1506 // That means there must be a dead def. 1507 if (!SlotIndex::isSameInstr(S.start, S.end)) { 1508 report("Live segment ending at dead slot spans instructions", EndMBB, LR); 1509 *OS << S << '\n'; 1510 } 1511 } 1512 1513 // A live segment can only end at an early-clobber slot if it is being 1514 // redefined by an early-clobber def. 1515 if (S.end.isEarlyClobber()) { 1516 if (I+1 == LR.end() || (I+1)->start != S.end) { 1517 report("Live segment ending at early clobber slot must be " 1518 "redefined by an EC def in the same instruction", EndMBB, LR); 1519 *OS << S << '\n'; 1520 } 1521 } 1522 1523 // The following checks only apply to virtual registers. Physreg liveness 1524 // is too weird to check. 1525 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 1526 // A live segment can end with either a redefinition, a kill flag on a 1527 // use, or a dead flag on a def. 1528 bool hasRead = false; 1529 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) { 1530 if (!MOI->isReg() || MOI->getReg() != Reg) 1531 continue; 1532 if (MOI->readsReg()) 1533 hasRead = true; 1534 } 1535 if (!S.end.isDead()) { 1536 if (!hasRead) { 1537 report("Instruction ending live segment doesn't read the register", MI); 1538 *OS << S << " in " << LR << '\n'; 1539 } 1540 } 1541 } 1542 1543 // Now check all the basic blocks in this live segment. 1544 MachineFunction::const_iterator MFI = MBB; 1545 // Is this live segment the beginning of a non-PHIDef VN? 1546 if (S.start == VNI->def && !VNI->isPHIDef()) { 1547 // Not live-in to any blocks. 1548 if (MBB == EndMBB) 1549 return; 1550 // Skip this block. 1551 ++MFI; 1552 } 1553 for (;;) { 1554 assert(LiveInts->isLiveInToMBB(LR, MFI)); 1555 // We don't know how to track physregs into a landing pad. 1556 if (!TargetRegisterInfo::isVirtualRegister(Reg) && 1557 MFI->isLandingPad()) { 1558 if (&*MFI == EndMBB) 1559 break; 1560 ++MFI; 1561 continue; 1562 } 1563 1564 // Is VNI a PHI-def in the current block? 1565 bool IsPHI = VNI->isPHIDef() && 1566 VNI->def == LiveInts->getMBBStartIdx(MFI); 1567 1568 // Check that VNI is live-out of all predecessors. 1569 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(), 1570 PE = MFI->pred_end(); PI != PE; ++PI) { 1571 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI); 1572 const VNInfo *PVNI = LR.getVNInfoBefore(PEnd); 1573 1574 // All predecessors must have a live-out value. 1575 if (!PVNI) { 1576 report("Register not marked live out of predecessor", *PI, LR); 1577 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber() 1578 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before " 1579 << PEnd << '\n'; 1580 continue; 1581 } 1582 1583 // Only PHI-defs can take different predecessor values. 1584 if (!IsPHI && PVNI != VNI) { 1585 report("Different value live out of predecessor", *PI, LR); 1586 *OS << "Valno #" << PVNI->id << " live out of BB#" 1587 << (*PI)->getNumber() << '@' << PEnd 1588 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber() 1589 << '@' << LiveInts->getMBBStartIdx(MFI) << '\n'; 1590 } 1591 } 1592 if (&*MFI == EndMBB) 1593 break; 1594 ++MFI; 1595 } 1596} 1597 1598void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg) { 1599 for (LiveRange::const_vni_iterator I = LR.vni_begin(), E = LR.vni_end(); 1600 I != E; ++I) 1601 verifyLiveRangeValue(LR, *I, Reg); 1602 1603 for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I) 1604 verifyLiveRangeSegment(LR, I, Reg); 1605} 1606 1607void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) { 1608 verifyLiveRange(LI, LI.reg); 1609 1610 // Check the LI only has one connected component. 1611 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { 1612 ConnectedVNInfoEqClasses ConEQ(*LiveInts); 1613 unsigned NumComp = ConEQ.Classify(&LI); 1614 if (NumComp > 1) { 1615 report("Multiple connected components in live interval", MF, LI); 1616 for (unsigned comp = 0; comp != NumComp; ++comp) { 1617 *OS << comp << ": valnos"; 1618 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), 1619 E = LI.vni_end(); I!=E; ++I) 1620 if (comp == ConEQ.getEqClass(*I)) 1621 *OS << ' ' << (*I)->id; 1622 *OS << '\n'; 1623 } 1624 } 1625 } 1626} 1627 1628namespace { 1629 // FrameSetup and FrameDestroy can have zero adjustment, so using a single 1630 // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the 1631 // value is zero. 1632 // We use a bool plus an integer to capture the stack state. 1633 struct StackStateOfBB { 1634 StackStateOfBB() : EntryValue(0), ExitValue(0), EntryIsSetup(false), 1635 ExitIsSetup(false) { } 1636 StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) : 1637 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup), 1638 ExitIsSetup(ExitSetup) { } 1639 // Can be negative, which means we are setting up a frame. 1640 int EntryValue; 1641 int ExitValue; 1642 bool EntryIsSetup; 1643 bool ExitIsSetup; 1644 }; 1645} 1646 1647/// Make sure on every path through the CFG, a FrameSetup <n> is always followed 1648/// by a FrameDestroy <n>, stack adjustments are identical on all 1649/// CFG edges to a merge point, and frame is destroyed at end of a return block. 1650void MachineVerifier::verifyStackFrame() { 1651 int FrameSetupOpcode = TII->getCallFrameSetupOpcode(); 1652 int FrameDestroyOpcode = TII->getCallFrameDestroyOpcode(); 1653 1654 SmallVector<StackStateOfBB, 8> SPState; 1655 SPState.resize(MF->getNumBlockIDs()); 1656 SmallPtrSet<const MachineBasicBlock*, 8> Reachable; 1657 1658 // Visit the MBBs in DFS order. 1659 for (df_ext_iterator<const MachineFunction*, 1660 SmallPtrSet<const MachineBasicBlock*, 8> > 1661 DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable); 1662 DFI != DFE; ++DFI) { 1663 const MachineBasicBlock *MBB = *DFI; 1664 1665 StackStateOfBB BBState; 1666 // Check the exit state of the DFS stack predecessor. 1667 if (DFI.getPathLength() >= 2) { 1668 const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2); 1669 assert(Reachable.count(StackPred) && 1670 "DFS stack predecessor is already visited.\n"); 1671 BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue; 1672 BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup; 1673 BBState.ExitValue = BBState.EntryValue; 1674 BBState.ExitIsSetup = BBState.EntryIsSetup; 1675 } 1676 1677 // Update stack state by checking contents of MBB. 1678 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); 1679 I != E; ++I) { 1680 if (I->getOpcode() == FrameSetupOpcode) { 1681 // The first operand of a FrameOpcode should be i32. 1682 int Size = I->getOperand(0).getImm(); 1683 assert(Size >= 0 && 1684 "Value should be non-negative in FrameSetup and FrameDestroy.\n"); 1685 1686 if (BBState.ExitIsSetup) 1687 report("FrameSetup is after another FrameSetup", I); 1688 BBState.ExitValue -= Size; 1689 BBState.ExitIsSetup = true; 1690 } 1691 1692 if (I->getOpcode() == FrameDestroyOpcode) { 1693 // The first operand of a FrameOpcode should be i32. 1694 int Size = I->getOperand(0).getImm(); 1695 assert(Size >= 0 && 1696 "Value should be non-negative in FrameSetup and FrameDestroy.\n"); 1697 1698 if (!BBState.ExitIsSetup) 1699 report("FrameDestroy is not after a FrameSetup", I); 1700 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue : 1701 BBState.ExitValue; 1702 if (BBState.ExitIsSetup && AbsSPAdj != Size) { 1703 report("FrameDestroy <n> is after FrameSetup <m>", I); 1704 *OS << "FrameDestroy <" << Size << "> is after FrameSetup <" 1705 << AbsSPAdj << ">.\n"; 1706 } 1707 BBState.ExitValue += Size; 1708 BBState.ExitIsSetup = false; 1709 } 1710 } 1711 SPState[MBB->getNumber()] = BBState; 1712 1713 // Make sure the exit state of any predecessor is consistent with the entry 1714 // state. 1715 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(), 1716 E = MBB->pred_end(); I != E; ++I) { 1717 if (Reachable.count(*I) && 1718 (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue || 1719 SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) { 1720 report("The exit stack state of a predecessor is inconsistent.", MBB); 1721 *OS << "Predecessor BB#" << (*I)->getNumber() << " has exit state (" 1722 << SPState[(*I)->getNumber()].ExitValue << ", " 1723 << SPState[(*I)->getNumber()].ExitIsSetup 1724 << "), while BB#" << MBB->getNumber() << " has entry state (" 1725 << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n"; 1726 } 1727 } 1728 1729 // Make sure the entry state of any successor is consistent with the exit 1730 // state. 1731 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(), 1732 E = MBB->succ_end(); I != E; ++I) { 1733 if (Reachable.count(*I) && 1734 (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue || 1735 SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) { 1736 report("The entry stack state of a successor is inconsistent.", MBB); 1737 *OS << "Successor BB#" << (*I)->getNumber() << " has entry state (" 1738 << SPState[(*I)->getNumber()].EntryValue << ", " 1739 << SPState[(*I)->getNumber()].EntryIsSetup 1740 << "), while BB#" << MBB->getNumber() << " has exit state (" 1741 << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n"; 1742 } 1743 } 1744 1745 // Make sure a basic block with return ends with zero stack adjustment. 1746 if (!MBB->empty() && MBB->back().isReturn()) { 1747 if (BBState.ExitIsSetup) 1748 report("A return block ends with a FrameSetup.", MBB); 1749 if (BBState.ExitValue) 1750 report("A return block ends with a nonzero stack adjustment.", MBB); 1751 } 1752 } 1753} 1754