Passes.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===-- Passes.cpp - Target independent code generation passes ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines interfaces to access the target independent code 11// generation passes provided by the LLVM backend. 12// 13//===---------------------------------------------------------------------===// 14 15#include "llvm/CodeGen/Passes.h" 16#include "llvm/Analysis/Passes.h" 17#include "llvm/CodeGen/GCStrategy.h" 18#include "llvm/CodeGen/MachineFunctionPass.h" 19#include "llvm/CodeGen/RegAllocRegistry.h" 20#include "llvm/IR/IRPrintingPasses.h" 21#include "llvm/IR/Verifier.h" 22#include "llvm/MC/MCAsmInfo.h" 23#include "llvm/PassManager.h" 24#include "llvm/Support/CommandLine.h" 25#include "llvm/Support/Debug.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Target/TargetSubtargetInfo.h" 29#include "llvm/Transforms/Scalar.h" 30 31using namespace llvm; 32 33namespace llvm { 34extern cl::opt<bool> EnableStackMapLiveness; 35extern cl::opt<bool> EnablePatchPointLiveness; 36} 37 38static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden, 39 cl::desc("Disable Post Regalloc")); 40static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden, 41 cl::desc("Disable branch folding")); 42static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, 43 cl::desc("Disable tail duplication")); 44static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden, 45 cl::desc("Disable pre-register allocation tail duplication")); 46static cl::opt<bool> DisableBlockPlacement("disable-block-placement", 47 cl::Hidden, cl::desc("Disable probability-driven block placement")); 48static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats", 49 cl::Hidden, cl::desc("Collect probability-driven block placement stats")); 50static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden, 51 cl::desc("Disable Stack Slot Coloring")); 52static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden, 53 cl::desc("Disable Machine Dead Code Elimination")); 54static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, 55 cl::desc("Disable Early If-conversion")); 56static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden, 57 cl::desc("Disable Machine LICM")); 58static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden, 59 cl::desc("Disable Machine Common Subexpression Elimination")); 60static cl::opt<cl::boolOrDefault> 61OptimizeRegAlloc("optimize-regalloc", cl::Hidden, 62 cl::desc("Enable optimized register allocation compilation path.")); 63static cl::opt<cl::boolOrDefault> 64EnableMachineSched("enable-misched", 65 cl::desc("Enable the machine instruction scheduling pass.")); 66static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm", 67 cl::Hidden, 68 cl::desc("Disable Machine LICM")); 69static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden, 70 cl::desc("Disable Machine Sinking")); 71static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden, 72 cl::desc("Disable Loop Strength Reduction Pass")); 73static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting", 74 cl::Hidden, cl::desc("Disable ConstantHoisting")); 75static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden, 76 cl::desc("Disable Codegen Prepare")); 77static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden, 78 cl::desc("Disable Copy Propagation pass")); 79static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden, 80 cl::desc("Print LLVM IR produced by the loop-reduce pass")); 81static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden, 82 cl::desc("Print LLVM IR input to isel pass")); 83static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden, 84 cl::desc("Dump garbage collector data")); 85static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden, 86 cl::desc("Verify generated machine code"), 87 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=nullptr)); 88static cl::opt<std::string> 89PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, 90 cl::desc("Print machine instrs"), 91 cl::value_desc("pass-name"), cl::init("option-unspecified")); 92 93// Temporary option to allow experimenting with MachineScheduler as a post-RA 94// scheduler. Targets can "properly" enable this with 95// substitutePass(&PostRASchedulerID, &MachineSchedulerID); Ideally it wouldn't 96// be part of the standard pass pipeline, and the target would just add a PostRA 97// scheduling pass wherever it wants. 98static cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden, 99 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)")); 100 101// Experimental option to run live interval analysis early. 102static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden, 103 cl::desc("Run live interval analysis earlier in the pipeline")); 104 105/// Allow standard passes to be disabled by command line options. This supports 106/// simple binary flags that either suppress the pass or do nothing. 107/// i.e. -disable-mypass=false has no effect. 108/// These should be converted to boolOrDefault in order to use applyOverride. 109static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, 110 bool Override) { 111 if (Override) 112 return IdentifyingPassPtr(); 113 return PassID; 114} 115 116/// Allow Pass selection to be overriden by command line options. This supports 117/// flags with ternary conditions. TargetID is passed through by default. The 118/// pass is suppressed when the option is false. When the option is true, the 119/// StandardID is selected if the target provides no default. 120static IdentifyingPassPtr applyOverride(IdentifyingPassPtr TargetID, 121 cl::boolOrDefault Override, 122 AnalysisID StandardID) { 123 switch (Override) { 124 case cl::BOU_UNSET: 125 return TargetID; 126 case cl::BOU_TRUE: 127 if (TargetID.isValid()) 128 return TargetID; 129 if (StandardID == nullptr) 130 report_fatal_error("Target cannot enable pass"); 131 return StandardID; 132 case cl::BOU_FALSE: 133 return IdentifyingPassPtr(); 134 } 135 llvm_unreachable("Invalid command line option state"); 136} 137 138/// Allow standard passes to be disabled by the command line, regardless of who 139/// is adding the pass. 140/// 141/// StandardID is the pass identified in the standard pass pipeline and provided 142/// to addPass(). It may be a target-specific ID in the case that the target 143/// directly adds its own pass, but in that case we harmlessly fall through. 144/// 145/// TargetID is the pass that the target has configured to override StandardID. 146/// 147/// StandardID may be a pseudo ID. In that case TargetID is the name of the real 148/// pass to run. This allows multiple options to control a single pass depending 149/// on where in the pipeline that pass is added. 150static IdentifyingPassPtr overridePass(AnalysisID StandardID, 151 IdentifyingPassPtr TargetID) { 152 if (StandardID == &PostRASchedulerID) 153 return applyDisable(TargetID, DisablePostRA); 154 155 if (StandardID == &BranchFolderPassID) 156 return applyDisable(TargetID, DisableBranchFold); 157 158 if (StandardID == &TailDuplicateID) 159 return applyDisable(TargetID, DisableTailDuplicate); 160 161 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID) 162 return applyDisable(TargetID, DisableEarlyTailDup); 163 164 if (StandardID == &MachineBlockPlacementID) 165 return applyDisable(TargetID, DisableBlockPlacement); 166 167 if (StandardID == &StackSlotColoringID) 168 return applyDisable(TargetID, DisableSSC); 169 170 if (StandardID == &DeadMachineInstructionElimID) 171 return applyDisable(TargetID, DisableMachineDCE); 172 173 if (StandardID == &EarlyIfConverterID) 174 return applyDisable(TargetID, DisableEarlyIfConversion); 175 176 if (StandardID == &MachineLICMID) 177 return applyDisable(TargetID, DisableMachineLICM); 178 179 if (StandardID == &MachineCSEID) 180 return applyDisable(TargetID, DisableMachineCSE); 181 182 if (StandardID == &MachineSchedulerID) 183 return applyOverride(TargetID, EnableMachineSched, StandardID); 184 185 if (StandardID == &TargetPassConfig::PostRAMachineLICMID) 186 return applyDisable(TargetID, DisablePostRAMachineLICM); 187 188 if (StandardID == &MachineSinkingID) 189 return applyDisable(TargetID, DisableMachineSink); 190 191 if (StandardID == &MachineCopyPropagationID) 192 return applyDisable(TargetID, DisableCopyProp); 193 194 return TargetID; 195} 196 197//===---------------------------------------------------------------------===// 198/// TargetPassConfig 199//===---------------------------------------------------------------------===// 200 201INITIALIZE_PASS(TargetPassConfig, "targetpassconfig", 202 "Target Pass Configuration", false, false) 203char TargetPassConfig::ID = 0; 204 205// Pseudo Pass IDs. 206char TargetPassConfig::EarlyTailDuplicateID = 0; 207char TargetPassConfig::PostRAMachineLICMID = 0; 208 209namespace llvm { 210class PassConfigImpl { 211public: 212 // List of passes explicitly substituted by this target. Normally this is 213 // empty, but it is a convenient way to suppress or replace specific passes 214 // that are part of a standard pass pipeline without overridding the entire 215 // pipeline. This mechanism allows target options to inherit a standard pass's 216 // user interface. For example, a target may disable a standard pass by 217 // default by substituting a pass ID of zero, and the user may still enable 218 // that standard pass with an explicit command line option. 219 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses; 220 221 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass 222 /// is inserted after each instance of the first one. 223 SmallVector<std::pair<AnalysisID, IdentifyingPassPtr>, 4> InsertedPasses; 224}; 225} // namespace llvm 226 227// Out of line virtual method. 228TargetPassConfig::~TargetPassConfig() { 229 delete Impl; 230} 231 232// Out of line constructor provides default values for pass options and 233// registers all common codegen passes. 234TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm) 235 : ImmutablePass(ID), PM(&pm), StartAfter(nullptr), StopAfter(nullptr), 236 Started(true), Stopped(false), TM(tm), Impl(nullptr), Initialized(false), 237 DisableVerify(false), 238 EnableTailMerge(true) { 239 240 Impl = new PassConfigImpl(); 241 242 // Register all target independent codegen passes to activate their PassIDs, 243 // including this pass itself. 244 initializeCodeGen(*PassRegistry::getPassRegistry()); 245 246 // Substitute Pseudo Pass IDs for real ones. 247 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID); 248 substitutePass(&PostRAMachineLICMID, &MachineLICMID); 249 250 // Temporarily disable experimental passes. 251 const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>(); 252 if (!ST.useMachineScheduler()) 253 disablePass(&MachineSchedulerID); 254} 255 256/// Insert InsertedPassID pass after TargetPassID. 257void TargetPassConfig::insertPass(AnalysisID TargetPassID, 258 IdentifyingPassPtr InsertedPassID) { 259 assert(((!InsertedPassID.isInstance() && 260 TargetPassID != InsertedPassID.getID()) || 261 (InsertedPassID.isInstance() && 262 TargetPassID != InsertedPassID.getInstance()->getPassID())) && 263 "Insert a pass after itself!"); 264 std::pair<AnalysisID, IdentifyingPassPtr> P(TargetPassID, InsertedPassID); 265 Impl->InsertedPasses.push_back(P); 266} 267 268/// createPassConfig - Create a pass configuration object to be used by 269/// addPassToEmitX methods for generating a pipeline of CodeGen passes. 270/// 271/// Targets may override this to extend TargetPassConfig. 272TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) { 273 return new TargetPassConfig(this, PM); 274} 275 276TargetPassConfig::TargetPassConfig() 277 : ImmutablePass(ID), PM(nullptr) { 278 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly"); 279} 280 281// Helper to verify the analysis is really immutable. 282void TargetPassConfig::setOpt(bool &Opt, bool Val) { 283 assert(!Initialized && "PassConfig is immutable"); 284 Opt = Val; 285} 286 287void TargetPassConfig::substitutePass(AnalysisID StandardID, 288 IdentifyingPassPtr TargetID) { 289 Impl->TargetPasses[StandardID] = TargetID; 290} 291 292IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const { 293 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator 294 I = Impl->TargetPasses.find(ID); 295 if (I == Impl->TargetPasses.end()) 296 return ID; 297 return I->second; 298} 299 300/// Add a pass to the PassManager if that pass is supposed to be run. If the 301/// Started/Stopped flags indicate either that the compilation should start at 302/// a later pass or that it should stop after an earlier pass, then do not add 303/// the pass. Finally, compare the current pass against the StartAfter 304/// and StopAfter options and change the Started/Stopped flags accordingly. 305void TargetPassConfig::addPass(Pass *P) { 306 assert(!Initialized && "PassConfig is immutable"); 307 308 // Cache the Pass ID here in case the pass manager finds this pass is 309 // redundant with ones already scheduled / available, and deletes it. 310 // Fundamentally, once we add the pass to the manager, we no longer own it 311 // and shouldn't reference it. 312 AnalysisID PassID = P->getPassID(); 313 314 if (Started && !Stopped) 315 PM->add(P); 316 else 317 delete P; 318 if (StopAfter == PassID) 319 Stopped = true; 320 if (StartAfter == PassID) 321 Started = true; 322 if (Stopped && !Started) 323 report_fatal_error("Cannot stop compilation after pass that is not run"); 324} 325 326/// Add a CodeGen pass at this point in the pipeline after checking for target 327/// and command line overrides. 328/// 329/// addPass cannot return a pointer to the pass instance because is internal the 330/// PassManager and the instance we create here may already be freed. 331AnalysisID TargetPassConfig::addPass(AnalysisID PassID) { 332 IdentifyingPassPtr TargetID = getPassSubstitution(PassID); 333 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID); 334 if (!FinalPtr.isValid()) 335 return nullptr; 336 337 Pass *P; 338 if (FinalPtr.isInstance()) 339 P = FinalPtr.getInstance(); 340 else { 341 P = Pass::createPass(FinalPtr.getID()); 342 if (!P) 343 llvm_unreachable("Pass ID not registered"); 344 } 345 AnalysisID FinalID = P->getPassID(); 346 addPass(P); // Ends the lifetime of P. 347 348 // Add the passes after the pass P if there is any. 349 for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator 350 I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end(); 351 I != E; ++I) { 352 if ((*I).first == PassID) { 353 assert((*I).second.isValid() && "Illegal Pass ID!"); 354 Pass *NP; 355 if ((*I).second.isInstance()) 356 NP = (*I).second.getInstance(); 357 else { 358 NP = Pass::createPass((*I).second.getID()); 359 assert(NP && "Pass ID not registered"); 360 } 361 addPass(NP); 362 } 363 } 364 return FinalID; 365} 366 367void TargetPassConfig::printAndVerify(const char *Banner) { 368 if (TM->shouldPrintMachineCode()) 369 addPass(createMachineFunctionPrinterPass(dbgs(), Banner)); 370 371 if (VerifyMachineCode) 372 addPass(createMachineVerifierPass(Banner)); 373} 374 375/// Add common target configurable passes that perform LLVM IR to IR transforms 376/// following machine independent optimization. 377void TargetPassConfig::addIRPasses() { 378 // Basic AliasAnalysis support. 379 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that 380 // BasicAliasAnalysis wins if they disagree. This is intended to help 381 // support "obvious" type-punning idioms. 382 addPass(createTypeBasedAliasAnalysisPass()); 383 addPass(createBasicAliasAnalysisPass()); 384 385 // Before running any passes, run the verifier to determine if the input 386 // coming from the front-end and/or optimizer is valid. 387 if (!DisableVerify) { 388 addPass(createVerifierPass()); 389 addPass(createDebugInfoVerifierPass()); 390 } 391 392 // Run loop strength reduction before anything else. 393 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) { 394 addPass(createLoopStrengthReducePass()); 395 if (PrintLSR) 396 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n")); 397 } 398 399 addPass(createGCLoweringPass()); 400 401 // Make sure that no unreachable blocks are instruction selected. 402 addPass(createUnreachableBlockEliminationPass()); 403 404 // Prepare expensive constants for SelectionDAG. 405 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting) 406 addPass(createConstantHoistingPass()); 407} 408 409/// Turn exception handling constructs into something the code generators can 410/// handle. 411void TargetPassConfig::addPassesToHandleExceptions() { 412 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) { 413 case ExceptionHandling::SjLj: 414 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both 415 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise, 416 // catch info can get misplaced when a selector ends up more than one block 417 // removed from the parent invoke(s). This could happen when a landing 418 // pad is shared by multiple invokes and is also a target of a normal 419 // edge from elsewhere. 420 addPass(createSjLjEHPreparePass(TM)); 421 // FALLTHROUGH 422 case ExceptionHandling::DwarfCFI: 423 case ExceptionHandling::ARM: 424 case ExceptionHandling::Win64: 425 addPass(createDwarfEHPass(TM)); 426 break; 427 case ExceptionHandling::None: 428 addPass(createLowerInvokePass()); 429 430 // The lower invoke pass may create unreachable code. Remove it. 431 addPass(createUnreachableBlockEliminationPass()); 432 break; 433 } 434} 435 436/// Add pass to prepare the LLVM IR for code generation. This should be done 437/// before exception handling preparation passes. 438void TargetPassConfig::addCodeGenPrepare() { 439 if (getOptLevel() != CodeGenOpt::None && !DisableCGP) 440 addPass(createCodeGenPreparePass(TM)); 441} 442 443/// Add common passes that perform LLVM IR to IR transforms in preparation for 444/// instruction selection. 445void TargetPassConfig::addISelPrepare() { 446 addPreISel(); 447 448 // Need to verify DebugInfo *before* creating the stack protector analysis. 449 // It's a function pass, and verifying between it and its users causes a 450 // crash. 451 if (!DisableVerify) 452 addPass(createDebugInfoVerifierPass()); 453 454 addPass(createStackProtectorPass(TM)); 455 456 if (PrintISelInput) 457 addPass(createPrintFunctionPass( 458 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n")); 459 460 // All passes which modify the LLVM IR are now complete; run the verifier 461 // to ensure that the IR is valid. 462 if (!DisableVerify) 463 addPass(createVerifierPass()); 464} 465 466/// Add the complete set of target-independent postISel code generator passes. 467/// 468/// This can be read as the standard order of major LLVM CodeGen stages. Stages 469/// with nontrivial configuration or multiple passes are broken out below in 470/// add%Stage routines. 471/// 472/// Any TargetPassConfig::addXX routine may be overriden by the Target. The 473/// addPre/Post methods with empty header implementations allow injecting 474/// target-specific fixups just before or after major stages. Additionally, 475/// targets have the flexibility to change pass order within a stage by 476/// overriding default implementation of add%Stage routines below. Each 477/// technique has maintainability tradeoffs because alternate pass orders are 478/// not well supported. addPre/Post works better if the target pass is easily 479/// tied to a common pass. But if it has subtle dependencies on multiple passes, 480/// the target should override the stage instead. 481/// 482/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection 483/// before/after any target-independent pass. But it's currently overkill. 484void TargetPassConfig::addMachinePasses() { 485 // Insert a machine instr printer pass after the specified pass. 486 // If -print-machineinstrs specified, print machineinstrs after all passes. 487 if (StringRef(PrintMachineInstrs.getValue()).equals("")) 488 TM->Options.PrintMachineCode = true; 489 else if (!StringRef(PrintMachineInstrs.getValue()) 490 .equals("option-unspecified")) { 491 const PassRegistry *PR = PassRegistry::getPassRegistry(); 492 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue()); 493 const PassInfo *IPI = PR->getPassInfo(StringRef("print-machineinstrs")); 494 assert (TPI && IPI && "Pass ID not registered!"); 495 const char *TID = (const char *)(TPI->getTypeInfo()); 496 const char *IID = (const char *)(IPI->getTypeInfo()); 497 insertPass(TID, IID); 498 } 499 500 // Print the instruction selected machine code... 501 printAndVerify("After Instruction Selection"); 502 503 // Expand pseudo-instructions emitted by ISel. 504 if (addPass(&ExpandISelPseudosID)) 505 printAndVerify("After ExpandISelPseudos"); 506 507 // Add passes that optimize machine instructions in SSA form. 508 if (getOptLevel() != CodeGenOpt::None) { 509 addMachineSSAOptimization(); 510 } else { 511 // If the target requests it, assign local variables to stack slots relative 512 // to one another and simplify frame index references where possible. 513 addPass(&LocalStackSlotAllocationID); 514 } 515 516 // Run pre-ra passes. 517 if (addPreRegAlloc()) 518 printAndVerify("After PreRegAlloc passes"); 519 520 // Run register allocation and passes that are tightly coupled with it, 521 // including phi elimination and scheduling. 522 if (getOptimizeRegAlloc()) 523 addOptimizedRegAlloc(createRegAllocPass(true)); 524 else 525 addFastRegAlloc(createRegAllocPass(false)); 526 527 // Run post-ra passes. 528 if (addPostRegAlloc()) 529 printAndVerify("After PostRegAlloc passes"); 530 531 // Insert prolog/epilog code. Eliminate abstract frame index references... 532 addPass(&PrologEpilogCodeInserterID); 533 printAndVerify("After PrologEpilogCodeInserter"); 534 535 /// Add passes that optimize machine instructions after register allocation. 536 if (getOptLevel() != CodeGenOpt::None) 537 addMachineLateOptimization(); 538 539 // Expand pseudo instructions before second scheduling pass. 540 addPass(&ExpandPostRAPseudosID); 541 printAndVerify("After ExpandPostRAPseudos"); 542 543 // Run pre-sched2 passes. 544 if (addPreSched2()) 545 printAndVerify("After PreSched2 passes"); 546 547 // Second pass scheduler. 548 if (getOptLevel() != CodeGenOpt::None) { 549 if (MISchedPostRA) 550 addPass(&PostMachineSchedulerID); 551 else 552 addPass(&PostRASchedulerID); 553 printAndVerify("After PostRAScheduler"); 554 } 555 556 // GC 557 if (addGCPasses()) { 558 if (PrintGCInfo) 559 addPass(createGCInfoPrinter(dbgs())); 560 } 561 562 // Basic block placement. 563 if (getOptLevel() != CodeGenOpt::None) 564 addBlockPlacement(); 565 566 if (addPreEmitPass()) 567 printAndVerify("After PreEmit passes"); 568 569 if (EnableStackMapLiveness || EnablePatchPointLiveness) 570 addPass(&StackMapLivenessID); 571} 572 573/// Add passes that optimize machine instructions in SSA form. 574void TargetPassConfig::addMachineSSAOptimization() { 575 // Pre-ra tail duplication. 576 if (addPass(&EarlyTailDuplicateID)) 577 printAndVerify("After Pre-RegAlloc TailDuplicate"); 578 579 // Optimize PHIs before DCE: removing dead PHI cycles may make more 580 // instructions dead. 581 addPass(&OptimizePHIsID); 582 583 // This pass merges large allocas. StackSlotColoring is a different pass 584 // which merges spill slots. 585 addPass(&StackColoringID); 586 587 // If the target requests it, assign local variables to stack slots relative 588 // to one another and simplify frame index references where possible. 589 addPass(&LocalStackSlotAllocationID); 590 591 // With optimization, dead code should already be eliminated. However 592 // there is one known exception: lowered code for arguments that are only 593 // used by tail calls, where the tail calls reuse the incoming stack 594 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll). 595 addPass(&DeadMachineInstructionElimID); 596 printAndVerify("After codegen DCE pass"); 597 598 // Allow targets to insert passes that improve instruction level parallelism, 599 // like if-conversion. Such passes will typically need dominator trees and 600 // loop info, just like LICM and CSE below. 601 if (addILPOpts()) 602 printAndVerify("After ILP optimizations"); 603 604 addPass(&MachineLICMID); 605 addPass(&MachineCSEID); 606 addPass(&MachineSinkingID); 607 printAndVerify("After Machine LICM, CSE and Sinking passes"); 608 609 addPass(&PeepholeOptimizerID); 610 printAndVerify("After codegen peephole optimization pass"); 611} 612 613//===---------------------------------------------------------------------===// 614/// Register Allocation Pass Configuration 615//===---------------------------------------------------------------------===// 616 617bool TargetPassConfig::getOptimizeRegAlloc() const { 618 switch (OptimizeRegAlloc) { 619 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None; 620 case cl::BOU_TRUE: return true; 621 case cl::BOU_FALSE: return false; 622 } 623 llvm_unreachable("Invalid optimize-regalloc state"); 624} 625 626/// RegisterRegAlloc's global Registry tracks allocator registration. 627MachinePassRegistry RegisterRegAlloc::Registry; 628 629/// A dummy default pass factory indicates whether the register allocator is 630/// overridden on the command line. 631static FunctionPass *useDefaultRegisterAllocator() { return nullptr; } 632static RegisterRegAlloc 633defaultRegAlloc("default", 634 "pick register allocator based on -O option", 635 useDefaultRegisterAllocator); 636 637/// -regalloc=... command line option. 638static cl::opt<RegisterRegAlloc::FunctionPassCtor, false, 639 RegisterPassParser<RegisterRegAlloc> > 640RegAlloc("regalloc", 641 cl::init(&useDefaultRegisterAllocator), 642 cl::desc("Register allocator to use")); 643 644 645/// Instantiate the default register allocator pass for this target for either 646/// the optimized or unoptimized allocation path. This will be added to the pass 647/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc 648/// in the optimized case. 649/// 650/// A target that uses the standard regalloc pass order for fast or optimized 651/// allocation may still override this for per-target regalloc 652/// selection. But -regalloc=... always takes precedence. 653FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) { 654 if (Optimized) 655 return createGreedyRegisterAllocator(); 656 else 657 return createFastRegisterAllocator(); 658} 659 660/// Find and instantiate the register allocation pass requested by this target 661/// at the current optimization level. Different register allocators are 662/// defined as separate passes because they may require different analysis. 663/// 664/// This helper ensures that the regalloc= option is always available, 665/// even for targets that override the default allocator. 666/// 667/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs, 668/// this can be folded into addPass. 669FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) { 670 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault(); 671 672 // Initialize the global default. 673 if (!Ctor) { 674 Ctor = RegAlloc; 675 RegisterRegAlloc::setDefault(RegAlloc); 676 } 677 if (Ctor != useDefaultRegisterAllocator) 678 return Ctor(); 679 680 // With no -regalloc= override, ask the target for a regalloc pass. 681 return createTargetRegisterAllocator(Optimized); 682} 683 684/// Add the minimum set of target-independent passes that are required for 685/// register allocation. No coalescing or scheduling. 686void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) { 687 addPass(&PHIEliminationID); 688 addPass(&TwoAddressInstructionPassID); 689 690 addPass(RegAllocPass); 691 printAndVerify("After Register Allocation"); 692} 693 694/// Add standard target-independent passes that are tightly coupled with 695/// optimized register allocation, including coalescing, machine instruction 696/// scheduling, and register allocation itself. 697void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) { 698 addPass(&ProcessImplicitDefsID); 699 700 // LiveVariables currently requires pure SSA form. 701 // 702 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, 703 // LiveVariables can be removed completely, and LiveIntervals can be directly 704 // computed. (We still either need to regenerate kill flags after regalloc, or 705 // preferably fix the scavenger to not depend on them). 706 addPass(&LiveVariablesID); 707 708 // Edge splitting is smarter with machine loop info. 709 addPass(&MachineLoopInfoID); 710 addPass(&PHIEliminationID); 711 712 // Eventually, we want to run LiveIntervals before PHI elimination. 713 if (EarlyLiveIntervals) 714 addPass(&LiveIntervalsID); 715 716 addPass(&TwoAddressInstructionPassID); 717 addPass(&RegisterCoalescerID); 718 719 // PreRA instruction scheduling. 720 if (addPass(&MachineSchedulerID)) 721 printAndVerify("After Machine Scheduling"); 722 723 // Add the selected register allocation pass. 724 addPass(RegAllocPass); 725 printAndVerify("After Register Allocation, before rewriter"); 726 727 // Allow targets to change the register assignments before rewriting. 728 if (addPreRewrite()) 729 printAndVerify("After pre-rewrite passes"); 730 731 // Finally rewrite virtual registers. 732 addPass(&VirtRegRewriterID); 733 printAndVerify("After Virtual Register Rewriter"); 734 735 // Perform stack slot coloring and post-ra machine LICM. 736 // 737 // FIXME: Re-enable coloring with register when it's capable of adding 738 // kill markers. 739 addPass(&StackSlotColoringID); 740 741 // Run post-ra machine LICM to hoist reloads / remats. 742 // 743 // FIXME: can this move into MachineLateOptimization? 744 addPass(&PostRAMachineLICMID); 745 746 printAndVerify("After StackSlotColoring and postra Machine LICM"); 747} 748 749//===---------------------------------------------------------------------===// 750/// Post RegAlloc Pass Configuration 751//===---------------------------------------------------------------------===// 752 753/// Add passes that optimize machine instructions after register allocation. 754void TargetPassConfig::addMachineLateOptimization() { 755 // Branch folding must be run after regalloc and prolog/epilog insertion. 756 if (addPass(&BranchFolderPassID)) 757 printAndVerify("After BranchFolding"); 758 759 // Tail duplication. 760 // Note that duplicating tail just increases code size and degrades 761 // performance for targets that require Structured Control Flow. 762 // In addition it can also make CFG irreducible. Thus we disable it. 763 if (!TM->requiresStructuredCFG() && addPass(&TailDuplicateID)) 764 printAndVerify("After TailDuplicate"); 765 766 // Copy propagation. 767 if (addPass(&MachineCopyPropagationID)) 768 printAndVerify("After copy propagation pass"); 769} 770 771/// Add standard GC passes. 772bool TargetPassConfig::addGCPasses() { 773 addPass(&GCMachineCodeAnalysisID); 774 return true; 775} 776 777/// Add standard basic block placement passes. 778void TargetPassConfig::addBlockPlacement() { 779 if (addPass(&MachineBlockPlacementID)) { 780 // Run a separate pass to collect block placement statistics. 781 if (EnableBlockPlacementStats) 782 addPass(&MachineBlockPlacementStatsID); 783 784 printAndVerify("After machine block placement."); 785 } 786} 787