1//===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11// register allocator for LLVM. This allocator works by constructing a PBQP
12// problem representing the register allocation problem under consideration,
13// solving this using a PBQP solver, and mapping the solution back to a
14// register assignment. If any variables are selected for spilling then spill
15// code is inserted and the process repeated.
16//
17// The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18// for register allocation. For more information on PBQP for register
19// allocation, see the following papers:
20//
21//   (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22//   PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23//   (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
24//
25//   (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26//   architectures. In Proceedings of the Joint Conference on Languages,
27//   Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
28//   NY, USA, 139-148.
29//
30//===----------------------------------------------------------------------===//
31
32#include "llvm/CodeGen/RegAllocPBQP.h"
33#include "RegisterCoalescer.h"
34#include "Spiller.h"
35#include "llvm/Analysis/AliasAnalysis.h"
36#include "llvm/CodeGen/CalcSpillWeights.h"
37#include "llvm/CodeGen/LiveIntervalAnalysis.h"
38#include "llvm/CodeGen/LiveRangeEdit.h"
39#include "llvm/CodeGen/LiveStackAnalysis.h"
40#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
41#include "llvm/CodeGen/MachineDominators.h"
42#include "llvm/CodeGen/MachineFunctionPass.h"
43#include "llvm/CodeGen/MachineLoopInfo.h"
44#include "llvm/CodeGen/MachineRegisterInfo.h"
45#include "llvm/CodeGen/RegAllocRegistry.h"
46#include "llvm/CodeGen/VirtRegMap.h"
47#include "llvm/IR/Module.h"
48#include "llvm/Support/Debug.h"
49#include "llvm/Support/FileSystem.h"
50#include "llvm/Support/raw_ostream.h"
51#include "llvm/Target/TargetInstrInfo.h"
52#include "llvm/Target/TargetMachine.h"
53#include <limits>
54#include <memory>
55#include <set>
56#include <sstream>
57#include <vector>
58
59using namespace llvm;
60
61#define DEBUG_TYPE "regalloc"
62
63static RegisterRegAlloc
64registerPBQPRepAlloc("pbqp", "PBQP register allocator",
65                       createDefaultPBQPRegisterAllocator);
66
67static cl::opt<bool>
68pbqpCoalescing("pbqp-coalescing",
69                cl::desc("Attempt coalescing during PBQP register allocation."),
70                cl::init(false), cl::Hidden);
71
72#ifndef NDEBUG
73static cl::opt<bool>
74pbqpDumpGraphs("pbqp-dump-graphs",
75               cl::desc("Dump graphs for each function/round in the compilation unit."),
76               cl::init(false), cl::Hidden);
77#endif
78
79namespace {
80
81///
82/// PBQP based allocators solve the register allocation problem by mapping
83/// register allocation problems to Partitioned Boolean Quadratic
84/// Programming problems.
85class RegAllocPBQP : public MachineFunctionPass {
86public:
87
88  static char ID;
89
90  /// Construct a PBQP register allocator.
91  RegAllocPBQP(std::unique_ptr<PBQPBuilder> &b, char *cPassID=nullptr)
92      : MachineFunctionPass(ID), builder(b.release()), customPassID(cPassID) {
93    initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
94    initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
95    initializeLiveStacksPass(*PassRegistry::getPassRegistry());
96    initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
97  }
98
99  /// Return the pass name.
100  const char* getPassName() const override {
101    return "PBQP Register Allocator";
102  }
103
104  /// PBQP analysis usage.
105  void getAnalysisUsage(AnalysisUsage &au) const override;
106
107  /// Perform register allocation
108  bool runOnMachineFunction(MachineFunction &MF) override;
109
110private:
111
112  typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
113  typedef std::vector<const LiveInterval*> Node2LIMap;
114  typedef std::vector<unsigned> AllowedSet;
115  typedef std::vector<AllowedSet> AllowedSetMap;
116  typedef std::pair<unsigned, unsigned> RegPair;
117  typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
118  typedef std::set<unsigned> RegSet;
119
120  std::unique_ptr<PBQPBuilder> builder;
121
122  char *customPassID;
123
124  MachineFunction *mf;
125  const TargetMachine *tm;
126  const TargetRegisterInfo *tri;
127  const TargetInstrInfo *tii;
128  MachineRegisterInfo *mri;
129  const MachineBlockFrequencyInfo *mbfi;
130
131  std::unique_ptr<Spiller> spiller;
132  LiveIntervals *lis;
133  LiveStacks *lss;
134  VirtRegMap *vrm;
135
136  RegSet vregsToAlloc, emptyIntervalVRegs;
137
138  /// \brief Finds the initial set of vreg intervals to allocate.
139  void findVRegIntervalsToAlloc();
140
141  /// \brief Given a solved PBQP problem maps this solution back to a register
142  /// assignment.
143  bool mapPBQPToRegAlloc(const PBQPRAProblem &problem,
144                         const PBQP::Solution &solution);
145
146  /// \brief Postprocessing before final spilling. Sets basic block "live in"
147  /// variables.
148  void finalizeAlloc() const;
149
150};
151
152char RegAllocPBQP::ID = 0;
153
154} // End anonymous namespace.
155
156unsigned PBQPRAProblem::getVRegForNode(PBQPRAGraph::NodeId node) const {
157  Node2VReg::const_iterator vregItr = node2VReg.find(node);
158  assert(vregItr != node2VReg.end() && "No vreg for node.");
159  return vregItr->second;
160}
161
162PBQPRAGraph::NodeId PBQPRAProblem::getNodeForVReg(unsigned vreg) const {
163  VReg2Node::const_iterator nodeItr = vreg2Node.find(vreg);
164  assert(nodeItr != vreg2Node.end() && "No node for vreg.");
165  return nodeItr->second;
166
167}
168
169const PBQPRAProblem::AllowedSet&
170  PBQPRAProblem::getAllowedSet(unsigned vreg) const {
171  AllowedSetMap::const_iterator allowedSetItr = allowedSets.find(vreg);
172  assert(allowedSetItr != allowedSets.end() && "No pregs for vreg.");
173  const AllowedSet &allowedSet = allowedSetItr->second;
174  return allowedSet;
175}
176
177unsigned PBQPRAProblem::getPRegForOption(unsigned vreg, unsigned option) const {
178  assert(isPRegOption(vreg, option) && "Not a preg option.");
179
180  const AllowedSet& allowedSet = getAllowedSet(vreg);
181  assert(option <= allowedSet.size() && "Option outside allowed set.");
182  return allowedSet[option - 1];
183}
184
185PBQPRAProblem *PBQPBuilder::build(MachineFunction *mf, const LiveIntervals *lis,
186                                  const MachineBlockFrequencyInfo *mbfi,
187                                  const RegSet &vregs) {
188
189  LiveIntervals *LIS = const_cast<LiveIntervals*>(lis);
190  MachineRegisterInfo *mri = &mf->getRegInfo();
191  const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo();
192
193  std::unique_ptr<PBQPRAProblem> p(new PBQPRAProblem());
194  PBQPRAGraph &g = p->getGraph();
195  RegSet pregs;
196
197  // Collect the set of preg intervals, record that they're used in the MF.
198  for (unsigned Reg = 1, e = tri->getNumRegs(); Reg != e; ++Reg) {
199    if (mri->def_empty(Reg))
200      continue;
201    pregs.insert(Reg);
202    mri->setPhysRegUsed(Reg);
203  }
204
205  // Iterate over vregs.
206  for (RegSet::const_iterator vregItr = vregs.begin(), vregEnd = vregs.end();
207       vregItr != vregEnd; ++vregItr) {
208    unsigned vreg = *vregItr;
209    const TargetRegisterClass *trc = mri->getRegClass(vreg);
210    LiveInterval *vregLI = &LIS->getInterval(vreg);
211
212    // Record any overlaps with regmask operands.
213    BitVector regMaskOverlaps;
214    LIS->checkRegMaskInterference(*vregLI, regMaskOverlaps);
215
216    // Compute an initial allowed set for the current vreg.
217    typedef std::vector<unsigned> VRAllowed;
218    VRAllowed vrAllowed;
219    ArrayRef<MCPhysReg> rawOrder = trc->getRawAllocationOrder(*mf);
220    for (unsigned i = 0; i != rawOrder.size(); ++i) {
221      unsigned preg = rawOrder[i];
222      if (mri->isReserved(preg))
223        continue;
224
225      // vregLI crosses a regmask operand that clobbers preg.
226      if (!regMaskOverlaps.empty() && !regMaskOverlaps.test(preg))
227        continue;
228
229      // vregLI overlaps fixed regunit interference.
230      bool Interference = false;
231      for (MCRegUnitIterator Units(preg, tri); Units.isValid(); ++Units) {
232        if (vregLI->overlaps(LIS->getRegUnit(*Units))) {
233          Interference = true;
234          break;
235        }
236      }
237      if (Interference)
238        continue;
239
240      // preg is usable for this virtual register.
241      vrAllowed.push_back(preg);
242    }
243
244    PBQP::Vector nodeCosts(vrAllowed.size() + 1, 0);
245
246    PBQP::PBQPNum spillCost = (vregLI->weight != 0.0) ?
247        vregLI->weight : std::numeric_limits<PBQP::PBQPNum>::min();
248
249    addSpillCosts(nodeCosts, spillCost);
250
251    // Construct the node.
252    PBQPRAGraph::NodeId nId = g.addNode(std::move(nodeCosts));
253
254    // Record the mapping and allowed set in the problem.
255    p->recordVReg(vreg, nId, vrAllowed.begin(), vrAllowed.end());
256
257  }
258
259  for (RegSet::const_iterator vr1Itr = vregs.begin(), vrEnd = vregs.end();
260         vr1Itr != vrEnd; ++vr1Itr) {
261    unsigned vr1 = *vr1Itr;
262    const LiveInterval &l1 = lis->getInterval(vr1);
263    const PBQPRAProblem::AllowedSet &vr1Allowed = p->getAllowedSet(vr1);
264
265    for (RegSet::const_iterator vr2Itr = std::next(vr1Itr); vr2Itr != vrEnd;
266         ++vr2Itr) {
267      unsigned vr2 = *vr2Itr;
268      const LiveInterval &l2 = lis->getInterval(vr2);
269      const PBQPRAProblem::AllowedSet &vr2Allowed = p->getAllowedSet(vr2);
270
271      assert(!l2.empty() && "Empty interval in vreg set?");
272      if (l1.overlaps(l2)) {
273        PBQP::Matrix edgeCosts(vr1Allowed.size()+1, vr2Allowed.size()+1, 0);
274        addInterferenceCosts(edgeCosts, vr1Allowed, vr2Allowed, tri);
275
276        g.addEdge(p->getNodeForVReg(vr1), p->getNodeForVReg(vr2),
277                  std::move(edgeCosts));
278      }
279    }
280  }
281
282  return p.release();
283}
284
285void PBQPBuilder::addSpillCosts(PBQP::Vector &costVec,
286                                PBQP::PBQPNum spillCost) {
287  costVec[0] = spillCost;
288}
289
290void PBQPBuilder::addInterferenceCosts(
291                                    PBQP::Matrix &costMat,
292                                    const PBQPRAProblem::AllowedSet &vr1Allowed,
293                                    const PBQPRAProblem::AllowedSet &vr2Allowed,
294                                    const TargetRegisterInfo *tri) {
295  assert(costMat.getRows() == vr1Allowed.size() + 1 && "Matrix height mismatch.");
296  assert(costMat.getCols() == vr2Allowed.size() + 1 && "Matrix width mismatch.");
297
298  for (unsigned i = 0; i != vr1Allowed.size(); ++i) {
299    unsigned preg1 = vr1Allowed[i];
300
301    for (unsigned j = 0; j != vr2Allowed.size(); ++j) {
302      unsigned preg2 = vr2Allowed[j];
303
304      if (tri->regsOverlap(preg1, preg2)) {
305        costMat[i + 1][j + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
306      }
307    }
308  }
309}
310
311PBQPRAProblem *PBQPBuilderWithCoalescing::build(MachineFunction *mf,
312                                                const LiveIntervals *lis,
313                                                const MachineBlockFrequencyInfo *mbfi,
314                                                const RegSet &vregs) {
315
316  std::unique_ptr<PBQPRAProblem> p(PBQPBuilder::build(mf, lis, mbfi, vregs));
317  PBQPRAGraph &g = p->getGraph();
318
319  const TargetMachine &tm = mf->getTarget();
320  CoalescerPair cp(*tm.getRegisterInfo());
321
322  // Scan the machine function and add a coalescing cost whenever CoalescerPair
323  // gives the Ok.
324  for (const auto &mbb : *mf) {
325    for (const auto &mi : mbb) {
326      if (!cp.setRegisters(&mi)) {
327        continue; // Not coalescable.
328      }
329
330      if (cp.getSrcReg() == cp.getDstReg()) {
331        continue; // Already coalesced.
332      }
333
334      unsigned dst = cp.getDstReg(),
335               src = cp.getSrcReg();
336
337      const float copyFactor = 0.5; // Cost of copy relative to load. Current
338      // value plucked randomly out of the air.
339
340      PBQP::PBQPNum cBenefit =
341        copyFactor * LiveIntervals::getSpillWeight(false, true, mbfi, &mi);
342
343      if (cp.isPhys()) {
344        if (!mf->getRegInfo().isAllocatable(dst)) {
345          continue;
346        }
347
348        const PBQPRAProblem::AllowedSet &allowed = p->getAllowedSet(src);
349        unsigned pregOpt = 0;
350        while (pregOpt < allowed.size() && allowed[pregOpt] != dst) {
351          ++pregOpt;
352        }
353        if (pregOpt < allowed.size()) {
354          ++pregOpt; // +1 to account for spill option.
355          PBQPRAGraph::NodeId node = p->getNodeForVReg(src);
356          llvm::dbgs() << "Reading node costs for node " << node << "\n";
357          llvm::dbgs() << "Source node: " << &g.getNodeCosts(node) << "\n";
358          PBQP::Vector newCosts(g.getNodeCosts(node));
359          addPhysRegCoalesce(newCosts, pregOpt, cBenefit);
360          g.setNodeCosts(node, newCosts);
361        }
362      } else {
363        const PBQPRAProblem::AllowedSet *allowed1 = &p->getAllowedSet(dst);
364        const PBQPRAProblem::AllowedSet *allowed2 = &p->getAllowedSet(src);
365        PBQPRAGraph::NodeId node1 = p->getNodeForVReg(dst);
366        PBQPRAGraph::NodeId node2 = p->getNodeForVReg(src);
367        PBQPRAGraph::EdgeId edge = g.findEdge(node1, node2);
368        if (edge == g.invalidEdgeId()) {
369          PBQP::Matrix costs(allowed1->size() + 1, allowed2->size() + 1, 0);
370          addVirtRegCoalesce(costs, *allowed1, *allowed2, cBenefit);
371          g.addEdge(node1, node2, costs);
372        } else {
373          if (g.getEdgeNode1Id(edge) == node2) {
374            std::swap(node1, node2);
375            std::swap(allowed1, allowed2);
376          }
377          PBQP::Matrix costs(g.getEdgeCosts(edge));
378          addVirtRegCoalesce(costs, *allowed1, *allowed2, cBenefit);
379          g.setEdgeCosts(edge, costs);
380        }
381      }
382    }
383  }
384
385  return p.release();
386}
387
388void PBQPBuilderWithCoalescing::addPhysRegCoalesce(PBQP::Vector &costVec,
389                                                   unsigned pregOption,
390                                                   PBQP::PBQPNum benefit) {
391  costVec[pregOption] += -benefit;
392}
393
394void PBQPBuilderWithCoalescing::addVirtRegCoalesce(
395                                    PBQP::Matrix &costMat,
396                                    const PBQPRAProblem::AllowedSet &vr1Allowed,
397                                    const PBQPRAProblem::AllowedSet &vr2Allowed,
398                                    PBQP::PBQPNum benefit) {
399
400  assert(costMat.getRows() == vr1Allowed.size() + 1 && "Size mismatch.");
401  assert(costMat.getCols() == vr2Allowed.size() + 1 && "Size mismatch.");
402
403  for (unsigned i = 0; i != vr1Allowed.size(); ++i) {
404    unsigned preg1 = vr1Allowed[i];
405    for (unsigned j = 0; j != vr2Allowed.size(); ++j) {
406      unsigned preg2 = vr2Allowed[j];
407
408      if (preg1 == preg2) {
409        costMat[i + 1][j + 1] += -benefit;
410      }
411    }
412  }
413}
414
415
416void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
417  au.setPreservesCFG();
418  au.addRequired<AliasAnalysis>();
419  au.addPreserved<AliasAnalysis>();
420  au.addRequired<SlotIndexes>();
421  au.addPreserved<SlotIndexes>();
422  au.addRequired<LiveIntervals>();
423  au.addPreserved<LiveIntervals>();
424  //au.addRequiredID(SplitCriticalEdgesID);
425  if (customPassID)
426    au.addRequiredID(*customPassID);
427  au.addRequired<LiveStacks>();
428  au.addPreserved<LiveStacks>();
429  au.addRequired<MachineBlockFrequencyInfo>();
430  au.addPreserved<MachineBlockFrequencyInfo>();
431  au.addRequired<MachineLoopInfo>();
432  au.addPreserved<MachineLoopInfo>();
433  au.addRequired<MachineDominatorTree>();
434  au.addPreserved<MachineDominatorTree>();
435  au.addRequired<VirtRegMap>();
436  au.addPreserved<VirtRegMap>();
437  MachineFunctionPass::getAnalysisUsage(au);
438}
439
440void RegAllocPBQP::findVRegIntervalsToAlloc() {
441
442  // Iterate over all live ranges.
443  for (unsigned i = 0, e = mri->getNumVirtRegs(); i != e; ++i) {
444    unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
445    if (mri->reg_nodbg_empty(Reg))
446      continue;
447    LiveInterval *li = &lis->getInterval(Reg);
448
449    // If this live interval is non-empty we will use pbqp to allocate it.
450    // Empty intervals we allocate in a simple post-processing stage in
451    // finalizeAlloc.
452    if (!li->empty()) {
453      vregsToAlloc.insert(li->reg);
454    } else {
455      emptyIntervalVRegs.insert(li->reg);
456    }
457  }
458}
459
460bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAProblem &problem,
461                                     const PBQP::Solution &solution) {
462  // Set to true if we have any spills
463  bool anotherRoundNeeded = false;
464
465  // Clear the existing allocation.
466  vrm->clearAllVirt();
467
468  const PBQPRAGraph &g = problem.getGraph();
469  // Iterate over the nodes mapping the PBQP solution to a register
470  // assignment.
471  for (auto NId : g.nodeIds()) {
472    unsigned vreg = problem.getVRegForNode(NId);
473    unsigned alloc = solution.getSelection(NId);
474
475    if (problem.isPRegOption(vreg, alloc)) {
476      unsigned preg = problem.getPRegForOption(vreg, alloc);
477      DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> "
478            << tri->getName(preg) << "\n");
479      assert(preg != 0 && "Invalid preg selected.");
480      vrm->assignVirt2Phys(vreg, preg);
481    } else if (problem.isSpillOption(vreg, alloc)) {
482      vregsToAlloc.erase(vreg);
483      SmallVector<unsigned, 8> newSpills;
484      LiveRangeEdit LRE(&lis->getInterval(vreg), newSpills, *mf, *lis, vrm);
485      spiller->spill(LRE);
486
487      DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> SPILLED (Cost: "
488                   << LRE.getParent().weight << ", New vregs: ");
489
490      // Copy any newly inserted live intervals into the list of regs to
491      // allocate.
492      for (LiveRangeEdit::iterator itr = LRE.begin(), end = LRE.end();
493           itr != end; ++itr) {
494        LiveInterval &li = lis->getInterval(*itr);
495        assert(!li.empty() && "Empty spill range.");
496        DEBUG(dbgs() << PrintReg(li.reg, tri) << " ");
497        vregsToAlloc.insert(li.reg);
498      }
499
500      DEBUG(dbgs() << ")\n");
501
502      // We need another round if spill intervals were added.
503      anotherRoundNeeded |= !LRE.empty();
504    } else {
505      llvm_unreachable("Unknown allocation option.");
506    }
507  }
508
509  return !anotherRoundNeeded;
510}
511
512
513void RegAllocPBQP::finalizeAlloc() const {
514  // First allocate registers for the empty intervals.
515  for (RegSet::const_iterator
516         itr = emptyIntervalVRegs.begin(), end = emptyIntervalVRegs.end();
517         itr != end; ++itr) {
518    LiveInterval *li = &lis->getInterval(*itr);
519
520    unsigned physReg = mri->getSimpleHint(li->reg);
521
522    if (physReg == 0) {
523      const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
524      physReg = liRC->getRawAllocationOrder(*mf).front();
525    }
526
527    vrm->assignVirt2Phys(li->reg, physReg);
528  }
529}
530
531bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
532
533  mf = &MF;
534  tm = &mf->getTarget();
535  tri = tm->getRegisterInfo();
536  tii = tm->getInstrInfo();
537  mri = &mf->getRegInfo();
538
539  lis = &getAnalysis<LiveIntervals>();
540  lss = &getAnalysis<LiveStacks>();
541  mbfi = &getAnalysis<MachineBlockFrequencyInfo>();
542
543  calculateSpillWeightsAndHints(*lis, MF, getAnalysis<MachineLoopInfo>(),
544                                *mbfi);
545
546  vrm = &getAnalysis<VirtRegMap>();
547  spiller.reset(createInlineSpiller(*this, MF, *vrm));
548
549  mri->freezeReservedRegs(MF);
550
551  DEBUG(dbgs() << "PBQP Register Allocating for " << mf->getName() << "\n");
552
553  // Allocator main loop:
554  //
555  // * Map current regalloc problem to a PBQP problem
556  // * Solve the PBQP problem
557  // * Map the solution back to a register allocation
558  // * Spill if necessary
559  //
560  // This process is continued till no more spills are generated.
561
562  // Find the vreg intervals in need of allocation.
563  findVRegIntervalsToAlloc();
564
565#ifndef NDEBUG
566  const Function* func = mf->getFunction();
567  std::string fqn =
568    func->getParent()->getModuleIdentifier() + "." +
569    func->getName().str();
570#endif
571
572  // If there are non-empty intervals allocate them using pbqp.
573  if (!vregsToAlloc.empty()) {
574
575    bool pbqpAllocComplete = false;
576    unsigned round = 0;
577
578    while (!pbqpAllocComplete) {
579      DEBUG(dbgs() << "  PBQP Regalloc round " << round << ":\n");
580
581      std::unique_ptr<PBQPRAProblem> problem(
582          builder->build(mf, lis, mbfi, vregsToAlloc));
583
584#ifndef NDEBUG
585      if (pbqpDumpGraphs) {
586        std::ostringstream rs;
587        rs << round;
588        std::string graphFileName(fqn + "." + rs.str() + ".pbqpgraph");
589        std::string tmp;
590        raw_fd_ostream os(graphFileName.c_str(), tmp, sys::fs::F_Text);
591        DEBUG(dbgs() << "Dumping graph for round " << round << " to \""
592              << graphFileName << "\"\n");
593        problem->getGraph().dump(os);
594      }
595#endif
596
597      PBQP::Solution solution =
598        PBQP::RegAlloc::solve(problem->getGraph());
599
600      pbqpAllocComplete = mapPBQPToRegAlloc(*problem, solution);
601
602      ++round;
603    }
604  }
605
606  // Finalise allocation, allocate empty ranges.
607  finalizeAlloc();
608  vregsToAlloc.clear();
609  emptyIntervalVRegs.clear();
610
611  DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *vrm << "\n");
612
613  return true;
614}
615
616FunctionPass *
617llvm::createPBQPRegisterAllocator(std::unique_ptr<PBQPBuilder> &builder,
618                                  char *customPassID) {
619  return new RegAllocPBQP(builder, customPassID);
620}
621
622FunctionPass* llvm::createDefaultPBQPRegisterAllocator() {
623  std::unique_ptr<PBQPBuilder> Builder;
624  if (pbqpCoalescing)
625    Builder.reset(new PBQPBuilderWithCoalescing());
626  else
627    Builder.reset(new PBQPBuilder());
628  return createPBQPRegisterAllocator(Builder);
629}
630
631#undef DEBUG_TYPE
632