FunctionLoweringInfo.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- FunctionLoweringInfo.cpp ------------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements routines for translating functions from LLVM IR into
11// Machine IR.
12//
13//===----------------------------------------------------------------------===//
14
15#include "llvm/CodeGen/FunctionLoweringInfo.h"
16#include "llvm/ADT/PostOrderIterator.h"
17#include "llvm/CodeGen/Analysis.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineModuleInfo.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/IR/DataLayout.h"
24#include "llvm/IR/DebugInfo.h"
25#include "llvm/IR/DerivedTypes.h"
26#include "llvm/IR/Function.h"
27#include "llvm/IR/Instructions.h"
28#include "llvm/IR/IntrinsicInst.h"
29#include "llvm/IR/LLVMContext.h"
30#include "llvm/IR/Module.h"
31#include "llvm/Support/Debug.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/MathExtras.h"
34#include "llvm/Target/TargetFrameLowering.h"
35#include "llvm/Target/TargetInstrInfo.h"
36#include "llvm/Target/TargetLowering.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/Target/TargetRegisterInfo.h"
39#include <algorithm>
40using namespace llvm;
41
42#define DEBUG_TYPE "function-lowering-info"
43
44/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
45/// PHI nodes or outside of the basic block that defines it, or used by a
46/// switch or atomic instruction, which may expand to multiple basic blocks.
47static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
48  if (I->use_empty()) return false;
49  if (isa<PHINode>(I)) return true;
50  const BasicBlock *BB = I->getParent();
51  for (const User *U : I->users())
52    if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
53      return true;
54
55  return false;
56}
57
58void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
59                               SelectionDAG *DAG) {
60  const TargetLowering *TLI = TM.getTargetLowering();
61
62  Fn = &fn;
63  MF = &mf;
64  RegInfo = &MF->getRegInfo();
65
66  // Check whether the function can return without sret-demotion.
67  SmallVector<ISD::OutputArg, 4> Outs;
68  GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
69  CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
70                                       Fn->isVarArg(),
71                                       Outs, Fn->getContext());
72
73  // Initialize the mapping of values to registers.  This is only set up for
74  // instruction values that are used outside of the block that defines
75  // them.
76  Function::const_iterator BB = Fn->begin(), EB = Fn->end();
77  for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I)
78    if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
79      // Don't fold inalloca allocas or other dynamic allocas into the initial
80      // stack frame allocation, even if they are in the entry block.
81      if (!AI->isStaticAlloca())
82        continue;
83
84      if (const ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
85        Type *Ty = AI->getAllocatedType();
86        uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
87        unsigned Align =
88          std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
89                   AI->getAlignment());
90
91        TySize *= CUI->getZExtValue();   // Get total allocated size.
92        if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
93
94        StaticAllocaMap[AI] =
95          MF->getFrameInfo()->CreateStackObject(TySize, Align, false, AI);
96      }
97    }
98
99  for (; BB != EB; ++BB)
100    for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
101         I != E; ++I) {
102      // Look for dynamic allocas.
103      if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
104        if (!AI->isStaticAlloca()) {
105          unsigned Align = std::max(
106              (unsigned)TLI->getDataLayout()->getPrefTypeAlignment(
107                AI->getAllocatedType()),
108              AI->getAlignment());
109          unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
110          if (Align <= StackAlign)
111            Align = 0;
112          // Inform the Frame Information that we have variable-sized objects.
113          MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, AI);
114        }
115      }
116
117      // Look for inline asm that clobbers the SP register.
118      if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
119        ImmutableCallSite CS(I);
120        if (isa<InlineAsm>(CS.getCalledValue())) {
121          unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
122          std::vector<TargetLowering::AsmOperandInfo> Ops =
123            TLI->ParseConstraints(CS);
124          for (size_t I = 0, E = Ops.size(); I != E; ++I) {
125            TargetLowering::AsmOperandInfo &Op = Ops[I];
126            if (Op.Type == InlineAsm::isClobber) {
127              // Clobbers don't have SDValue operands, hence SDValue().
128              TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
129              std::pair<unsigned, const TargetRegisterClass*> PhysReg =
130                TLI->getRegForInlineAsmConstraint(Op.ConstraintCode,
131                                                  Op.ConstraintVT);
132              if (PhysReg.first == SP)
133                MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(true);
134            }
135          }
136        }
137      }
138
139      // Mark values used outside their block as exported, by allocating
140      // a virtual register for them.
141      if (isUsedOutsideOfDefiningBlock(I))
142        if (!isa<AllocaInst>(I) ||
143            !StaticAllocaMap.count(cast<AllocaInst>(I)))
144          InitializeRegForValue(I);
145
146      // Collect llvm.dbg.declare information. This is done now instead of
147      // during the initial isel pass through the IR so that it is done
148      // in a predictable order.
149      if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
150        MachineModuleInfo &MMI = MF->getMMI();
151        DIVariable DIVar(DI->getVariable());
152        assert((!DIVar || DIVar.isVariable()) &&
153          "Variable in DbgDeclareInst should be either null or a DIVariable.");
154        if (MMI.hasDebugInfo() &&
155            DIVar &&
156            !DI->getDebugLoc().isUnknown()) {
157          // Don't handle byval struct arguments or VLAs, for example.
158          // Non-byval arguments are handled here (they refer to the stack
159          // temporary alloca at this point).
160          const Value *Address = DI->getAddress();
161          if (Address) {
162            if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
163              Address = BCI->getOperand(0);
164            if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
165              DenseMap<const AllocaInst *, int>::iterator SI =
166                StaticAllocaMap.find(AI);
167              if (SI != StaticAllocaMap.end()) { // Check for VLAs.
168                int FI = SI->second;
169                MMI.setVariableDbgInfo(DI->getVariable(),
170                                       FI, DI->getDebugLoc());
171              }
172            }
173          }
174        }
175      }
176    }
177
178  // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
179  // also creates the initial PHI MachineInstrs, though none of the input
180  // operands are populated.
181  for (BB = Fn->begin(); BB != EB; ++BB) {
182    MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
183    MBBMap[BB] = MBB;
184    MF->push_back(MBB);
185
186    // Transfer the address-taken flag. This is necessary because there could
187    // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
188    // the first one should be marked.
189    if (BB->hasAddressTaken())
190      MBB->setHasAddressTaken();
191
192    // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
193    // appropriate.
194    for (BasicBlock::const_iterator I = BB->begin();
195         const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
196      if (PN->use_empty()) continue;
197
198      // Skip empty types
199      if (PN->getType()->isEmptyTy())
200        continue;
201
202      DebugLoc DL = PN->getDebugLoc();
203      unsigned PHIReg = ValueMap[PN];
204      assert(PHIReg && "PHI node does not have an assigned virtual register!");
205
206      SmallVector<EVT, 4> ValueVTs;
207      ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
208      for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
209        EVT VT = ValueVTs[vti];
210        unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
211        const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
212        for (unsigned i = 0; i != NumRegisters; ++i)
213          BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
214        PHIReg += NumRegisters;
215      }
216    }
217  }
218
219  // Mark landing pad blocks.
220  for (BB = Fn->begin(); BB != EB; ++BB)
221    if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
222      MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
223}
224
225/// clear - Clear out all the function-specific state. This returns this
226/// FunctionLoweringInfo to an empty state, ready to be used for a
227/// different function.
228void FunctionLoweringInfo::clear() {
229  assert(CatchInfoFound.size() == CatchInfoLost.size() &&
230         "Not all catch info was assigned to a landing pad!");
231
232  MBBMap.clear();
233  ValueMap.clear();
234  StaticAllocaMap.clear();
235#ifndef NDEBUG
236  CatchInfoLost.clear();
237  CatchInfoFound.clear();
238#endif
239  LiveOutRegInfo.clear();
240  VisitedBBs.clear();
241  ArgDbgValues.clear();
242  ByValArgFrameIndexMap.clear();
243  RegFixups.clear();
244}
245
246/// CreateReg - Allocate a single virtual register for the given type.
247unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
248  return RegInfo->
249    createVirtualRegister(TM.getTargetLowering()->getRegClassFor(VT));
250}
251
252/// CreateRegs - Allocate the appropriate number of virtual registers of
253/// the correctly promoted or expanded types.  Assign these registers
254/// consecutive vreg numbers and return the first assigned number.
255///
256/// In the case that the given value has struct or array type, this function
257/// will assign registers for each member or element.
258///
259unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
260  const TargetLowering *TLI = TM.getTargetLowering();
261
262  SmallVector<EVT, 4> ValueVTs;
263  ComputeValueVTs(*TLI, Ty, ValueVTs);
264
265  unsigned FirstReg = 0;
266  for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
267    EVT ValueVT = ValueVTs[Value];
268    MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
269
270    unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
271    for (unsigned i = 0; i != NumRegs; ++i) {
272      unsigned R = CreateReg(RegisterVT);
273      if (!FirstReg) FirstReg = R;
274    }
275  }
276  return FirstReg;
277}
278
279/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
280/// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
281/// the register's LiveOutInfo is for a smaller bit width, it is extended to
282/// the larger bit width by zero extension. The bit width must be no smaller
283/// than the LiveOutInfo's existing bit width.
284const FunctionLoweringInfo::LiveOutInfo *
285FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
286  if (!LiveOutRegInfo.inBounds(Reg))
287    return nullptr;
288
289  LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
290  if (!LOI->IsValid)
291    return nullptr;
292
293  if (BitWidth > LOI->KnownZero.getBitWidth()) {
294    LOI->NumSignBits = 1;
295    LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
296    LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
297  }
298
299  return LOI;
300}
301
302/// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
303/// register based on the LiveOutInfo of its operands.
304void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
305  Type *Ty = PN->getType();
306  if (!Ty->isIntegerTy() || Ty->isVectorTy())
307    return;
308
309  const TargetLowering *TLI = TM.getTargetLowering();
310
311  SmallVector<EVT, 1> ValueVTs;
312  ComputeValueVTs(*TLI, Ty, ValueVTs);
313  assert(ValueVTs.size() == 1 &&
314         "PHIs with non-vector integer types should have a single VT.");
315  EVT IntVT = ValueVTs[0];
316
317  if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
318    return;
319  IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
320  unsigned BitWidth = IntVT.getSizeInBits();
321
322  unsigned DestReg = ValueMap[PN];
323  if (!TargetRegisterInfo::isVirtualRegister(DestReg))
324    return;
325  LiveOutRegInfo.grow(DestReg);
326  LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
327
328  Value *V = PN->getIncomingValue(0);
329  if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
330    DestLOI.NumSignBits = 1;
331    APInt Zero(BitWidth, 0);
332    DestLOI.KnownZero = Zero;
333    DestLOI.KnownOne = Zero;
334    return;
335  }
336
337  if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
338    APInt Val = CI->getValue().zextOrTrunc(BitWidth);
339    DestLOI.NumSignBits = Val.getNumSignBits();
340    DestLOI.KnownZero = ~Val;
341    DestLOI.KnownOne = Val;
342  } else {
343    assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
344                                "CopyToReg node was created.");
345    unsigned SrcReg = ValueMap[V];
346    if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
347      DestLOI.IsValid = false;
348      return;
349    }
350    const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
351    if (!SrcLOI) {
352      DestLOI.IsValid = false;
353      return;
354    }
355    DestLOI = *SrcLOI;
356  }
357
358  assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
359         DestLOI.KnownOne.getBitWidth() == BitWidth &&
360         "Masks should have the same bit width as the type.");
361
362  for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
363    Value *V = PN->getIncomingValue(i);
364    if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
365      DestLOI.NumSignBits = 1;
366      APInt Zero(BitWidth, 0);
367      DestLOI.KnownZero = Zero;
368      DestLOI.KnownOne = Zero;
369      return;
370    }
371
372    if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
373      APInt Val = CI->getValue().zextOrTrunc(BitWidth);
374      DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
375      DestLOI.KnownZero &= ~Val;
376      DestLOI.KnownOne &= Val;
377      continue;
378    }
379
380    assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
381                                "its CopyToReg node was created.");
382    unsigned SrcReg = ValueMap[V];
383    if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
384      DestLOI.IsValid = false;
385      return;
386    }
387    const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
388    if (!SrcLOI) {
389      DestLOI.IsValid = false;
390      return;
391    }
392    DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
393    DestLOI.KnownZero &= SrcLOI->KnownZero;
394    DestLOI.KnownOne &= SrcLOI->KnownOne;
395  }
396}
397
398/// setArgumentFrameIndex - Record frame index for the byval
399/// argument. This overrides previous frame index entry for this argument,
400/// if any.
401void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
402                                                 int FI) {
403  ByValArgFrameIndexMap[A] = FI;
404}
405
406/// getArgumentFrameIndex - Get frame index for the byval argument.
407/// If the argument does not have any assigned frame index then 0 is
408/// returned.
409int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
410  DenseMap<const Argument *, int>::iterator I =
411    ByValArgFrameIndexMap.find(A);
412  if (I != ByValArgFrameIndexMap.end())
413    return I->second;
414  DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
415  return 0;
416}
417
418/// ComputeUsesVAFloatArgument - Determine if any floating-point values are
419/// being passed to this variadic function, and set the MachineModuleInfo's
420/// usesVAFloatArgument flag if so. This flag is used to emit an undefined
421/// reference to _fltused on Windows, which will link in MSVCRT's
422/// floating-point support.
423void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
424                                      MachineModuleInfo *MMI)
425{
426  FunctionType *FT = cast<FunctionType>(
427    I.getCalledValue()->getType()->getContainedType(0));
428  if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
429    for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
430      Type* T = I.getArgOperand(i)->getType();
431      for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
432           i != e; ++i) {
433        if (i->isFloatingPointTy()) {
434          MMI->setUsesVAFloatArgument(true);
435          return;
436        }
437      }
438    }
439  }
440}
441
442/// AddCatchInfo - Extract the personality and type infos from an eh.selector
443/// call, and add them to the specified machine basic block.
444void llvm::AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI,
445                        MachineBasicBlock *MBB) {
446  // Inform the MachineModuleInfo of the personality for this landing pad.
447  const ConstantExpr *CE = cast<ConstantExpr>(I.getArgOperand(1));
448  assert(CE->getOpcode() == Instruction::BitCast &&
449         isa<Function>(CE->getOperand(0)) &&
450         "Personality should be a function");
451  MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
452
453  // Gather all the type infos for this landing pad and pass them along to
454  // MachineModuleInfo.
455  std::vector<const GlobalVariable *> TyInfo;
456  unsigned N = I.getNumArgOperands();
457
458  for (unsigned i = N - 1; i > 1; --i) {
459    if (const ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(i))) {
460      unsigned FilterLength = CI->getZExtValue();
461      unsigned FirstCatch = i + FilterLength + !FilterLength;
462      assert(FirstCatch <= N && "Invalid filter length");
463
464      if (FirstCatch < N) {
465        TyInfo.reserve(N - FirstCatch);
466        for (unsigned j = FirstCatch; j < N; ++j)
467          TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
468        MMI->addCatchTypeInfo(MBB, TyInfo);
469        TyInfo.clear();
470      }
471
472      if (!FilterLength) {
473        // Cleanup.
474        MMI->addCleanup(MBB);
475      } else {
476        // Filter.
477        TyInfo.reserve(FilterLength - 1);
478        for (unsigned j = i + 1; j < FirstCatch; ++j)
479          TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
480        MMI->addFilterTypeInfo(MBB, TyInfo);
481        TyInfo.clear();
482      }
483
484      N = i;
485    }
486  }
487
488  if (N > 2) {
489    TyInfo.reserve(N - 2);
490    for (unsigned j = 2; j < N; ++j)
491      TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
492    MMI->addCatchTypeInfo(MBB, TyInfo);
493  }
494}
495
496/// AddLandingPadInfo - Extract the exception handling information from the
497/// landingpad instruction and add them to the specified machine module info.
498void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
499                             MachineBasicBlock *MBB) {
500  MMI.addPersonality(MBB,
501                     cast<Function>(I.getPersonalityFn()->stripPointerCasts()));
502
503  if (I.isCleanup())
504    MMI.addCleanup(MBB);
505
506  // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
507  //        but we need to do it this way because of how the DWARF EH emitter
508  //        processes the clauses.
509  for (unsigned i = I.getNumClauses(); i != 0; --i) {
510    Value *Val = I.getClause(i - 1);
511    if (I.isCatch(i - 1)) {
512      MMI.addCatchTypeInfo(MBB,
513                           dyn_cast<GlobalVariable>(Val->stripPointerCasts()));
514    } else {
515      // Add filters in a list.
516      Constant *CVal = cast<Constant>(Val);
517      SmallVector<const GlobalVariable*, 4> FilterList;
518      for (User::op_iterator
519             II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
520        FilterList.push_back(cast<GlobalVariable>((*II)->stripPointerCasts()));
521
522      MMI.addFilterTypeInfo(MBB, FilterList);
523    }
524  }
525}
526