InstrEmitter.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the Emit routines for the SelectionDAG class, which creates 11// MachineInstrs based on the decisions of the SelectionDAG instruction 12// selection. 13// 14//===----------------------------------------------------------------------===// 15 16#include "InstrEmitter.h" 17#include "SDNodeDbgValue.h" 18#include "llvm/ADT/Statistic.h" 19#include "llvm/CodeGen/MachineConstantPool.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/StackMaps.h" 24#include "llvm/IR/DataLayout.h" 25#include "llvm/Support/Debug.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Support/MathExtras.h" 28#include "llvm/Target/TargetInstrInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31using namespace llvm; 32 33#define DEBUG_TYPE "instr-emitter" 34 35/// MinRCSize - Smallest register class we allow when constraining virtual 36/// registers. If satisfying all register class constraints would require 37/// using a smaller register class, emit a COPY to a new virtual register 38/// instead. 39const unsigned MinRCSize = 4; 40 41/// CountResults - The results of target nodes have register or immediate 42/// operands first, then an optional chain, and optional glue operands (which do 43/// not go into the resulting MachineInstr). 44unsigned InstrEmitter::CountResults(SDNode *Node) { 45 unsigned N = Node->getNumValues(); 46 while (N && Node->getValueType(N - 1) == MVT::Glue) 47 --N; 48 if (N && Node->getValueType(N - 1) == MVT::Other) 49 --N; // Skip over chain result. 50 return N; 51} 52 53/// countOperands - The inputs to target nodes have any actual inputs first, 54/// followed by an optional chain operand, then an optional glue operand. 55/// Compute the number of actual operands that will go into the resulting 56/// MachineInstr. 57/// 58/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding 59/// the chain and glue. These operands may be implicit on the machine instr. 60static unsigned countOperands(SDNode *Node, unsigned NumExpUses, 61 unsigned &NumImpUses) { 62 unsigned N = Node->getNumOperands(); 63 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 64 --N; 65 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 66 --N; // Ignore chain if it exists. 67 68 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses. 69 NumImpUses = N - NumExpUses; 70 for (unsigned I = N; I > NumExpUses; --I) { 71 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1))) 72 continue; 73 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1))) 74 if (TargetRegisterInfo::isPhysicalRegister(RN->getReg())) 75 continue; 76 NumImpUses = N - I; 77 break; 78 } 79 80 return N; 81} 82 83/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 84/// implicit physical register output. 85void InstrEmitter:: 86EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 87 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 88 unsigned VRBase = 0; 89 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 90 // Just use the input register directly! 91 SDValue Op(Node, ResNo); 92 if (IsClone) 93 VRBaseMap.erase(Op); 94 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 95 (void)isNew; // Silence compiler warning. 96 assert(isNew && "Node emitted out of order - early"); 97 return; 98 } 99 100 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 101 // the CopyToReg'd destination register instead of creating a new vreg. 102 bool MatchReg = true; 103 const TargetRegisterClass *UseRC = nullptr; 104 MVT VT = Node->getSimpleValueType(ResNo); 105 106 // Stick to the preferred register classes for legal types. 107 if (TLI->isTypeLegal(VT)) 108 UseRC = TLI->getRegClassFor(VT); 109 110 if (!IsClone && !IsCloned) 111 for (SDNode *User : Node->uses()) { 112 bool Match = true; 113 if (User->getOpcode() == ISD::CopyToReg && 114 User->getOperand(2).getNode() == Node && 115 User->getOperand(2).getResNo() == ResNo) { 116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 117 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 118 VRBase = DestReg; 119 Match = false; 120 } else if (DestReg != SrcReg) 121 Match = false; 122 } else { 123 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 124 SDValue Op = User->getOperand(i); 125 if (Op.getNode() != Node || Op.getResNo() != ResNo) 126 continue; 127 MVT VT = Node->getSimpleValueType(Op.getResNo()); 128 if (VT == MVT::Other || VT == MVT::Glue) 129 continue; 130 Match = false; 131 if (User->isMachineOpcode()) { 132 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); 133 const TargetRegisterClass *RC = nullptr; 134 if (i+II.getNumDefs() < II.getNumOperands()) { 135 RC = TRI->getAllocatableClass( 136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 137 } 138 if (!UseRC) 139 UseRC = RC; 140 else if (RC) { 141 const TargetRegisterClass *ComRC = 142 TRI->getCommonSubClass(UseRC, RC); 143 // If multiple uses expect disjoint register classes, we emit 144 // copies in AddRegisterOperand. 145 if (ComRC) 146 UseRC = ComRC; 147 } 148 } 149 } 150 } 151 MatchReg &= Match; 152 if (VRBase) 153 break; 154 } 155 156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; 157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 158 159 // Figure out the register class to create for the destreg. 160 if (VRBase) { 161 DstRC = MRI->getRegClass(VRBase); 162 } else if (UseRC) { 163 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 164 DstRC = UseRC; 165 } else { 166 DstRC = TLI->getRegClassFor(VT); 167 } 168 169 // If all uses are reading from the src physical register and copying the 170 // register is either impossible or very expensive, then don't create a copy. 171 if (MatchReg && SrcRC->getCopyCost() < 0) { 172 VRBase = SrcReg; 173 } else { 174 // Create the reg, emit the copy. 175 VRBase = MRI->createVirtualRegister(DstRC); 176 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 177 VRBase).addReg(SrcReg); 178 } 179 180 SDValue Op(Node, ResNo); 181 if (IsClone) 182 VRBaseMap.erase(Op); 183 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 184 (void)isNew; // Silence compiler warning. 185 assert(isNew && "Node emitted out of order - early"); 186} 187 188/// getDstOfCopyToRegUse - If the only use of the specified result number of 189/// node is a CopyToReg, return its destination register. Return 0 otherwise. 190unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 191 unsigned ResNo) const { 192 if (!Node->hasOneUse()) 193 return 0; 194 195 SDNode *User = *Node->use_begin(); 196 if (User->getOpcode() == ISD::CopyToReg && 197 User->getOperand(2).getNode() == Node && 198 User->getOperand(2).getResNo() == ResNo) { 199 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 200 if (TargetRegisterInfo::isVirtualRegister(Reg)) 201 return Reg; 202 } 203 return 0; 204} 205 206void InstrEmitter::CreateVirtualRegisters(SDNode *Node, 207 MachineInstrBuilder &MIB, 208 const MCInstrDesc &II, 209 bool IsClone, bool IsCloned, 210 DenseMap<SDValue, unsigned> &VRBaseMap) { 211 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 212 "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 213 214 unsigned NumResults = CountResults(Node); 215 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 216 // If the specific node value is only used by a CopyToReg and the dest reg 217 // is a vreg in the same register class, use the CopyToReg'd destination 218 // register instead of creating a new vreg. 219 unsigned VRBase = 0; 220 const TargetRegisterClass *RC = 221 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 222 // Always let the value type influence the used register class. The 223 // constraints on the instruction may be too lax to represent the value 224 // type correctly. For example, a 64-bit float (X86::FR64) can't live in 225 // the 32-bit float super-class (X86::FR32). 226 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { 227 const TargetRegisterClass *VTRC = 228 TLI->getRegClassFor(Node->getSimpleValueType(i)); 229 if (RC) 230 VTRC = TRI->getCommonSubClass(RC, VTRC); 231 if (VTRC) 232 RC = VTRC; 233 } 234 235 if (II.OpInfo[i].isOptionalDef()) { 236 // Optional def must be a physical register. 237 unsigned NumResults = CountResults(Node); 238 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 239 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 240 MIB.addReg(VRBase, RegState::Define); 241 } 242 243 if (!VRBase && !IsClone && !IsCloned) 244 for (SDNode *User : Node->uses()) { 245 if (User->getOpcode() == ISD::CopyToReg && 246 User->getOperand(2).getNode() == Node && 247 User->getOperand(2).getResNo() == i) { 248 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 249 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 250 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 251 if (RegRC == RC) { 252 VRBase = Reg; 253 MIB.addReg(VRBase, RegState::Define); 254 break; 255 } 256 } 257 } 258 } 259 260 // Create the result registers for this node and add the result regs to 261 // the machine instruction. 262 if (VRBase == 0) { 263 assert(RC && "Isn't a register operand!"); 264 VRBase = MRI->createVirtualRegister(RC); 265 MIB.addReg(VRBase, RegState::Define); 266 } 267 268 SDValue Op(Node, i); 269 if (IsClone) 270 VRBaseMap.erase(Op); 271 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 272 (void)isNew; // Silence compiler warning. 273 assert(isNew && "Node emitted out of order - early"); 274 } 275} 276 277/// getVR - Return the virtual register corresponding to the specified result 278/// of the specified node. 279unsigned InstrEmitter::getVR(SDValue Op, 280 DenseMap<SDValue, unsigned> &VRBaseMap) { 281 if (Op.isMachineOpcode() && 282 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 283 // Add an IMPLICIT_DEF instruction before every use. 284 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 285 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc 286 // does not include operand register class info. 287 if (!VReg) { 288 const TargetRegisterClass *RC = 289 TLI->getRegClassFor(Op.getSimpleValueType()); 290 VReg = MRI->createVirtualRegister(RC); 291 } 292 BuildMI(*MBB, InsertPos, Op.getDebugLoc(), 293 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 294 return VReg; 295 } 296 297 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 298 assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 299 return I->second; 300} 301 302 303/// AddRegisterOperand - Add the specified register as an operand to the 304/// specified machine instr. Insert register copies if the register is 305/// not in the required register class. 306void 307InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, 308 SDValue Op, 309 unsigned IIOpNum, 310 const MCInstrDesc *II, 311 DenseMap<SDValue, unsigned> &VRBaseMap, 312 bool IsDebug, bool IsClone, bool IsCloned) { 313 assert(Op.getValueType() != MVT::Other && 314 Op.getValueType() != MVT::Glue && 315 "Chain and glue operands should occur at end of operand list!"); 316 // Get/emit the operand. 317 unsigned VReg = getVR(Op, VRBaseMap); 318 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 319 320 const MCInstrDesc &MCID = MIB->getDesc(); 321 bool isOptDef = IIOpNum < MCID.getNumOperands() && 322 MCID.OpInfo[IIOpNum].isOptionalDef(); 323 324 // If the instruction requires a register in a different class, create 325 // a new virtual register and copy the value into it, but first attempt to 326 // shrink VReg's register class within reason. For example, if VReg == GR32 327 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. 328 if (II) { 329 const TargetRegisterClass *DstRC = nullptr; 330 if (IIOpNum < II->getNumOperands()) 331 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 332 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { 333 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 334 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), 335 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 336 VReg = NewVReg; 337 } 338 } 339 340 // If this value has only one use, that use is a kill. This is a 341 // conservative approximation. InstrEmitter does trivial coalescing 342 // with CopyFromReg nodes, so don't emit kill flags for them. 343 // Avoid kill flags on Schedule cloned nodes, since there will be 344 // multiple uses. 345 // Tied operands are never killed, so we need to check that. And that 346 // means we need to determine the index of the operand. 347 bool isKill = Op.hasOneUse() && 348 Op.getNode()->getOpcode() != ISD::CopyFromReg && 349 !IsDebug && 350 !(IsClone || IsCloned); 351 if (isKill) { 352 unsigned Idx = MIB->getNumOperands(); 353 while (Idx > 0 && 354 MIB->getOperand(Idx-1).isReg() && 355 MIB->getOperand(Idx-1).isImplicit()) 356 --Idx; 357 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; 358 if (isTied) 359 isKill = false; 360 } 361 362 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | 363 getDebugRegState(IsDebug)); 364} 365 366/// AddOperand - Add the specified operand to the specified machine instr. II 367/// specifies the instruction information for the node, and IIOpNum is the 368/// operand number (in the II) that we are adding. 369void InstrEmitter::AddOperand(MachineInstrBuilder &MIB, 370 SDValue Op, 371 unsigned IIOpNum, 372 const MCInstrDesc *II, 373 DenseMap<SDValue, unsigned> &VRBaseMap, 374 bool IsDebug, bool IsClone, bool IsCloned) { 375 if (Op.isMachineOpcode()) { 376 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, 377 IsDebug, IsClone, IsCloned); 378 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 379 MIB.addImm(C->getSExtValue()); 380 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 381 MIB.addFPImm(F->getConstantFPValue()); 382 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 383 // Turn additional physreg operands into implicit uses on non-variadic 384 // instructions. This is used by call and return instructions passing 385 // arguments in registers. 386 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic()); 387 MIB.addReg(R->getReg(), getImplRegState(Imp)); 388 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) { 389 MIB.addRegMask(RM->getRegMask()); 390 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 391 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(), 392 TGA->getTargetFlags()); 393 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 394 MIB.addMBB(BBNode->getBasicBlock()); 395 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 396 MIB.addFrameIndex(FI->getIndex()); 397 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 398 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags()); 399 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 400 int Offset = CP->getOffset(); 401 unsigned Align = CP->getAlignment(); 402 Type *Type = CP->getType(); 403 // MachineConstantPool wants an explicit alignment. 404 if (Align == 0) { 405 Align = TM->getDataLayout()->getPrefTypeAlignment(Type); 406 if (Align == 0) { 407 // Alignment of vector types. FIXME! 408 Align = TM->getDataLayout()->getTypeAllocSize(Type); 409 } 410 } 411 412 unsigned Idx; 413 MachineConstantPool *MCP = MF->getConstantPool(); 414 if (CP->isMachineConstantPoolEntry()) 415 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 416 else 417 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 418 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags()); 419 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 420 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags()); 421 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 422 MIB.addBlockAddress(BA->getBlockAddress(), 423 BA->getOffset(), 424 BA->getTargetFlags()); 425 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) { 426 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags()); 427 } else { 428 assert(Op.getValueType() != MVT::Other && 429 Op.getValueType() != MVT::Glue && 430 "Chain and glue operands should occur at end of operand list!"); 431 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, 432 IsDebug, IsClone, IsCloned); 433 } 434} 435 436unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, 437 MVT VT, DebugLoc DL) { 438 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); 439 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); 440 441 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg 442 // within reason. 443 if (RC && RC != VRC) 444 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); 445 446 // VReg has been adjusted. It can be used with SubIdx operands now. 447 if (RC) 448 return VReg; 449 450 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual 451 // register instead. 452 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); 453 assert(RC && "No legal register class for VT supports that SubIdx"); 454 unsigned NewReg = MRI->createVirtualRegister(RC); 455 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) 456 .addReg(VReg); 457 return NewReg; 458} 459 460/// EmitSubregNode - Generate machine code for subreg nodes. 461/// 462void InstrEmitter::EmitSubregNode(SDNode *Node, 463 DenseMap<SDValue, unsigned> &VRBaseMap, 464 bool IsClone, bool IsCloned) { 465 unsigned VRBase = 0; 466 unsigned Opc = Node->getMachineOpcode(); 467 468 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 469 // the CopyToReg'd destination register instead of creating a new vreg. 470 for (SDNode *User : Node->uses()) { 471 if (User->getOpcode() == ISD::CopyToReg && 472 User->getOperand(2).getNode() == Node) { 473 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 474 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 475 VRBase = DestReg; 476 break; 477 } 478 } 479 } 480 481 if (Opc == TargetOpcode::EXTRACT_SUBREG) { 482 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no 483 // constraints on the %dst register, COPY can target all legal register 484 // classes. 485 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 486 const TargetRegisterClass *TRC = 487 TLI->getRegClassFor(Node->getSimpleValueType(0)); 488 489 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 490 MachineInstr *DefMI = MRI->getVRegDef(VReg); 491 unsigned SrcReg, DstReg, DefSubIdx; 492 if (DefMI && 493 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 494 SubIdx == DefSubIdx && 495 TRC == MRI->getRegClass(SrcReg)) { 496 // Optimize these: 497 // r1025 = s/zext r1024, 4 498 // r1026 = extract_subreg r1025, 4 499 // to a copy 500 // r1026 = copy r1024 501 VRBase = MRI->createVirtualRegister(TRC); 502 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 503 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); 504 MRI->clearKillFlags(SrcReg); 505 } else { 506 // VReg may not support a SubIdx sub-register, and we may need to 507 // constrain its register class or issue a COPY to a compatible register 508 // class. 509 VReg = ConstrainForSubReg(VReg, SubIdx, 510 Node->getOperand(0).getSimpleValueType(), 511 Node->getDebugLoc()); 512 513 // Create the destreg if it is missing. 514 if (VRBase == 0) 515 VRBase = MRI->createVirtualRegister(TRC); 516 517 // Create the extract_subreg machine instruction. 518 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 519 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); 520 } 521 } else if (Opc == TargetOpcode::INSERT_SUBREG || 522 Opc == TargetOpcode::SUBREG_TO_REG) { 523 SDValue N0 = Node->getOperand(0); 524 SDValue N1 = Node->getOperand(1); 525 SDValue N2 = Node->getOperand(2); 526 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 527 528 // Figure out the register class to create for the destreg. It should be 529 // the largest legal register class supporting SubIdx sub-registers. 530 // RegisterCoalescer will constrain it further if it decides to eliminate 531 // the INSERT_SUBREG instruction. 532 // 533 // %dst = INSERT_SUBREG %src, %sub, SubIdx 534 // 535 // is lowered by TwoAddressInstructionPass to: 536 // 537 // %dst = COPY %src 538 // %dst:SubIdx = COPY %sub 539 // 540 // There is no constraint on the %src register class. 541 // 542 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0)); 543 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); 544 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"); 545 546 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) 547 VRBase = MRI->createVirtualRegister(SRC); 548 549 // Create the insert_subreg or subreg_to_reg machine instruction. 550 MachineInstrBuilder MIB = 551 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase); 552 553 // If creating a subreg_to_reg, then the first input operand 554 // is an implicit value immediate, otherwise it's a register 555 if (Opc == TargetOpcode::SUBREG_TO_REG) { 556 const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 557 MIB.addImm(SD->getZExtValue()); 558 } else 559 AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false, 560 IsClone, IsCloned); 561 // Add the subregster being inserted 562 AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false, 563 IsClone, IsCloned); 564 MIB.addImm(SubIdx); 565 MBB->insert(InsertPos, MIB); 566 } else 567 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 568 569 SDValue Op(Node, 0); 570 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 571 (void)isNew; // Silence compiler warning. 572 assert(isNew && "Node emitted out of order - early"); 573} 574 575/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 576/// COPY_TO_REGCLASS is just a normal copy, except that the destination 577/// register is constrained to be in a particular register class. 578/// 579void 580InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 581 DenseMap<SDValue, unsigned> &VRBaseMap) { 582 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 583 584 // Create the new VReg in the destination class and emit a copy. 585 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 586 const TargetRegisterClass *DstRC = 587 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); 588 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 589 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 590 NewVReg).addReg(VReg); 591 592 SDValue Op(Node, 0); 593 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 594 (void)isNew; // Silence compiler warning. 595 assert(isNew && "Node emitted out of order - early"); 596} 597 598/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 599/// 600void InstrEmitter::EmitRegSequence(SDNode *Node, 601 DenseMap<SDValue, unsigned> &VRBaseMap, 602 bool IsClone, bool IsCloned) { 603 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue(); 604 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); 605 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC)); 606 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 607 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg); 608 unsigned NumOps = Node->getNumOperands(); 609 assert((NumOps & 1) == 1 && 610 "REG_SEQUENCE must have an odd number of operands!"); 611 for (unsigned i = 1; i != NumOps; ++i) { 612 SDValue Op = Node->getOperand(i); 613 if ((i & 1) == 0) { 614 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1)); 615 // Skip physical registers as they don't have a vreg to get and we'll 616 // insert copies for them in TwoAddressInstructionPass anyway. 617 if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 618 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 619 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 620 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 621 const TargetRegisterClass *SRC = 622 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); 623 if (SRC && SRC != RC) { 624 MRI->setRegClass(NewVReg, SRC); 625 RC = SRC; 626 } 627 } 628 } 629 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, 630 IsClone, IsCloned); 631 } 632 633 MBB->insert(InsertPos, MIB); 634 SDValue Op(Node, 0); 635 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 636 (void)isNew; // Silence compiler warning. 637 assert(isNew && "Node emitted out of order - early"); 638} 639 640/// EmitDbgValue - Generate machine instruction for a dbg_value node. 641/// 642MachineInstr * 643InstrEmitter::EmitDbgValue(SDDbgValue *SD, 644 DenseMap<SDValue, unsigned> &VRBaseMap) { 645 uint64_t Offset = SD->getOffset(); 646 MDNode* MDPtr = SD->getMDPtr(); 647 DebugLoc DL = SD->getDebugLoc(); 648 649 if (SD->getKind() == SDDbgValue::FRAMEIX) { 650 // Stack address; this needs to be lowered in target-dependent fashion. 651 // EmitTargetCodeForFrameDebugValue is responsible for allocation. 652 return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE)) 653 .addFrameIndex(SD->getFrameIx()).addImm(Offset).addMetadata(MDPtr); 654 } 655 // Otherwise, we're going to create an instruction here. 656 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 657 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 658 if (SD->getKind() == SDDbgValue::SDNODE) { 659 SDNode *Node = SD->getSDNode(); 660 SDValue Op = SDValue(Node, SD->getResNo()); 661 // It's possible we replaced this SDNode with other(s) and therefore 662 // didn't generate code for it. It's better to catch these cases where 663 // they happen and transfer the debug info, but trying to guarantee that 664 // in all cases would be very fragile; this is a safeguard for any 665 // that were missed. 666 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 667 if (I==VRBaseMap.end()) 668 MIB.addReg(0U); // undef 669 else 670 AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 671 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false); 672 } else if (SD->getKind() == SDDbgValue::CONST) { 673 const Value *V = SD->getConst(); 674 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 675 if (CI->getBitWidth() > 64) 676 MIB.addCImm(CI); 677 else 678 MIB.addImm(CI->getSExtValue()); 679 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 680 MIB.addFPImm(CF); 681 } else { 682 // Could be an Undef. In any case insert an Undef so we can see what we 683 // dropped. 684 MIB.addReg(0U); 685 } 686 } else { 687 // Insert an Undef so we can see what we dropped. 688 MIB.addReg(0U); 689 } 690 691 // Indirect addressing is indicated by an Imm as the second parameter. 692 if (SD->isIndirect()) 693 MIB.addImm(Offset); 694 else { 695 assert(Offset == 0 && "direct value cannot have an offset"); 696 MIB.addReg(0U, RegState::Debug); 697 } 698 699 MIB.addMetadata(MDPtr); 700 701 return &*MIB; 702} 703 704/// EmitMachineNode - Generate machine code for a target-specific node and 705/// needed dependencies. 706/// 707void InstrEmitter:: 708EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 709 DenseMap<SDValue, unsigned> &VRBaseMap) { 710 unsigned Opc = Node->getMachineOpcode(); 711 712 // Handle subreg insert/extract specially 713 if (Opc == TargetOpcode::EXTRACT_SUBREG || 714 Opc == TargetOpcode::INSERT_SUBREG || 715 Opc == TargetOpcode::SUBREG_TO_REG) { 716 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned); 717 return; 718 } 719 720 // Handle COPY_TO_REGCLASS specially. 721 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 722 EmitCopyToRegClassNode(Node, VRBaseMap); 723 return; 724 } 725 726 // Handle REG_SEQUENCE specially. 727 if (Opc == TargetOpcode::REG_SEQUENCE) { 728 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned); 729 return; 730 } 731 732 if (Opc == TargetOpcode::IMPLICIT_DEF) 733 // We want a unique VR for each IMPLICIT_DEF use. 734 return; 735 736 const MCInstrDesc &II = TII->get(Opc); 737 unsigned NumResults = CountResults(Node); 738 unsigned NumDefs = II.getNumDefs(); 739 const MCPhysReg *ScratchRegs = nullptr; 740 741 // Handle STACKMAP and PATCHPOINT specially and then use the generic code. 742 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) { 743 // Stackmaps do not have arguments and do not preserve their calling 744 // convention. However, to simplify runtime support, they clobber the same 745 // scratch registers as AnyRegCC. 746 unsigned CC = CallingConv::AnyReg; 747 if (Opc == TargetOpcode::PATCHPOINT) { 748 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos); 749 NumDefs = NumResults; 750 } 751 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC); 752 } 753 754 unsigned NumImpUses = 0; 755 unsigned NodeOperands = 756 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses); 757 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr; 758#ifndef NDEBUG 759 unsigned NumMIOperands = NodeOperands + NumResults; 760 if (II.isVariadic()) 761 assert(NumMIOperands >= II.getNumOperands() && 762 "Too few operands for a variadic node!"); 763 else 764 assert(NumMIOperands >= II.getNumOperands() && 765 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + 766 NumImpUses && 767 "#operands for dag node doesn't match .td file!"); 768#endif 769 770 // Create the new machine instruction. 771 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II); 772 773 // Add result register values for things that are defined by this 774 // instruction. 775 if (NumResults) 776 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap); 777 778 // Emit all of the actual operands of this instruction, adding them to the 779 // instruction as appropriate. 780 bool HasOptPRefs = NumDefs > NumResults; 781 assert((!HasOptPRefs || !HasPhysRegOuts) && 782 "Unable to cope with optional defs and phys regs defs!"); 783 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0; 784 for (unsigned i = NumSkip; i != NodeOperands; ++i) 785 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II, 786 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned); 787 788 // Add scratch registers as implicit def and early clobber 789 if (ScratchRegs) 790 for (unsigned i = 0; ScratchRegs[i]; ++i) 791 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | 792 RegState::EarlyClobber); 793 794 // Transfer all of the memory reference descriptions of this instruction. 795 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 796 cast<MachineSDNode>(Node)->memoperands_end()); 797 798 // Insert the instruction into position in the block. This needs to 799 // happen before any custom inserter hook is called so that the 800 // hook knows where in the block to insert the replacement code. 801 MBB->insert(InsertPos, MIB); 802 803 // The MachineInstr may also define physregs instead of virtregs. These 804 // physreg values can reach other instructions in different ways: 805 // 806 // 1. When there is a use of a Node value beyond the explicitly defined 807 // virtual registers, we emit a CopyFromReg for one of the implicitly 808 // defined physregs. This only happens when HasPhysRegOuts is true. 809 // 810 // 2. A CopyFromReg reading a physreg may be glued to this instruction. 811 // 812 // 3. A glued instruction may implicitly use a physreg. 813 // 814 // 4. A glued instruction may use a RegisterSDNode operand. 815 // 816 // Collect all the used physreg defs, and make sure that any unused physreg 817 // defs are marked as dead. 818 SmallVector<unsigned, 8> UsedRegs; 819 820 // Additional results must be physical register defs. 821 if (HasPhysRegOuts) { 822 for (unsigned i = NumDefs; i < NumResults; ++i) { 823 unsigned Reg = II.getImplicitDefs()[i - NumDefs]; 824 if (!Node->hasAnyUseOfValue(i)) 825 continue; 826 // This implicitly defined physreg has a use. 827 UsedRegs.push_back(Reg); 828 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 829 } 830 } 831 832 // Scan the glue chain for any used physregs. 833 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) { 834 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) { 835 if (F->getOpcode() == ISD::CopyFromReg) { 836 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); 837 continue; 838 } else if (F->getOpcode() == ISD::CopyToReg) { 839 // Skip CopyToReg nodes that are internal to the glue chain. 840 continue; 841 } 842 // Collect declared implicit uses. 843 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); 844 UsedRegs.append(MCID.getImplicitUses(), 845 MCID.getImplicitUses() + MCID.getNumImplicitUses()); 846 // In addition to declared implicit uses, we must also check for 847 // direct RegisterSDNode operands. 848 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i) 849 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) { 850 unsigned Reg = R->getReg(); 851 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 852 UsedRegs.push_back(Reg); 853 } 854 } 855 } 856 857 // Finally mark unused registers as dead. 858 if (!UsedRegs.empty() || II.getImplicitDefs()) 859 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI); 860 861 // Run post-isel target hook to adjust this instruction if needed. 862#ifdef NDEBUG 863 if (II.hasPostISelHook()) 864#endif 865 TLI->AdjustInstrPostInstrSelection(MIB, Node); 866} 867 868/// EmitSpecialNode - Generate machine code for a target-independent node and 869/// needed dependencies. 870void InstrEmitter:: 871EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 872 DenseMap<SDValue, unsigned> &VRBaseMap) { 873 switch (Node->getOpcode()) { 874 default: 875#ifndef NDEBUG 876 Node->dump(); 877#endif 878 llvm_unreachable("This target-independent node should have been selected!"); 879 case ISD::EntryToken: 880 llvm_unreachable("EntryToken should have been excluded from the schedule!"); 881 case ISD::MERGE_VALUES: 882 case ISD::TokenFactor: // fall thru 883 break; 884 case ISD::CopyToReg: { 885 unsigned SrcReg; 886 SDValue SrcVal = Node->getOperand(2); 887 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 888 SrcReg = R->getReg(); 889 else 890 SrcReg = getVR(SrcVal, VRBaseMap); 891 892 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 893 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 894 break; 895 896 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 897 DestReg).addReg(SrcReg); 898 break; 899 } 900 case ISD::CopyFromReg: { 901 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 902 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 903 break; 904 } 905 case ISD::EH_LABEL: { 906 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 907 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 908 TII->get(TargetOpcode::EH_LABEL)).addSym(S); 909 break; 910 } 911 912 case ISD::LIFETIME_START: 913 case ISD::LIFETIME_END: { 914 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ? 915 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END; 916 917 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1)); 918 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp)) 919 .addFrameIndex(FI->getIndex()); 920 break; 921 } 922 923 case ISD::INLINEASM: { 924 unsigned NumOps = Node->getNumOperands(); 925 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 926 --NumOps; // Ignore the glue operand. 927 928 // Create the inline asm machine instruction. 929 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), 930 TII->get(TargetOpcode::INLINEASM)); 931 932 // Add the asm string as an external symbol operand. 933 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 934 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 935 MIB.addExternalSymbol(AsmStr); 936 937 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore 938 // bits. 939 int64_t ExtraInfo = 940 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))-> 941 getZExtValue(); 942 MIB.addImm(ExtraInfo); 943 944 // Remember to operand index of the group flags. 945 SmallVector<unsigned, 8> GroupIdx; 946 947 // Add all of the operand registers to the instruction. 948 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 949 unsigned Flags = 950 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 951 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 952 953 GroupIdx.push_back(MIB->getNumOperands()); 954 MIB.addImm(Flags); 955 ++i; // Skip the ID value. 956 957 switch (InlineAsm::getKind(Flags)) { 958 default: llvm_unreachable("Bad flags!"); 959 case InlineAsm::Kind_RegDef: 960 for (unsigned j = 0; j != NumVals; ++j, ++i) { 961 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 962 // FIXME: Add dead flags for physical and virtual registers defined. 963 // For now, mark physical register defs as implicit to help fast 964 // regalloc. This makes inline asm look a lot like calls. 965 MIB.addReg(Reg, RegState::Define | 966 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg))); 967 } 968 break; 969 case InlineAsm::Kind_RegDefEarlyClobber: 970 case InlineAsm::Kind_Clobber: 971 for (unsigned j = 0; j != NumVals; ++j, ++i) { 972 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 973 MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber | 974 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg))); 975 } 976 break; 977 case InlineAsm::Kind_RegUse: // Use of register. 978 case InlineAsm::Kind_Imm: // Immediate. 979 case InlineAsm::Kind_Mem: // Addressing mode. 980 // The addressing mode has been selected, just add all of the 981 // operands to the machine instruction. 982 for (unsigned j = 0; j != NumVals; ++j, ++i) 983 AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap, 984 /*IsDebug=*/false, IsClone, IsCloned); 985 986 // Manually set isTied bits. 987 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) { 988 unsigned DefGroup = 0; 989 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) { 990 unsigned DefIdx = GroupIdx[DefGroup] + 1; 991 unsigned UseIdx = GroupIdx.back() + 1; 992 for (unsigned j = 0; j != NumVals; ++j) 993 MIB->tieOperands(DefIdx + j, UseIdx + j); 994 } 995 } 996 break; 997 } 998 } 999 1000 // Get the mdnode from the asm if it exists and add it to the instruction. 1001 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 1002 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 1003 if (MD) 1004 MIB.addMetadata(MD); 1005 1006 MBB->insert(InsertPos, MIB); 1007 break; 1008 } 1009 } 1010} 1011 1012/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 1013/// at the given position in the given block. 1014InstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 1015 MachineBasicBlock::iterator insertpos) 1016 : MF(mbb->getParent()), 1017 MRI(&MF->getRegInfo()), 1018 TM(&MF->getTarget()), 1019 TII(TM->getInstrInfo()), 1020 TRI(TM->getRegisterInfo()), 1021 TLI(TM->getTargetLowering()), 1022 MBB(mbb), InsertPos(insertpos) { 1023} 1024