1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements routines for translating from LLVM IR into SelectionDAG IR.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SelectionDAGBuilder.h"
15#include "SDNodeDbgValue.h"
16#include "llvm/ADT/BitVector.h"
17#include "llvm/ADT/Optional.h"
18#include "llvm/ADT/SmallSet.h"
19#include "llvm/Analysis/AliasAnalysis.h"
20#include "llvm/Analysis/BranchProbabilityInfo.h"
21#include "llvm/Analysis/ConstantFolding.h"
22#include "llvm/Analysis/ValueTracking.h"
23#include "llvm/CodeGen/Analysis.h"
24#include "llvm/CodeGen/FastISel.h"
25#include "llvm/CodeGen/FunctionLoweringInfo.h"
26#include "llvm/CodeGen/GCMetadata.h"
27#include "llvm/CodeGen/GCStrategy.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/MachineRegisterInfo.h"
34#include "llvm/CodeGen/SelectionDAG.h"
35#include "llvm/CodeGen/StackMaps.h"
36#include "llvm/IR/CallingConv.h"
37#include "llvm/IR/Constants.h"
38#include "llvm/IR/DataLayout.h"
39#include "llvm/IR/DebugInfo.h"
40#include "llvm/IR/DerivedTypes.h"
41#include "llvm/IR/Function.h"
42#include "llvm/IR/GlobalVariable.h"
43#include "llvm/IR/InlineAsm.h"
44#include "llvm/IR/Instructions.h"
45#include "llvm/IR/IntrinsicInst.h"
46#include "llvm/IR/Intrinsics.h"
47#include "llvm/IR/LLVMContext.h"
48#include "llvm/IR/Module.h"
49#include "llvm/Support/CommandLine.h"
50#include "llvm/Support/Debug.h"
51#include "llvm/Support/ErrorHandling.h"
52#include "llvm/Support/MathExtras.h"
53#include "llvm/Support/raw_ostream.h"
54#include "llvm/Target/TargetFrameLowering.h"
55#include "llvm/Target/TargetInstrInfo.h"
56#include "llvm/Target/TargetIntrinsicInfo.h"
57#include "llvm/Target/TargetLibraryInfo.h"
58#include "llvm/Target/TargetLowering.h"
59#include "llvm/Target/TargetOptions.h"
60#include "llvm/Target/TargetSelectionDAGInfo.h"
61#include <algorithm>
62using namespace llvm;
63
64#define DEBUG_TYPE "isel"
65
66/// LimitFloatPrecision - Generate low-precision inline sequences for
67/// some float libcalls (6, 8 or 12 bits).
68static unsigned LimitFloatPrecision;
69
70static cl::opt<unsigned, true>
71LimitFPPrecision("limit-float-precision",
72                 cl::desc("Generate low-precision inline sequences "
73                          "for some float libcalls"),
74                 cl::location(LimitFloatPrecision),
75                 cl::init(0));
76
77// Limit the width of DAG chains. This is important in general to prevent
78// prevent DAG-based analysis from blowing up. For example, alias analysis and
79// load clustering may not complete in reasonable time. It is difficult to
80// recognize and avoid this situation within each individual analysis, and
81// future analyses are likely to have the same behavior. Limiting DAG width is
82// the safe approach, and will be especially important with global DAGs.
83//
84// MaxParallelChains default is arbitrarily high to avoid affecting
85// optimization, but could be lowered to improve compile time. Any ld-ld-st-st
86// sequence over this should have been converted to llvm.memcpy by the
87// frontend. It easy to induce this behavior with .ll code such as:
88// %buffer = alloca [4096 x i8]
89// %data = load [4096 x i8]* %argPtr
90// store [4096 x i8] %data, [4096 x i8]* %buffer
91static const unsigned MaxParallelChains = 64;
92
93static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
94                                      const SDValue *Parts, unsigned NumParts,
95                                      MVT PartVT, EVT ValueVT, const Value *V);
96
97/// getCopyFromParts - Create a value that contains the specified legal parts
98/// combined into the value they represent.  If the parts combine to a type
99/// larger then ValueVT then AssertOp can be used to specify whether the extra
100/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
101/// (ISD::AssertSext).
102static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
103                                const SDValue *Parts,
104                                unsigned NumParts, MVT PartVT, EVT ValueVT,
105                                const Value *V,
106                                ISD::NodeType AssertOp = ISD::DELETED_NODE) {
107  if (ValueVT.isVector())
108    return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
109                                  PartVT, ValueVT, V);
110
111  assert(NumParts > 0 && "No parts to assemble!");
112  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
113  SDValue Val = Parts[0];
114
115  if (NumParts > 1) {
116    // Assemble the value from multiple parts.
117    if (ValueVT.isInteger()) {
118      unsigned PartBits = PartVT.getSizeInBits();
119      unsigned ValueBits = ValueVT.getSizeInBits();
120
121      // Assemble the power of 2 part.
122      unsigned RoundParts = NumParts & (NumParts - 1) ?
123        1 << Log2_32(NumParts) : NumParts;
124      unsigned RoundBits = PartBits * RoundParts;
125      EVT RoundVT = RoundBits == ValueBits ?
126        ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
127      SDValue Lo, Hi;
128
129      EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
130
131      if (RoundParts > 2) {
132        Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
133                              PartVT, HalfVT, V);
134        Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
135                              RoundParts / 2, PartVT, HalfVT, V);
136      } else {
137        Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
138        Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
139      }
140
141      if (TLI.isBigEndian())
142        std::swap(Lo, Hi);
143
144      Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
145
146      if (RoundParts < NumParts) {
147        // Assemble the trailing non-power-of-2 part.
148        unsigned OddParts = NumParts - RoundParts;
149        EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
150        Hi = getCopyFromParts(DAG, DL,
151                              Parts + RoundParts, OddParts, PartVT, OddVT, V);
152
153        // Combine the round and odd parts.
154        Lo = Val;
155        if (TLI.isBigEndian())
156          std::swap(Lo, Hi);
157        EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
158        Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
159        Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
160                         DAG.getConstant(Lo.getValueType().getSizeInBits(),
161                                         TLI.getPointerTy()));
162        Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
163        Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
164      }
165    } else if (PartVT.isFloatingPoint()) {
166      // FP split into multiple FP parts (for ppcf128)
167      assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
168             "Unexpected split");
169      SDValue Lo, Hi;
170      Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
171      Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
172      if (TLI.hasBigEndianPartOrdering(ValueVT))
173        std::swap(Lo, Hi);
174      Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
175    } else {
176      // FP split into integer parts (soft fp)
177      assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
178             !PartVT.isVector() && "Unexpected split");
179      EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
180      Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
181    }
182  }
183
184  // There is now one part, held in Val.  Correct it to match ValueVT.
185  EVT PartEVT = Val.getValueType();
186
187  if (PartEVT == ValueVT)
188    return Val;
189
190  if (PartEVT.isInteger() && ValueVT.isInteger()) {
191    if (ValueVT.bitsLT(PartEVT)) {
192      // For a truncate, see if we have any information to
193      // indicate whether the truncated bits will always be
194      // zero or sign-extension.
195      if (AssertOp != ISD::DELETED_NODE)
196        Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
197                          DAG.getValueType(ValueVT));
198      return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
199    }
200    return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
201  }
202
203  if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
204    // FP_ROUND's are always exact here.
205    if (ValueVT.bitsLT(Val.getValueType()))
206      return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
207                         DAG.getTargetConstant(1, TLI.getPointerTy()));
208
209    return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
210  }
211
212  if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
213    return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
214
215  llvm_unreachable("Unknown mismatch!");
216}
217
218static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
219                                              const Twine &ErrMsg) {
220  const Instruction *I = dyn_cast_or_null<Instruction>(V);
221  if (!V)
222    return Ctx.emitError(ErrMsg);
223
224  const char *AsmError = ", possible invalid constraint for vector type";
225  if (const CallInst *CI = dyn_cast<CallInst>(I))
226    if (isa<InlineAsm>(CI->getCalledValue()))
227      return Ctx.emitError(I, ErrMsg + AsmError);
228
229  return Ctx.emitError(I, ErrMsg);
230}
231
232/// getCopyFromPartsVector - Create a value that contains the specified legal
233/// parts combined into the value they represent.  If the parts combine to a
234/// type larger then ValueVT then AssertOp can be used to specify whether the
235/// extra bits are known to be zero (ISD::AssertZext) or sign extended from
236/// ValueVT (ISD::AssertSext).
237static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
238                                      const SDValue *Parts, unsigned NumParts,
239                                      MVT PartVT, EVT ValueVT, const Value *V) {
240  assert(ValueVT.isVector() && "Not a vector value");
241  assert(NumParts > 0 && "No parts to assemble!");
242  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
243  SDValue Val = Parts[0];
244
245  // Handle a multi-element vector.
246  if (NumParts > 1) {
247    EVT IntermediateVT;
248    MVT RegisterVT;
249    unsigned NumIntermediates;
250    unsigned NumRegs =
251    TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
252                               NumIntermediates, RegisterVT);
253    assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
254    NumParts = NumRegs; // Silence a compiler warning.
255    assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
256    assert(RegisterVT == Parts[0].getSimpleValueType() &&
257           "Part type doesn't match part!");
258
259    // Assemble the parts into intermediate operands.
260    SmallVector<SDValue, 8> Ops(NumIntermediates);
261    if (NumIntermediates == NumParts) {
262      // If the register was not expanded, truncate or copy the value,
263      // as appropriate.
264      for (unsigned i = 0; i != NumParts; ++i)
265        Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
266                                  PartVT, IntermediateVT, V);
267    } else if (NumParts > 0) {
268      // If the intermediate type was expanded, build the intermediate
269      // operands from the parts.
270      assert(NumParts % NumIntermediates == 0 &&
271             "Must expand into a divisible number of parts!");
272      unsigned Factor = NumParts / NumIntermediates;
273      for (unsigned i = 0; i != NumIntermediates; ++i)
274        Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
275                                  PartVT, IntermediateVT, V);
276    }
277
278    // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
279    // intermediate operands.
280    Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
281                                                : ISD::BUILD_VECTOR,
282                      DL, ValueVT, Ops);
283  }
284
285  // There is now one part, held in Val.  Correct it to match ValueVT.
286  EVT PartEVT = Val.getValueType();
287
288  if (PartEVT == ValueVT)
289    return Val;
290
291  if (PartEVT.isVector()) {
292    // If the element type of the source/dest vectors are the same, but the
293    // parts vector has more elements than the value vector, then we have a
294    // vector widening case (e.g. <2 x float> -> <4 x float>).  Extract the
295    // elements we want.
296    if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
297      assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
298             "Cannot narrow, it would be a lossy transformation");
299      return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
300                         DAG.getConstant(0, TLI.getVectorIdxTy()));
301    }
302
303    // Vector/Vector bitcast.
304    if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
305      return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
306
307    assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
308      "Cannot handle this kind of promotion");
309    // Promoted vector extract
310    bool Smaller = ValueVT.bitsLE(PartEVT);
311    return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
312                       DL, ValueVT, Val);
313
314  }
315
316  // Trivial bitcast if the types are the same size and the destination
317  // vector type is legal.
318  if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
319      TLI.isTypeLegal(ValueVT))
320    return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
321
322  // Handle cases such as i8 -> <1 x i1>
323  if (ValueVT.getVectorNumElements() != 1) {
324    diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
325                                      "non-trivial scalar-to-vector conversion");
326    return DAG.getUNDEF(ValueVT);
327  }
328
329  if (ValueVT.getVectorNumElements() == 1 &&
330      ValueVT.getVectorElementType() != PartEVT) {
331    bool Smaller = ValueVT.bitsLE(PartEVT);
332    Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
333                       DL, ValueVT.getScalarType(), Val);
334  }
335
336  return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
337}
338
339static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
340                                 SDValue Val, SDValue *Parts, unsigned NumParts,
341                                 MVT PartVT, const Value *V);
342
343/// getCopyToParts - Create a series of nodes that contain the specified value
344/// split into legal parts.  If the parts contain more bits than Val, then, for
345/// integers, ExtendKind can be used to specify how to generate the extra bits.
346static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
347                           SDValue Val, SDValue *Parts, unsigned NumParts,
348                           MVT PartVT, const Value *V,
349                           ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
350  EVT ValueVT = Val.getValueType();
351
352  // Handle the vector case separately.
353  if (ValueVT.isVector())
354    return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
355
356  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
357  unsigned PartBits = PartVT.getSizeInBits();
358  unsigned OrigNumParts = NumParts;
359  assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
360
361  if (NumParts == 0)
362    return;
363
364  assert(!ValueVT.isVector() && "Vector case handled elsewhere");
365  EVT PartEVT = PartVT;
366  if (PartEVT == ValueVT) {
367    assert(NumParts == 1 && "No-op copy with multiple parts!");
368    Parts[0] = Val;
369    return;
370  }
371
372  if (NumParts * PartBits > ValueVT.getSizeInBits()) {
373    // If the parts cover more bits than the value has, promote the value.
374    if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
375      assert(NumParts == 1 && "Do not know what to promote to!");
376      Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
377    } else {
378      assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
379             ValueVT.isInteger() &&
380             "Unknown mismatch!");
381      ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
382      Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
383      if (PartVT == MVT::x86mmx)
384        Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
385    }
386  } else if (PartBits == ValueVT.getSizeInBits()) {
387    // Different types of the same size.
388    assert(NumParts == 1 && PartEVT != ValueVT);
389    Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
390  } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
391    // If the parts cover less bits than value has, truncate the value.
392    assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
393           ValueVT.isInteger() &&
394           "Unknown mismatch!");
395    ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
396    Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
397    if (PartVT == MVT::x86mmx)
398      Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
399  }
400
401  // The value may have changed - recompute ValueVT.
402  ValueVT = Val.getValueType();
403  assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
404         "Failed to tile the value with PartVT!");
405
406  if (NumParts == 1) {
407    if (PartEVT != ValueVT)
408      diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
409                                        "scalar-to-vector conversion failed");
410
411    Parts[0] = Val;
412    return;
413  }
414
415  // Expand the value into multiple parts.
416  if (NumParts & (NumParts - 1)) {
417    // The number of parts is not a power of 2.  Split off and copy the tail.
418    assert(PartVT.isInteger() && ValueVT.isInteger() &&
419           "Do not know what to expand to!");
420    unsigned RoundParts = 1 << Log2_32(NumParts);
421    unsigned RoundBits = RoundParts * PartBits;
422    unsigned OddParts = NumParts - RoundParts;
423    SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
424                                 DAG.getIntPtrConstant(RoundBits));
425    getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
426
427    if (TLI.isBigEndian())
428      // The odd parts were reversed by getCopyToParts - unreverse them.
429      std::reverse(Parts + RoundParts, Parts + NumParts);
430
431    NumParts = RoundParts;
432    ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
433    Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
434  }
435
436  // The number of parts is a power of 2.  Repeatedly bisect the value using
437  // EXTRACT_ELEMENT.
438  Parts[0] = DAG.getNode(ISD::BITCAST, DL,
439                         EVT::getIntegerVT(*DAG.getContext(),
440                                           ValueVT.getSizeInBits()),
441                         Val);
442
443  for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
444    for (unsigned i = 0; i < NumParts; i += StepSize) {
445      unsigned ThisBits = StepSize * PartBits / 2;
446      EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
447      SDValue &Part0 = Parts[i];
448      SDValue &Part1 = Parts[i+StepSize/2];
449
450      Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
451                          ThisVT, Part0, DAG.getIntPtrConstant(1));
452      Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
453                          ThisVT, Part0, DAG.getIntPtrConstant(0));
454
455      if (ThisBits == PartBits && ThisVT != PartVT) {
456        Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
457        Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
458      }
459    }
460  }
461
462  if (TLI.isBigEndian())
463    std::reverse(Parts, Parts + OrigNumParts);
464}
465
466
467/// getCopyToPartsVector - Create a series of nodes that contain the specified
468/// value split into legal parts.
469static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
470                                 SDValue Val, SDValue *Parts, unsigned NumParts,
471                                 MVT PartVT, const Value *V) {
472  EVT ValueVT = Val.getValueType();
473  assert(ValueVT.isVector() && "Not a vector");
474  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
475
476  if (NumParts == 1) {
477    EVT PartEVT = PartVT;
478    if (PartEVT == ValueVT) {
479      // Nothing to do.
480    } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
481      // Bitconvert vector->vector case.
482      Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
483    } else if (PartVT.isVector() &&
484               PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
485               PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
486      EVT ElementVT = PartVT.getVectorElementType();
487      // Vector widening case, e.g. <2 x float> -> <4 x float>.  Shuffle in
488      // undef elements.
489      SmallVector<SDValue, 16> Ops;
490      for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
491        Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
492                                  ElementVT, Val, DAG.getConstant(i,
493                                                  TLI.getVectorIdxTy())));
494
495      for (unsigned i = ValueVT.getVectorNumElements(),
496           e = PartVT.getVectorNumElements(); i != e; ++i)
497        Ops.push_back(DAG.getUNDEF(ElementVT));
498
499      Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
500
501      // FIXME: Use CONCAT for 2x -> 4x.
502
503      //SDValue UndefElts = DAG.getUNDEF(VectorTy);
504      //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
505    } else if (PartVT.isVector() &&
506               PartEVT.getVectorElementType().bitsGE(
507                 ValueVT.getVectorElementType()) &&
508               PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
509
510      // Promoted vector extract
511      bool Smaller = PartEVT.bitsLE(ValueVT);
512      Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
513                        DL, PartVT, Val);
514    } else{
515      // Vector -> scalar conversion.
516      assert(ValueVT.getVectorNumElements() == 1 &&
517             "Only trivial vector-to-scalar conversions should get here!");
518      Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
519                        PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
520
521      bool Smaller = ValueVT.bitsLE(PartVT);
522      Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
523                         DL, PartVT, Val);
524    }
525
526    Parts[0] = Val;
527    return;
528  }
529
530  // Handle a multi-element vector.
531  EVT IntermediateVT;
532  MVT RegisterVT;
533  unsigned NumIntermediates;
534  unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
535                                                IntermediateVT,
536                                                NumIntermediates, RegisterVT);
537  unsigned NumElements = ValueVT.getVectorNumElements();
538
539  assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
540  NumParts = NumRegs; // Silence a compiler warning.
541  assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
542
543  // Split the vector into intermediate operands.
544  SmallVector<SDValue, 8> Ops(NumIntermediates);
545  for (unsigned i = 0; i != NumIntermediates; ++i) {
546    if (IntermediateVT.isVector())
547      Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
548                           IntermediateVT, Val,
549                   DAG.getConstant(i * (NumElements / NumIntermediates),
550                                   TLI.getVectorIdxTy()));
551    else
552      Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
553                           IntermediateVT, Val,
554                           DAG.getConstant(i, TLI.getVectorIdxTy()));
555  }
556
557  // Split the intermediate operands into legal parts.
558  if (NumParts == NumIntermediates) {
559    // If the register was not expanded, promote or copy the value,
560    // as appropriate.
561    for (unsigned i = 0; i != NumParts; ++i)
562      getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
563  } else if (NumParts > 0) {
564    // If the intermediate type was expanded, split each the value into
565    // legal parts.
566    assert(NumParts % NumIntermediates == 0 &&
567           "Must expand into a divisible number of parts!");
568    unsigned Factor = NumParts / NumIntermediates;
569    for (unsigned i = 0; i != NumIntermediates; ++i)
570      getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
571  }
572}
573
574namespace {
575  /// RegsForValue - This struct represents the registers (physical or virtual)
576  /// that a particular set of values is assigned, and the type information
577  /// about the value. The most common situation is to represent one value at a
578  /// time, but struct or array values are handled element-wise as multiple
579  /// values.  The splitting of aggregates is performed recursively, so that we
580  /// never have aggregate-typed registers. The values at this point do not
581  /// necessarily have legal types, so each value may require one or more
582  /// registers of some legal type.
583  ///
584  struct RegsForValue {
585    /// ValueVTs - The value types of the values, which may not be legal, and
586    /// may need be promoted or synthesized from one or more registers.
587    ///
588    SmallVector<EVT, 4> ValueVTs;
589
590    /// RegVTs - The value types of the registers. This is the same size as
591    /// ValueVTs and it records, for each value, what the type of the assigned
592    /// register or registers are. (Individual values are never synthesized
593    /// from more than one type of register.)
594    ///
595    /// With virtual registers, the contents of RegVTs is redundant with TLI's
596    /// getRegisterType member function, however when with physical registers
597    /// it is necessary to have a separate record of the types.
598    ///
599    SmallVector<MVT, 4> RegVTs;
600
601    /// Regs - This list holds the registers assigned to the values.
602    /// Each legal or promoted value requires one register, and each
603    /// expanded value requires multiple registers.
604    ///
605    SmallVector<unsigned, 4> Regs;
606
607    RegsForValue() {}
608
609    RegsForValue(const SmallVector<unsigned, 4> &regs,
610                 MVT regvt, EVT valuevt)
611      : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
612
613    RegsForValue(LLVMContext &Context, const TargetLowering &tli,
614                 unsigned Reg, Type *Ty) {
615      ComputeValueVTs(tli, Ty, ValueVTs);
616
617      for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
618        EVT ValueVT = ValueVTs[Value];
619        unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
620        MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
621        for (unsigned i = 0; i != NumRegs; ++i)
622          Regs.push_back(Reg + i);
623        RegVTs.push_back(RegisterVT);
624        Reg += NumRegs;
625      }
626    }
627
628    /// append - Add the specified values to this one.
629    void append(const RegsForValue &RHS) {
630      ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
631      RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
632      Regs.append(RHS.Regs.begin(), RHS.Regs.end());
633    }
634
635    /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
636    /// this value and returns the result as a ValueVTs value.  This uses
637    /// Chain/Flag as the input and updates them for the output Chain/Flag.
638    /// If the Flag pointer is NULL, no flag is used.
639    SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
640                            SDLoc dl,
641                            SDValue &Chain, SDValue *Flag,
642                            const Value *V = nullptr) const;
643
644    /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
645    /// specified value into the registers specified by this object.  This uses
646    /// Chain/Flag as the input and updates them for the output Chain/Flag.
647    /// If the Flag pointer is NULL, no flag is used.
648    void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
649                       SDValue &Chain, SDValue *Flag, const Value *V) const;
650
651    /// AddInlineAsmOperands - Add this value to the specified inlineasm node
652    /// operand list.  This adds the code marker, matching input operand index
653    /// (if applicable), and includes the number of values added into it.
654    void AddInlineAsmOperands(unsigned Kind,
655                              bool HasMatching, unsigned MatchingIdx,
656                              SelectionDAG &DAG,
657                              std::vector<SDValue> &Ops) const;
658  };
659}
660
661/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
662/// this value and returns the result as a ValueVT value.  This uses
663/// Chain/Flag as the input and updates them for the output Chain/Flag.
664/// If the Flag pointer is NULL, no flag is used.
665SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
666                                      FunctionLoweringInfo &FuncInfo,
667                                      SDLoc dl,
668                                      SDValue &Chain, SDValue *Flag,
669                                      const Value *V) const {
670  // A Value with type {} or [0 x %t] needs no registers.
671  if (ValueVTs.empty())
672    return SDValue();
673
674  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
675
676  // Assemble the legal parts into the final values.
677  SmallVector<SDValue, 4> Values(ValueVTs.size());
678  SmallVector<SDValue, 8> Parts;
679  for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
680    // Copy the legal parts from the registers.
681    EVT ValueVT = ValueVTs[Value];
682    unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
683    MVT RegisterVT = RegVTs[Value];
684
685    Parts.resize(NumRegs);
686    for (unsigned i = 0; i != NumRegs; ++i) {
687      SDValue P;
688      if (!Flag) {
689        P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
690      } else {
691        P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
692        *Flag = P.getValue(2);
693      }
694
695      Chain = P.getValue(1);
696      Parts[i] = P;
697
698      // If the source register was virtual and if we know something about it,
699      // add an assert node.
700      if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
701          !RegisterVT.isInteger() || RegisterVT.isVector())
702        continue;
703
704      const FunctionLoweringInfo::LiveOutInfo *LOI =
705        FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
706      if (!LOI)
707        continue;
708
709      unsigned RegSize = RegisterVT.getSizeInBits();
710      unsigned NumSignBits = LOI->NumSignBits;
711      unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
712
713      if (NumZeroBits == RegSize) {
714        // The current value is a zero.
715        // Explicitly express that as it would be easier for
716        // optimizations to kick in.
717        Parts[i] = DAG.getConstant(0, RegisterVT);
718        continue;
719      }
720
721      // FIXME: We capture more information than the dag can represent.  For
722      // now, just use the tightest assertzext/assertsext possible.
723      bool isSExt = true;
724      EVT FromVT(MVT::Other);
725      if (NumSignBits == RegSize)
726        isSExt = true, FromVT = MVT::i1;   // ASSERT SEXT 1
727      else if (NumZeroBits >= RegSize-1)
728        isSExt = false, FromVT = MVT::i1;  // ASSERT ZEXT 1
729      else if (NumSignBits > RegSize-8)
730        isSExt = true, FromVT = MVT::i8;   // ASSERT SEXT 8
731      else if (NumZeroBits >= RegSize-8)
732        isSExt = false, FromVT = MVT::i8;  // ASSERT ZEXT 8
733      else if (NumSignBits > RegSize-16)
734        isSExt = true, FromVT = MVT::i16;  // ASSERT SEXT 16
735      else if (NumZeroBits >= RegSize-16)
736        isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
737      else if (NumSignBits > RegSize-32)
738        isSExt = true, FromVT = MVT::i32;  // ASSERT SEXT 32
739      else if (NumZeroBits >= RegSize-32)
740        isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
741      else
742        continue;
743
744      // Add an assertion node.
745      assert(FromVT != MVT::Other);
746      Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
747                             RegisterVT, P, DAG.getValueType(FromVT));
748    }
749
750    Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
751                                     NumRegs, RegisterVT, ValueVT, V);
752    Part += NumRegs;
753    Parts.clear();
754  }
755
756  return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
757}
758
759/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
760/// specified value into the registers specified by this object.  This uses
761/// Chain/Flag as the input and updates them for the output Chain/Flag.
762/// If the Flag pointer is NULL, no flag is used.
763void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
764                                 SDValue &Chain, SDValue *Flag,
765                                 const Value *V) const {
766  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
767
768  // Get the list of the values's legal parts.
769  unsigned NumRegs = Regs.size();
770  SmallVector<SDValue, 8> Parts(NumRegs);
771  for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
772    EVT ValueVT = ValueVTs[Value];
773    unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
774    MVT RegisterVT = RegVTs[Value];
775    ISD::NodeType ExtendKind =
776      TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
777
778    getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
779                   &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
780    Part += NumParts;
781  }
782
783  // Copy the parts into the registers.
784  SmallVector<SDValue, 8> Chains(NumRegs);
785  for (unsigned i = 0; i != NumRegs; ++i) {
786    SDValue Part;
787    if (!Flag) {
788      Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
789    } else {
790      Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
791      *Flag = Part.getValue(1);
792    }
793
794    Chains[i] = Part.getValue(0);
795  }
796
797  if (NumRegs == 1 || Flag)
798    // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
799    // flagged to it. That is the CopyToReg nodes and the user are considered
800    // a single scheduling unit. If we create a TokenFactor and return it as
801    // chain, then the TokenFactor is both a predecessor (operand) of the
802    // user as well as a successor (the TF operands are flagged to the user).
803    // c1, f1 = CopyToReg
804    // c2, f2 = CopyToReg
805    // c3     = TokenFactor c1, c2
806    // ...
807    //        = op c3, ..., f2
808    Chain = Chains[NumRegs-1];
809  else
810    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
811}
812
813/// AddInlineAsmOperands - Add this value to the specified inlineasm node
814/// operand list.  This adds the code marker and includes the number of
815/// values added into it.
816void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
817                                        unsigned MatchingIdx,
818                                        SelectionDAG &DAG,
819                                        std::vector<SDValue> &Ops) const {
820  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
821
822  unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
823  if (HasMatching)
824    Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
825  else if (!Regs.empty() &&
826           TargetRegisterInfo::isVirtualRegister(Regs.front())) {
827    // Put the register class of the virtual registers in the flag word.  That
828    // way, later passes can recompute register class constraints for inline
829    // assembly as well as normal instructions.
830    // Don't do this for tied operands that can use the regclass information
831    // from the def.
832    const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
833    const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
834    Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
835  }
836
837  SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
838  Ops.push_back(Res);
839
840  unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
841  for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
842    unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
843    MVT RegisterVT = RegVTs[Value];
844    for (unsigned i = 0; i != NumRegs; ++i) {
845      assert(Reg < Regs.size() && "Mismatch in # registers expected");
846      unsigned TheReg = Regs[Reg++];
847      Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
848
849      if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
850        // If we clobbered the stack pointer, MFI should know about it.
851        assert(DAG.getMachineFunction().getFrameInfo()->
852            hasInlineAsmWithSPAdjust());
853      }
854    }
855  }
856}
857
858void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
859                               const TargetLibraryInfo *li) {
860  AA = &aa;
861  GFI = gfi;
862  LibInfo = li;
863  DL = DAG.getTarget().getDataLayout();
864  Context = DAG.getContext();
865  LPadToCallSiteMap.clear();
866}
867
868/// clear - Clear out the current SelectionDAG and the associated
869/// state and prepare this SelectionDAGBuilder object to be used
870/// for a new block. This doesn't clear out information about
871/// additional blocks that are needed to complete switch lowering
872/// or PHI node updating; that information is cleared out as it is
873/// consumed.
874void SelectionDAGBuilder::clear() {
875  NodeMap.clear();
876  UnusedArgNodeMap.clear();
877  PendingLoads.clear();
878  PendingExports.clear();
879  CurInst = nullptr;
880  HasTailCall = false;
881  SDNodeOrder = LowestSDNodeOrder;
882}
883
884/// clearDanglingDebugInfo - Clear the dangling debug information
885/// map. This function is separated from the clear so that debug
886/// information that is dangling in a basic block can be properly
887/// resolved in a different basic block. This allows the
888/// SelectionDAG to resolve dangling debug information attached
889/// to PHI nodes.
890void SelectionDAGBuilder::clearDanglingDebugInfo() {
891  DanglingDebugInfoMap.clear();
892}
893
894/// getRoot - Return the current virtual root of the Selection DAG,
895/// flushing any PendingLoad items. This must be done before emitting
896/// a store or any other node that may need to be ordered after any
897/// prior load instructions.
898///
899SDValue SelectionDAGBuilder::getRoot() {
900  if (PendingLoads.empty())
901    return DAG.getRoot();
902
903  if (PendingLoads.size() == 1) {
904    SDValue Root = PendingLoads[0];
905    DAG.setRoot(Root);
906    PendingLoads.clear();
907    return Root;
908  }
909
910  // Otherwise, we have to make a token factor node.
911  SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
912                             PendingLoads);
913  PendingLoads.clear();
914  DAG.setRoot(Root);
915  return Root;
916}
917
918/// getControlRoot - Similar to getRoot, but instead of flushing all the
919/// PendingLoad items, flush all the PendingExports items. It is necessary
920/// to do this before emitting a terminator instruction.
921///
922SDValue SelectionDAGBuilder::getControlRoot() {
923  SDValue Root = DAG.getRoot();
924
925  if (PendingExports.empty())
926    return Root;
927
928  // Turn all of the CopyToReg chains into one factored node.
929  if (Root.getOpcode() != ISD::EntryToken) {
930    unsigned i = 0, e = PendingExports.size();
931    for (; i != e; ++i) {
932      assert(PendingExports[i].getNode()->getNumOperands() > 1);
933      if (PendingExports[i].getNode()->getOperand(0) == Root)
934        break;  // Don't add the root if we already indirectly depend on it.
935    }
936
937    if (i == e)
938      PendingExports.push_back(Root);
939  }
940
941  Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
942                     PendingExports);
943  PendingExports.clear();
944  DAG.setRoot(Root);
945  return Root;
946}
947
948void SelectionDAGBuilder::visit(const Instruction &I) {
949  // Set up outgoing PHI node register values before emitting the terminator.
950  if (isa<TerminatorInst>(&I))
951    HandlePHINodesInSuccessorBlocks(I.getParent());
952
953  ++SDNodeOrder;
954
955  CurInst = &I;
956
957  visit(I.getOpcode(), I);
958
959  if (!isa<TerminatorInst>(&I) && !HasTailCall)
960    CopyToExportRegsIfNeeded(&I);
961
962  CurInst = nullptr;
963}
964
965void SelectionDAGBuilder::visitPHI(const PHINode &) {
966  llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
967}
968
969void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
970  // Note: this doesn't use InstVisitor, because it has to work with
971  // ConstantExpr's in addition to instructions.
972  switch (Opcode) {
973  default: llvm_unreachable("Unknown instruction type encountered!");
974    // Build the switch statement using the Instruction.def file.
975#define HANDLE_INST(NUM, OPCODE, CLASS) \
976    case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
977#include "llvm/IR/Instruction.def"
978  }
979}
980
981// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
982// generate the debug data structures now that we've seen its definition.
983void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
984                                                   SDValue Val) {
985  DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
986  if (DDI.getDI()) {
987    const DbgValueInst *DI = DDI.getDI();
988    DebugLoc dl = DDI.getdl();
989    unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
990    MDNode *Variable = DI->getVariable();
991    uint64_t Offset = DI->getOffset();
992    // A dbg.value for an alloca is always indirect.
993    bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
994    SDDbgValue *SDV;
995    if (Val.getNode()) {
996      if (!EmitFuncArgumentDbgValue(V, Variable, Offset, IsIndirect, Val)) {
997        SDV = DAG.getDbgValue(Variable, Val.getNode(),
998                              Val.getResNo(), IsIndirect,
999			      Offset, dl, DbgSDNodeOrder);
1000        DAG.AddDbgValue(SDV, Val.getNode(), false);
1001      }
1002    } else
1003      DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1004    DanglingDebugInfoMap[V] = DanglingDebugInfo();
1005  }
1006}
1007
1008/// getValue - Return an SDValue for the given Value.
1009SDValue SelectionDAGBuilder::getValue(const Value *V) {
1010  // If we already have an SDValue for this value, use it. It's important
1011  // to do this first, so that we don't create a CopyFromReg if we already
1012  // have a regular SDValue.
1013  SDValue &N = NodeMap[V];
1014  if (N.getNode()) return N;
1015
1016  // If there's a virtual register allocated and initialized for this
1017  // value, use it.
1018  DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1019  if (It != FuncInfo.ValueMap.end()) {
1020    unsigned InReg = It->second;
1021    RegsForValue RFV(*DAG.getContext(), *TM.getTargetLowering(),
1022                     InReg, V->getType());
1023    SDValue Chain = DAG.getEntryNode();
1024    N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1025    resolveDanglingDebugInfo(V, N);
1026    return N;
1027  }
1028
1029  // Otherwise create a new SDValue and remember it.
1030  SDValue Val = getValueImpl(V);
1031  NodeMap[V] = Val;
1032  resolveDanglingDebugInfo(V, Val);
1033  return Val;
1034}
1035
1036/// getNonRegisterValue - Return an SDValue for the given Value, but
1037/// don't look in FuncInfo.ValueMap for a virtual register.
1038SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1039  // If we already have an SDValue for this value, use it.
1040  SDValue &N = NodeMap[V];
1041  if (N.getNode()) return N;
1042
1043  // Otherwise create a new SDValue and remember it.
1044  SDValue Val = getValueImpl(V);
1045  NodeMap[V] = Val;
1046  resolveDanglingDebugInfo(V, Val);
1047  return Val;
1048}
1049
1050/// getValueImpl - Helper function for getValue and getNonRegisterValue.
1051/// Create an SDValue for the given value.
1052SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1053  const TargetLowering *TLI = TM.getTargetLowering();
1054
1055  if (const Constant *C = dyn_cast<Constant>(V)) {
1056    EVT VT = TLI->getValueType(V->getType(), true);
1057
1058    if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1059      return DAG.getConstant(*CI, VT);
1060
1061    if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1062      return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1063
1064    if (isa<ConstantPointerNull>(C)) {
1065      unsigned AS = V->getType()->getPointerAddressSpace();
1066      return DAG.getConstant(0, TLI->getPointerTy(AS));
1067    }
1068
1069    if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1070      return DAG.getConstantFP(*CFP, VT);
1071
1072    if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1073      return DAG.getUNDEF(VT);
1074
1075    if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1076      visit(CE->getOpcode(), *CE);
1077      SDValue N1 = NodeMap[V];
1078      assert(N1.getNode() && "visit didn't populate the NodeMap!");
1079      return N1;
1080    }
1081
1082    if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1083      SmallVector<SDValue, 4> Constants;
1084      for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1085           OI != OE; ++OI) {
1086        SDNode *Val = getValue(*OI).getNode();
1087        // If the operand is an empty aggregate, there are no values.
1088        if (!Val) continue;
1089        // Add each leaf value from the operand to the Constants list
1090        // to form a flattened list of all the values.
1091        for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1092          Constants.push_back(SDValue(Val, i));
1093      }
1094
1095      return DAG.getMergeValues(Constants, getCurSDLoc());
1096    }
1097
1098    if (const ConstantDataSequential *CDS =
1099          dyn_cast<ConstantDataSequential>(C)) {
1100      SmallVector<SDValue, 4> Ops;
1101      for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1102        SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1103        // Add each leaf value from the operand to the Constants list
1104        // to form a flattened list of all the values.
1105        for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1106          Ops.push_back(SDValue(Val, i));
1107      }
1108
1109      if (isa<ArrayType>(CDS->getType()))
1110        return DAG.getMergeValues(Ops, getCurSDLoc());
1111      return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1112                                      VT, Ops);
1113    }
1114
1115    if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1116      assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1117             "Unknown struct or array constant!");
1118
1119      SmallVector<EVT, 4> ValueVTs;
1120      ComputeValueVTs(*TLI, C->getType(), ValueVTs);
1121      unsigned NumElts = ValueVTs.size();
1122      if (NumElts == 0)
1123        return SDValue(); // empty struct
1124      SmallVector<SDValue, 4> Constants(NumElts);
1125      for (unsigned i = 0; i != NumElts; ++i) {
1126        EVT EltVT = ValueVTs[i];
1127        if (isa<UndefValue>(C))
1128          Constants[i] = DAG.getUNDEF(EltVT);
1129        else if (EltVT.isFloatingPoint())
1130          Constants[i] = DAG.getConstantFP(0, EltVT);
1131        else
1132          Constants[i] = DAG.getConstant(0, EltVT);
1133      }
1134
1135      return DAG.getMergeValues(Constants, getCurSDLoc());
1136    }
1137
1138    if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1139      return DAG.getBlockAddress(BA, VT);
1140
1141    VectorType *VecTy = cast<VectorType>(V->getType());
1142    unsigned NumElements = VecTy->getNumElements();
1143
1144    // Now that we know the number and type of the elements, get that number of
1145    // elements into the Ops array based on what kind of constant it is.
1146    SmallVector<SDValue, 16> Ops;
1147    if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1148      for (unsigned i = 0; i != NumElements; ++i)
1149        Ops.push_back(getValue(CV->getOperand(i)));
1150    } else {
1151      assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1152      EVT EltVT = TLI->getValueType(VecTy->getElementType());
1153
1154      SDValue Op;
1155      if (EltVT.isFloatingPoint())
1156        Op = DAG.getConstantFP(0, EltVT);
1157      else
1158        Op = DAG.getConstant(0, EltVT);
1159      Ops.assign(NumElements, Op);
1160    }
1161
1162    // Create a BUILD_VECTOR node.
1163    return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1164  }
1165
1166  // If this is a static alloca, generate it as the frameindex instead of
1167  // computation.
1168  if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1169    DenseMap<const AllocaInst*, int>::iterator SI =
1170      FuncInfo.StaticAllocaMap.find(AI);
1171    if (SI != FuncInfo.StaticAllocaMap.end())
1172      return DAG.getFrameIndex(SI->second, TLI->getPointerTy());
1173  }
1174
1175  // If this is an instruction which fast-isel has deferred, select it now.
1176  if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1177    unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1178    RegsForValue RFV(*DAG.getContext(), *TLI, InReg, Inst->getType());
1179    SDValue Chain = DAG.getEntryNode();
1180    return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1181  }
1182
1183  llvm_unreachable("Can't get register for value!");
1184}
1185
1186void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1187  const TargetLowering *TLI = TM.getTargetLowering();
1188  SDValue Chain = getControlRoot();
1189  SmallVector<ISD::OutputArg, 8> Outs;
1190  SmallVector<SDValue, 8> OutVals;
1191
1192  if (!FuncInfo.CanLowerReturn) {
1193    unsigned DemoteReg = FuncInfo.DemoteRegister;
1194    const Function *F = I.getParent()->getParent();
1195
1196    // Emit a store of the return value through the virtual register.
1197    // Leave Outs empty so that LowerReturn won't try to load return
1198    // registers the usual way.
1199    SmallVector<EVT, 1> PtrValueVTs;
1200    ComputeValueVTs(*TLI, PointerType::getUnqual(F->getReturnType()),
1201                    PtrValueVTs);
1202
1203    SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1204    SDValue RetOp = getValue(I.getOperand(0));
1205
1206    SmallVector<EVT, 4> ValueVTs;
1207    SmallVector<uint64_t, 4> Offsets;
1208    ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1209    unsigned NumValues = ValueVTs.size();
1210
1211    SmallVector<SDValue, 4> Chains(NumValues);
1212    for (unsigned i = 0; i != NumValues; ++i) {
1213      SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1214                                RetPtr.getValueType(), RetPtr,
1215                                DAG.getIntPtrConstant(Offsets[i]));
1216      Chains[i] =
1217        DAG.getStore(Chain, getCurSDLoc(),
1218                     SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1219                     // FIXME: better loc info would be nice.
1220                     Add, MachinePointerInfo(), false, false, 0);
1221    }
1222
1223    Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1224                        MVT::Other, Chains);
1225  } else if (I.getNumOperands() != 0) {
1226    SmallVector<EVT, 4> ValueVTs;
1227    ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs);
1228    unsigned NumValues = ValueVTs.size();
1229    if (NumValues) {
1230      SDValue RetOp = getValue(I.getOperand(0));
1231      for (unsigned j = 0, f = NumValues; j != f; ++j) {
1232        EVT VT = ValueVTs[j];
1233
1234        ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1235
1236        const Function *F = I.getParent()->getParent();
1237        if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1238                                            Attribute::SExt))
1239          ExtendKind = ISD::SIGN_EXTEND;
1240        else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1241                                                 Attribute::ZExt))
1242          ExtendKind = ISD::ZERO_EXTEND;
1243
1244        if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1245          VT = TLI->getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1246
1247        unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), VT);
1248        MVT PartVT = TLI->getRegisterType(*DAG.getContext(), VT);
1249        SmallVector<SDValue, 4> Parts(NumParts);
1250        getCopyToParts(DAG, getCurSDLoc(),
1251                       SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1252                       &Parts[0], NumParts, PartVT, &I, ExtendKind);
1253
1254        // 'inreg' on function refers to return value
1255        ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1256        if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1257                                            Attribute::InReg))
1258          Flags.setInReg();
1259
1260        // Propagate extension type if any
1261        if (ExtendKind == ISD::SIGN_EXTEND)
1262          Flags.setSExt();
1263        else if (ExtendKind == ISD::ZERO_EXTEND)
1264          Flags.setZExt();
1265
1266        for (unsigned i = 0; i < NumParts; ++i) {
1267          Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1268                                        VT, /*isfixed=*/true, 0, 0));
1269          OutVals.push_back(Parts[i]);
1270        }
1271      }
1272    }
1273  }
1274
1275  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1276  CallingConv::ID CallConv =
1277    DAG.getMachineFunction().getFunction()->getCallingConv();
1278  Chain = TM.getTargetLowering()->LowerReturn(Chain, CallConv, isVarArg,
1279                                              Outs, OutVals, getCurSDLoc(),
1280                                              DAG);
1281
1282  // Verify that the target's LowerReturn behaved as expected.
1283  assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1284         "LowerReturn didn't return a valid chain!");
1285
1286  // Update the DAG with the new chain value resulting from return lowering.
1287  DAG.setRoot(Chain);
1288}
1289
1290/// CopyToExportRegsIfNeeded - If the given value has virtual registers
1291/// created for it, emit nodes to copy the value into the virtual
1292/// registers.
1293void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1294  // Skip empty types
1295  if (V->getType()->isEmptyTy())
1296    return;
1297
1298  DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1299  if (VMI != FuncInfo.ValueMap.end()) {
1300    assert(!V->use_empty() && "Unused value assigned virtual registers!");
1301    CopyValueToVirtualRegister(V, VMI->second);
1302  }
1303}
1304
1305/// ExportFromCurrentBlock - If this condition isn't known to be exported from
1306/// the current basic block, add it to ValueMap now so that we'll get a
1307/// CopyTo/FromReg.
1308void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1309  // No need to export constants.
1310  if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1311
1312  // Already exported?
1313  if (FuncInfo.isExportedInst(V)) return;
1314
1315  unsigned Reg = FuncInfo.InitializeRegForValue(V);
1316  CopyValueToVirtualRegister(V, Reg);
1317}
1318
1319bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1320                                                     const BasicBlock *FromBB) {
1321  // The operands of the setcc have to be in this block.  We don't know
1322  // how to export them from some other block.
1323  if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1324    // Can export from current BB.
1325    if (VI->getParent() == FromBB)
1326      return true;
1327
1328    // Is already exported, noop.
1329    return FuncInfo.isExportedInst(V);
1330  }
1331
1332  // If this is an argument, we can export it if the BB is the entry block or
1333  // if it is already exported.
1334  if (isa<Argument>(V)) {
1335    if (FromBB == &FromBB->getParent()->getEntryBlock())
1336      return true;
1337
1338    // Otherwise, can only export this if it is already exported.
1339    return FuncInfo.isExportedInst(V);
1340  }
1341
1342  // Otherwise, constants can always be exported.
1343  return true;
1344}
1345
1346/// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1347uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1348                                            const MachineBasicBlock *Dst) const {
1349  BranchProbabilityInfo *BPI = FuncInfo.BPI;
1350  if (!BPI)
1351    return 0;
1352  const BasicBlock *SrcBB = Src->getBasicBlock();
1353  const BasicBlock *DstBB = Dst->getBasicBlock();
1354  return BPI->getEdgeWeight(SrcBB, DstBB);
1355}
1356
1357void SelectionDAGBuilder::
1358addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1359                       uint32_t Weight /* = 0 */) {
1360  if (!Weight)
1361    Weight = getEdgeWeight(Src, Dst);
1362  Src->addSuccessor(Dst, Weight);
1363}
1364
1365
1366static bool InBlock(const Value *V, const BasicBlock *BB) {
1367  if (const Instruction *I = dyn_cast<Instruction>(V))
1368    return I->getParent() == BB;
1369  return true;
1370}
1371
1372/// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1373/// This function emits a branch and is used at the leaves of an OR or an
1374/// AND operator tree.
1375///
1376void
1377SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1378                                                  MachineBasicBlock *TBB,
1379                                                  MachineBasicBlock *FBB,
1380                                                  MachineBasicBlock *CurBB,
1381                                                  MachineBasicBlock *SwitchBB,
1382                                                  uint32_t TWeight,
1383                                                  uint32_t FWeight) {
1384  const BasicBlock *BB = CurBB->getBasicBlock();
1385
1386  // If the leaf of the tree is a comparison, merge the condition into
1387  // the caseblock.
1388  if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1389    // The operands of the cmp have to be in this block.  We don't know
1390    // how to export them from some other block.  If this is the first block
1391    // of the sequence, no exporting is needed.
1392    if (CurBB == SwitchBB ||
1393        (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1394         isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1395      ISD::CondCode Condition;
1396      if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1397        Condition = getICmpCondCode(IC->getPredicate());
1398      } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1399        Condition = getFCmpCondCode(FC->getPredicate());
1400        if (TM.Options.NoNaNsFPMath)
1401          Condition = getFCmpCodeWithoutNaN(Condition);
1402      } else {
1403        Condition = ISD::SETEQ; // silence warning.
1404        llvm_unreachable("Unknown compare instruction");
1405      }
1406
1407      CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1408                   TBB, FBB, CurBB, TWeight, FWeight);
1409      SwitchCases.push_back(CB);
1410      return;
1411    }
1412  }
1413
1414  // Create a CaseBlock record representing this branch.
1415  CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1416               nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1417  SwitchCases.push_back(CB);
1418}
1419
1420/// Scale down both weights to fit into uint32_t.
1421static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1422  uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1423  uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1424  NewTrue = NewTrue / Scale;
1425  NewFalse = NewFalse / Scale;
1426}
1427
1428/// FindMergedConditions - If Cond is an expression like
1429void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1430                                               MachineBasicBlock *TBB,
1431                                               MachineBasicBlock *FBB,
1432                                               MachineBasicBlock *CurBB,
1433                                               MachineBasicBlock *SwitchBB,
1434                                               unsigned Opc, uint32_t TWeight,
1435                                               uint32_t FWeight) {
1436  // If this node is not part of the or/and tree, emit it as a branch.
1437  const Instruction *BOp = dyn_cast<Instruction>(Cond);
1438  if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1439      (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1440      BOp->getParent() != CurBB->getBasicBlock() ||
1441      !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1442      !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1443    EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1444                                 TWeight, FWeight);
1445    return;
1446  }
1447
1448  //  Create TmpBB after CurBB.
1449  MachineFunction::iterator BBI = CurBB;
1450  MachineFunction &MF = DAG.getMachineFunction();
1451  MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1452  CurBB->getParent()->insert(++BBI, TmpBB);
1453
1454  if (Opc == Instruction::Or) {
1455    // Codegen X | Y as:
1456    // BB1:
1457    //   jmp_if_X TBB
1458    //   jmp TmpBB
1459    // TmpBB:
1460    //   jmp_if_Y TBB
1461    //   jmp FBB
1462    //
1463
1464    // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1465    // The requirement is that
1466    //   TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1467    //     = TrueProb for orignal BB.
1468    // Assuming the orignal weights are A and B, one choice is to set BB1's
1469    // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1470    // assumes that
1471    //   TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1472    // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1473    // TmpBB, but the math is more complicated.
1474
1475    uint64_t NewTrueWeight = TWeight;
1476    uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1477    ScaleWeights(NewTrueWeight, NewFalseWeight);
1478    // Emit the LHS condition.
1479    FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1480                         NewTrueWeight, NewFalseWeight);
1481
1482    NewTrueWeight = TWeight;
1483    NewFalseWeight = 2 * (uint64_t)FWeight;
1484    ScaleWeights(NewTrueWeight, NewFalseWeight);
1485    // Emit the RHS condition into TmpBB.
1486    FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1487                         NewTrueWeight, NewFalseWeight);
1488  } else {
1489    assert(Opc == Instruction::And && "Unknown merge op!");
1490    // Codegen X & Y as:
1491    // BB1:
1492    //   jmp_if_X TmpBB
1493    //   jmp FBB
1494    // TmpBB:
1495    //   jmp_if_Y TBB
1496    //   jmp FBB
1497    //
1498    //  This requires creation of TmpBB after CurBB.
1499
1500    // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1501    // The requirement is that
1502    //   FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1503    //     = FalseProb for orignal BB.
1504    // Assuming the orignal weights are A and B, one choice is to set BB1's
1505    // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1506    // assumes that
1507    //   FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1508
1509    uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1510    uint64_t NewFalseWeight = FWeight;
1511    ScaleWeights(NewTrueWeight, NewFalseWeight);
1512    // Emit the LHS condition.
1513    FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1514                         NewTrueWeight, NewFalseWeight);
1515
1516    NewTrueWeight = 2 * (uint64_t)TWeight;
1517    NewFalseWeight = FWeight;
1518    ScaleWeights(NewTrueWeight, NewFalseWeight);
1519    // Emit the RHS condition into TmpBB.
1520    FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1521                         NewTrueWeight, NewFalseWeight);
1522  }
1523}
1524
1525/// If the set of cases should be emitted as a series of branches, return true.
1526/// If we should emit this as a bunch of and/or'd together conditions, return
1527/// false.
1528bool
1529SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1530  if (Cases.size() != 2) return true;
1531
1532  // If this is two comparisons of the same values or'd or and'd together, they
1533  // will get folded into a single comparison, so don't emit two blocks.
1534  if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1535       Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1536      (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1537       Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1538    return false;
1539  }
1540
1541  // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1542  // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1543  if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1544      Cases[0].CC == Cases[1].CC &&
1545      isa<Constant>(Cases[0].CmpRHS) &&
1546      cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1547    if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1548      return false;
1549    if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1550      return false;
1551  }
1552
1553  return true;
1554}
1555
1556void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1557  MachineBasicBlock *BrMBB = FuncInfo.MBB;
1558
1559  // Update machine-CFG edges.
1560  MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1561
1562  // Figure out which block is immediately after the current one.
1563  MachineBasicBlock *NextBlock = nullptr;
1564  MachineFunction::iterator BBI = BrMBB;
1565  if (++BBI != FuncInfo.MF->end())
1566    NextBlock = BBI;
1567
1568  if (I.isUnconditional()) {
1569    // Update machine-CFG edges.
1570    BrMBB->addSuccessor(Succ0MBB);
1571
1572    // If this is not a fall-through branch or optimizations are switched off,
1573    // emit the branch.
1574    if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1575      DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1576                              MVT::Other, getControlRoot(),
1577                              DAG.getBasicBlock(Succ0MBB)));
1578
1579    return;
1580  }
1581
1582  // If this condition is one of the special cases we handle, do special stuff
1583  // now.
1584  const Value *CondVal = I.getCondition();
1585  MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1586
1587  // If this is a series of conditions that are or'd or and'd together, emit
1588  // this as a sequence of branches instead of setcc's with and/or operations.
1589  // As long as jumps are not expensive, this should improve performance.
1590  // For example, instead of something like:
1591  //     cmp A, B
1592  //     C = seteq
1593  //     cmp D, E
1594  //     F = setle
1595  //     or C, F
1596  //     jnz foo
1597  // Emit:
1598  //     cmp A, B
1599  //     je foo
1600  //     cmp D, E
1601  //     jle foo
1602  //
1603  if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1604    if (!TM.getTargetLowering()->isJumpExpensive() &&
1605        BOp->hasOneUse() &&
1606        (BOp->getOpcode() == Instruction::And ||
1607         BOp->getOpcode() == Instruction::Or)) {
1608      FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1609                           BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1610                           getEdgeWeight(BrMBB, Succ1MBB));
1611      // If the compares in later blocks need to use values not currently
1612      // exported from this block, export them now.  This block should always
1613      // be the first entry.
1614      assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1615
1616      // Allow some cases to be rejected.
1617      if (ShouldEmitAsBranches(SwitchCases)) {
1618        for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1619          ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1620          ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1621        }
1622
1623        // Emit the branch for this block.
1624        visitSwitchCase(SwitchCases[0], BrMBB);
1625        SwitchCases.erase(SwitchCases.begin());
1626        return;
1627      }
1628
1629      // Okay, we decided not to do this, remove any inserted MBB's and clear
1630      // SwitchCases.
1631      for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1632        FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1633
1634      SwitchCases.clear();
1635    }
1636  }
1637
1638  // Create a CaseBlock record representing this branch.
1639  CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1640               nullptr, Succ0MBB, Succ1MBB, BrMBB);
1641
1642  // Use visitSwitchCase to actually insert the fast branch sequence for this
1643  // cond branch.
1644  visitSwitchCase(CB, BrMBB);
1645}
1646
1647/// visitSwitchCase - Emits the necessary code to represent a single node in
1648/// the binary search tree resulting from lowering a switch instruction.
1649void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1650                                          MachineBasicBlock *SwitchBB) {
1651  SDValue Cond;
1652  SDValue CondLHS = getValue(CB.CmpLHS);
1653  SDLoc dl = getCurSDLoc();
1654
1655  // Build the setcc now.
1656  if (!CB.CmpMHS) {
1657    // Fold "(X == true)" to X and "(X == false)" to !X to
1658    // handle common cases produced by branch lowering.
1659    if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1660        CB.CC == ISD::SETEQ)
1661      Cond = CondLHS;
1662    else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1663             CB.CC == ISD::SETEQ) {
1664      SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1665      Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1666    } else
1667      Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1668  } else {
1669    assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1670
1671    const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1672    const APInt& High  = cast<ConstantInt>(CB.CmpRHS)->getValue();
1673
1674    SDValue CmpOp = getValue(CB.CmpMHS);
1675    EVT VT = CmpOp.getValueType();
1676
1677    if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1678      Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1679                          ISD::SETLE);
1680    } else {
1681      SDValue SUB = DAG.getNode(ISD::SUB, dl,
1682                                VT, CmpOp, DAG.getConstant(Low, VT));
1683      Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1684                          DAG.getConstant(High-Low, VT), ISD::SETULE);
1685    }
1686  }
1687
1688  // Update successor info
1689  addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1690  // TrueBB and FalseBB are always different unless the incoming IR is
1691  // degenerate. This only happens when running llc on weird IR.
1692  if (CB.TrueBB != CB.FalseBB)
1693    addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1694
1695  // Set NextBlock to be the MBB immediately after the current one, if any.
1696  // This is used to avoid emitting unnecessary branches to the next block.
1697  MachineBasicBlock *NextBlock = nullptr;
1698  MachineFunction::iterator BBI = SwitchBB;
1699  if (++BBI != FuncInfo.MF->end())
1700    NextBlock = BBI;
1701
1702  // If the lhs block is the next block, invert the condition so that we can
1703  // fall through to the lhs instead of the rhs block.
1704  if (CB.TrueBB == NextBlock) {
1705    std::swap(CB.TrueBB, CB.FalseBB);
1706    SDValue True = DAG.getConstant(1, Cond.getValueType());
1707    Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1708  }
1709
1710  SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1711                               MVT::Other, getControlRoot(), Cond,
1712                               DAG.getBasicBlock(CB.TrueBB));
1713
1714  // Insert the false branch. Do this even if it's a fall through branch,
1715  // this makes it easier to do DAG optimizations which require inverting
1716  // the branch condition.
1717  BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1718                       DAG.getBasicBlock(CB.FalseBB));
1719
1720  DAG.setRoot(BrCond);
1721}
1722
1723/// visitJumpTable - Emit JumpTable node in the current MBB
1724void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1725  // Emit the code for the jump table
1726  assert(JT.Reg != -1U && "Should lower JT Header first!");
1727  EVT PTy = TM.getTargetLowering()->getPointerTy();
1728  SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1729                                     JT.Reg, PTy);
1730  SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1731  SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1732                                    MVT::Other, Index.getValue(1),
1733                                    Table, Index);
1734  DAG.setRoot(BrJumpTable);
1735}
1736
1737/// visitJumpTableHeader - This function emits necessary code to produce index
1738/// in the JumpTable from switch case.
1739void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1740                                               JumpTableHeader &JTH,
1741                                               MachineBasicBlock *SwitchBB) {
1742  // Subtract the lowest switch case value from the value being switched on and
1743  // conditional branch to default mbb if the result is greater than the
1744  // difference between smallest and largest cases.
1745  SDValue SwitchOp = getValue(JTH.SValue);
1746  EVT VT = SwitchOp.getValueType();
1747  SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1748                            DAG.getConstant(JTH.First, VT));
1749
1750  // The SDNode we just created, which holds the value being switched on minus
1751  // the smallest case value, needs to be copied to a virtual register so it
1752  // can be used as an index into the jump table in a subsequent basic block.
1753  // This value may be smaller or larger than the target's pointer type, and
1754  // therefore require extension or truncating.
1755  const TargetLowering *TLI = TM.getTargetLowering();
1756  SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI->getPointerTy());
1757
1758  unsigned JumpTableReg = FuncInfo.CreateReg(TLI->getPointerTy());
1759  SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1760                                    JumpTableReg, SwitchOp);
1761  JT.Reg = JumpTableReg;
1762
1763  // Emit the range check for the jump table, and branch to the default block
1764  // for the switch statement if the value being switched on exceeds the largest
1765  // case in the switch.
1766  SDValue CMP = DAG.getSetCC(getCurSDLoc(),
1767                             TLI->getSetCCResultType(*DAG.getContext(),
1768                                                     Sub.getValueType()),
1769                             Sub,
1770                             DAG.getConstant(JTH.Last - JTH.First,VT),
1771                             ISD::SETUGT);
1772
1773  // Set NextBlock to be the MBB immediately after the current one, if any.
1774  // This is used to avoid emitting unnecessary branches to the next block.
1775  MachineBasicBlock *NextBlock = nullptr;
1776  MachineFunction::iterator BBI = SwitchBB;
1777
1778  if (++BBI != FuncInfo.MF->end())
1779    NextBlock = BBI;
1780
1781  SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1782                               MVT::Other, CopyTo, CMP,
1783                               DAG.getBasicBlock(JT.Default));
1784
1785  if (JT.MBB != NextBlock)
1786    BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1787                         DAG.getBasicBlock(JT.MBB));
1788
1789  DAG.setRoot(BrCond);
1790}
1791
1792/// Codegen a new tail for a stack protector check ParentMBB which has had its
1793/// tail spliced into a stack protector check success bb.
1794///
1795/// For a high level explanation of how this fits into the stack protector
1796/// generation see the comment on the declaration of class
1797/// StackProtectorDescriptor.
1798void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1799                                                  MachineBasicBlock *ParentBB) {
1800
1801  // First create the loads to the guard/stack slot for the comparison.
1802  const TargetLowering *TLI = TM.getTargetLowering();
1803  EVT PtrTy = TLI->getPointerTy();
1804
1805  MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1806  int FI = MFI->getStackProtectorIndex();
1807
1808  const Value *IRGuard = SPD.getGuard();
1809  SDValue GuardPtr = getValue(IRGuard);
1810  SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1811
1812  unsigned Align =
1813    TLI->getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1814  SDValue Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1815                              GuardPtr, MachinePointerInfo(IRGuard, 0),
1816                              true, false, false, Align);
1817
1818  SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1819                                  StackSlotPtr,
1820                                  MachinePointerInfo::getFixedStack(FI),
1821                                  true, false, false, Align);
1822
1823  // Perform the comparison via a subtract/getsetcc.
1824  EVT VT = Guard.getValueType();
1825  SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1826
1827  SDValue Cmp = DAG.getSetCC(getCurSDLoc(),
1828                             TLI->getSetCCResultType(*DAG.getContext(),
1829                                                     Sub.getValueType()),
1830                             Sub, DAG.getConstant(0, VT),
1831                             ISD::SETNE);
1832
1833  // If the sub is not 0, then we know the guard/stackslot do not equal, so
1834  // branch to failure MBB.
1835  SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1836                               MVT::Other, StackSlot.getOperand(0),
1837                               Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1838  // Otherwise branch to success MBB.
1839  SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1840                           MVT::Other, BrCond,
1841                           DAG.getBasicBlock(SPD.getSuccessMBB()));
1842
1843  DAG.setRoot(Br);
1844}
1845
1846/// Codegen the failure basic block for a stack protector check.
1847///
1848/// A failure stack protector machine basic block consists simply of a call to
1849/// __stack_chk_fail().
1850///
1851/// For a high level explanation of how this fits into the stack protector
1852/// generation see the comment on the declaration of class
1853/// StackProtectorDescriptor.
1854void
1855SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1856  const TargetLowering *TLI = TM.getTargetLowering();
1857  SDValue Chain = TLI->makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL,
1858                                   MVT::isVoid, nullptr, 0, false,
1859                                   getCurSDLoc(), false, false).second;
1860  DAG.setRoot(Chain);
1861}
1862
1863/// visitBitTestHeader - This function emits necessary code to produce value
1864/// suitable for "bit tests"
1865void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1866                                             MachineBasicBlock *SwitchBB) {
1867  // Subtract the minimum value
1868  SDValue SwitchOp = getValue(B.SValue);
1869  EVT VT = SwitchOp.getValueType();
1870  SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1871                            DAG.getConstant(B.First, VT));
1872
1873  // Check range
1874  const TargetLowering *TLI = TM.getTargetLowering();
1875  SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(),
1876                                  TLI->getSetCCResultType(*DAG.getContext(),
1877                                                         Sub.getValueType()),
1878                                  Sub, DAG.getConstant(B.Range, VT),
1879                                  ISD::SETUGT);
1880
1881  // Determine the type of the test operands.
1882  bool UsePtrType = false;
1883  if (!TLI->isTypeLegal(VT))
1884    UsePtrType = true;
1885  else {
1886    for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1887      if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1888        // Switch table case range are encoded into series of masks.
1889        // Just use pointer type, it's guaranteed to fit.
1890        UsePtrType = true;
1891        break;
1892      }
1893  }
1894  if (UsePtrType) {
1895    VT = TLI->getPointerTy();
1896    Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1897  }
1898
1899  B.RegVT = VT.getSimpleVT();
1900  B.Reg = FuncInfo.CreateReg(B.RegVT);
1901  SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1902                                    B.Reg, Sub);
1903
1904  // Set NextBlock to be the MBB immediately after the current one, if any.
1905  // This is used to avoid emitting unnecessary branches to the next block.
1906  MachineBasicBlock *NextBlock = nullptr;
1907  MachineFunction::iterator BBI = SwitchBB;
1908  if (++BBI != FuncInfo.MF->end())
1909    NextBlock = BBI;
1910
1911  MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1912
1913  addSuccessorWithWeight(SwitchBB, B.Default);
1914  addSuccessorWithWeight(SwitchBB, MBB);
1915
1916  SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1917                                MVT::Other, CopyTo, RangeCmp,
1918                                DAG.getBasicBlock(B.Default));
1919
1920  if (MBB != NextBlock)
1921    BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1922                          DAG.getBasicBlock(MBB));
1923
1924  DAG.setRoot(BrRange);
1925}
1926
1927/// visitBitTestCase - this function produces one "bit test"
1928void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1929                                           MachineBasicBlock* NextMBB,
1930                                           uint32_t BranchWeightToNext,
1931                                           unsigned Reg,
1932                                           BitTestCase &B,
1933                                           MachineBasicBlock *SwitchBB) {
1934  MVT VT = BB.RegVT;
1935  SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1936                                       Reg, VT);
1937  SDValue Cmp;
1938  unsigned PopCount = CountPopulation_64(B.Mask);
1939  const TargetLowering *TLI = TM.getTargetLowering();
1940  if (PopCount == 1) {
1941    // Testing for a single bit; just compare the shift count with what it
1942    // would need to be to shift a 1 bit in that position.
1943    Cmp = DAG.getSetCC(getCurSDLoc(),
1944                       TLI->getSetCCResultType(*DAG.getContext(), VT),
1945                       ShiftOp,
1946                       DAG.getConstant(countTrailingZeros(B.Mask), VT),
1947                       ISD::SETEQ);
1948  } else if (PopCount == BB.Range) {
1949    // There is only one zero bit in the range, test for it directly.
1950    Cmp = DAG.getSetCC(getCurSDLoc(),
1951                       TLI->getSetCCResultType(*DAG.getContext(), VT),
1952                       ShiftOp,
1953                       DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1954                       ISD::SETNE);
1955  } else {
1956    // Make desired shift
1957    SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1958                                    DAG.getConstant(1, VT), ShiftOp);
1959
1960    // Emit bit tests and jumps
1961    SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1962                                VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1963    Cmp = DAG.getSetCC(getCurSDLoc(),
1964                       TLI->getSetCCResultType(*DAG.getContext(), VT),
1965                       AndOp, DAG.getConstant(0, VT),
1966                       ISD::SETNE);
1967  }
1968
1969  // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1970  addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1971  // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1972  addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1973
1974  SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1975                              MVT::Other, getControlRoot(),
1976                              Cmp, DAG.getBasicBlock(B.TargetBB));
1977
1978  // Set NextBlock to be the MBB immediately after the current one, if any.
1979  // This is used to avoid emitting unnecessary branches to the next block.
1980  MachineBasicBlock *NextBlock = nullptr;
1981  MachineFunction::iterator BBI = SwitchBB;
1982  if (++BBI != FuncInfo.MF->end())
1983    NextBlock = BBI;
1984
1985  if (NextMBB != NextBlock)
1986    BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1987                        DAG.getBasicBlock(NextMBB));
1988
1989  DAG.setRoot(BrAnd);
1990}
1991
1992void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1993  MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1994
1995  // Retrieve successors.
1996  MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1997  MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1998
1999  const Value *Callee(I.getCalledValue());
2000  const Function *Fn = dyn_cast<Function>(Callee);
2001  if (isa<InlineAsm>(Callee))
2002    visitInlineAsm(&I);
2003  else if (Fn && Fn->isIntrinsic()) {
2004    assert(Fn->getIntrinsicID() == Intrinsic::donothing);
2005    // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2006  } else
2007    LowerCallTo(&I, getValue(Callee), false, LandingPad);
2008
2009  // If the value of the invoke is used outside of its defining block, make it
2010  // available as a virtual register.
2011  CopyToExportRegsIfNeeded(&I);
2012
2013  // Update successor info
2014  addSuccessorWithWeight(InvokeMBB, Return);
2015  addSuccessorWithWeight(InvokeMBB, LandingPad);
2016
2017  // Drop into normal successor.
2018  DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2019                          MVT::Other, getControlRoot(),
2020                          DAG.getBasicBlock(Return)));
2021}
2022
2023void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2024  llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2025}
2026
2027void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2028  assert(FuncInfo.MBB->isLandingPad() &&
2029         "Call to landingpad not in landing pad!");
2030
2031  MachineBasicBlock *MBB = FuncInfo.MBB;
2032  MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2033  AddLandingPadInfo(LP, MMI, MBB);
2034
2035  // If there aren't registers to copy the values into (e.g., during SjLj
2036  // exceptions), then don't bother to create these DAG nodes.
2037  const TargetLowering *TLI = TM.getTargetLowering();
2038  if (TLI->getExceptionPointerRegister() == 0 &&
2039      TLI->getExceptionSelectorRegister() == 0)
2040    return;
2041
2042  SmallVector<EVT, 2> ValueVTs;
2043  ComputeValueVTs(*TLI, LP.getType(), ValueVTs);
2044  assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2045
2046  // Get the two live-in registers as SDValues. The physregs have already been
2047  // copied into virtual registers.
2048  SDValue Ops[2];
2049  Ops[0] = DAG.getZExtOrTrunc(
2050    DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2051                       FuncInfo.ExceptionPointerVirtReg, TLI->getPointerTy()),
2052    getCurSDLoc(), ValueVTs[0]);
2053  Ops[1] = DAG.getZExtOrTrunc(
2054    DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2055                       FuncInfo.ExceptionSelectorVirtReg, TLI->getPointerTy()),
2056    getCurSDLoc(), ValueVTs[1]);
2057
2058  // Merge into one.
2059  SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2060                            DAG.getVTList(ValueVTs), Ops);
2061  setValue(&LP, Res);
2062}
2063
2064/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2065/// small case ranges).
2066bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2067                                                 CaseRecVector& WorkList,
2068                                                 const Value* SV,
2069                                                 MachineBasicBlock *Default,
2070                                                 MachineBasicBlock *SwitchBB) {
2071  // Size is the number of Cases represented by this range.
2072  size_t Size = CR.Range.second - CR.Range.first;
2073  if (Size > 3)
2074    return false;
2075
2076  // Get the MachineFunction which holds the current MBB.  This is used when
2077  // inserting any additional MBBs necessary to represent the switch.
2078  MachineFunction *CurMF = FuncInfo.MF;
2079
2080  // Figure out which block is immediately after the current one.
2081  MachineBasicBlock *NextBlock = nullptr;
2082  MachineFunction::iterator BBI = CR.CaseBB;
2083
2084  if (++BBI != FuncInfo.MF->end())
2085    NextBlock = BBI;
2086
2087  BranchProbabilityInfo *BPI = FuncInfo.BPI;
2088  // If any two of the cases has the same destination, and if one value
2089  // is the same as the other, but has one bit unset that the other has set,
2090  // use bit manipulation to do two compares at once.  For example:
2091  // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2092  // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2093  // TODO: Handle cases where CR.CaseBB != SwitchBB.
2094  if (Size == 2 && CR.CaseBB == SwitchBB) {
2095    Case &Small = *CR.Range.first;
2096    Case &Big = *(CR.Range.second-1);
2097
2098    if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2099      const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2100      const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2101
2102      // Check that there is only one bit different.
2103      if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2104          (SmallValue | BigValue) == BigValue) {
2105        // Isolate the common bit.
2106        APInt CommonBit = BigValue & ~SmallValue;
2107        assert((SmallValue | CommonBit) == BigValue &&
2108               CommonBit.countPopulation() == 1 && "Not a common bit?");
2109
2110        SDValue CondLHS = getValue(SV);
2111        EVT VT = CondLHS.getValueType();
2112        SDLoc DL = getCurSDLoc();
2113
2114        SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2115                                 DAG.getConstant(CommonBit, VT));
2116        SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2117                                    Or, DAG.getConstant(BigValue, VT),
2118                                    ISD::SETEQ);
2119
2120        // Update successor info.
2121        // Both Small and Big will jump to Small.BB, so we sum up the weights.
2122        addSuccessorWithWeight(SwitchBB, Small.BB,
2123                               Small.ExtraWeight + Big.ExtraWeight);
2124        addSuccessorWithWeight(SwitchBB, Default,
2125          // The default destination is the first successor in IR.
2126          BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2127
2128        // Insert the true branch.
2129        SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2130                                     getControlRoot(), Cond,
2131                                     DAG.getBasicBlock(Small.BB));
2132
2133        // Insert the false branch.
2134        BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2135                             DAG.getBasicBlock(Default));
2136
2137        DAG.setRoot(BrCond);
2138        return true;
2139      }
2140    }
2141  }
2142
2143  // Order cases by weight so the most likely case will be checked first.
2144  uint32_t UnhandledWeights = 0;
2145  if (BPI) {
2146    for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2147      uint32_t IWeight = I->ExtraWeight;
2148      UnhandledWeights += IWeight;
2149      for (CaseItr J = CR.Range.first; J < I; ++J) {
2150        uint32_t JWeight = J->ExtraWeight;
2151        if (IWeight > JWeight)
2152          std::swap(*I, *J);
2153      }
2154    }
2155  }
2156  // Rearrange the case blocks so that the last one falls through if possible.
2157  Case &BackCase = *(CR.Range.second-1);
2158  if (Size > 1 &&
2159      NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2160    // The last case block won't fall through into 'NextBlock' if we emit the
2161    // branches in this order.  See if rearranging a case value would help.
2162    // We start at the bottom as it's the case with the least weight.
2163    for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2164      if (I->BB == NextBlock) {
2165        std::swap(*I, BackCase);
2166        break;
2167      }
2168  }
2169
2170  // Create a CaseBlock record representing a conditional branch to
2171  // the Case's target mbb if the value being switched on SV is equal
2172  // to C.
2173  MachineBasicBlock *CurBlock = CR.CaseBB;
2174  for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2175    MachineBasicBlock *FallThrough;
2176    if (I != E-1) {
2177      FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2178      CurMF->insert(BBI, FallThrough);
2179
2180      // Put SV in a virtual register to make it available from the new blocks.
2181      ExportFromCurrentBlock(SV);
2182    } else {
2183      // If the last case doesn't match, go to the default block.
2184      FallThrough = Default;
2185    }
2186
2187    const Value *RHS, *LHS, *MHS;
2188    ISD::CondCode CC;
2189    if (I->High == I->Low) {
2190      // This is just small small case range :) containing exactly 1 case
2191      CC = ISD::SETEQ;
2192      LHS = SV; RHS = I->High; MHS = nullptr;
2193    } else {
2194      CC = ISD::SETLE;
2195      LHS = I->Low; MHS = SV; RHS = I->High;
2196    }
2197
2198    // The false weight should be sum of all un-handled cases.
2199    UnhandledWeights -= I->ExtraWeight;
2200    CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2201                 /* me */ CurBlock,
2202                 /* trueweight */ I->ExtraWeight,
2203                 /* falseweight */ UnhandledWeights);
2204
2205    // If emitting the first comparison, just call visitSwitchCase to emit the
2206    // code into the current block.  Otherwise, push the CaseBlock onto the
2207    // vector to be later processed by SDISel, and insert the node's MBB
2208    // before the next MBB.
2209    if (CurBlock == SwitchBB)
2210      visitSwitchCase(CB, SwitchBB);
2211    else
2212      SwitchCases.push_back(CB);
2213
2214    CurBlock = FallThrough;
2215  }
2216
2217  return true;
2218}
2219
2220static inline bool areJTsAllowed(const TargetLowering &TLI) {
2221  return TLI.supportJumpTables() &&
2222          (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2223           TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2224}
2225
2226static APInt ComputeRange(const APInt &First, const APInt &Last) {
2227  uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2228  APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2229  return (LastExt - FirstExt + 1ULL);
2230}
2231
2232/// handleJTSwitchCase - Emit jumptable for current switch case range
2233bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2234                                             CaseRecVector &WorkList,
2235                                             const Value *SV,
2236                                             MachineBasicBlock *Default,
2237                                             MachineBasicBlock *SwitchBB) {
2238  Case& FrontCase = *CR.Range.first;
2239  Case& BackCase  = *(CR.Range.second-1);
2240
2241  const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2242  const APInt &Last  = cast<ConstantInt>(BackCase.High)->getValue();
2243
2244  APInt TSize(First.getBitWidth(), 0);
2245  for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2246    TSize += I->size();
2247
2248  const TargetLowering *TLI = TM.getTargetLowering();
2249  if (!areJTsAllowed(*TLI) || TSize.ult(TLI->getMinimumJumpTableEntries()))
2250    return false;
2251
2252  APInt Range = ComputeRange(First, Last);
2253  // The density is TSize / Range. Require at least 40%.
2254  // It should not be possible for IntTSize to saturate for sane code, but make
2255  // sure we handle Range saturation correctly.
2256  uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2257  uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2258  if (IntTSize * 10 < IntRange * 4)
2259    return false;
2260
2261  DEBUG(dbgs() << "Lowering jump table\n"
2262               << "First entry: " << First << ". Last entry: " << Last << '\n'
2263               << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2264
2265  // Get the MachineFunction which holds the current MBB.  This is used when
2266  // inserting any additional MBBs necessary to represent the switch.
2267  MachineFunction *CurMF = FuncInfo.MF;
2268
2269  // Figure out which block is immediately after the current one.
2270  MachineFunction::iterator BBI = CR.CaseBB;
2271  ++BBI;
2272
2273  const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2274
2275  // Create a new basic block to hold the code for loading the address
2276  // of the jump table, and jumping to it.  Update successor information;
2277  // we will either branch to the default case for the switch, or the jump
2278  // table.
2279  MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2280  CurMF->insert(BBI, JumpTableBB);
2281
2282  addSuccessorWithWeight(CR.CaseBB, Default);
2283  addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2284
2285  // Build a vector of destination BBs, corresponding to each target
2286  // of the jump table. If the value of the jump table slot corresponds to
2287  // a case statement, push the case's BB onto the vector, otherwise, push
2288  // the default BB.
2289  std::vector<MachineBasicBlock*> DestBBs;
2290  APInt TEI = First;
2291  for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2292    const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2293    const APInt &High = cast<ConstantInt>(I->High)->getValue();
2294
2295    if (Low.sle(TEI) && TEI.sle(High)) {
2296      DestBBs.push_back(I->BB);
2297      if (TEI==High)
2298        ++I;
2299    } else {
2300      DestBBs.push_back(Default);
2301    }
2302  }
2303
2304  // Calculate weight for each unique destination in CR.
2305  DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2306  if (FuncInfo.BPI)
2307    for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2308      DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2309          DestWeights.find(I->BB);
2310      if (Itr != DestWeights.end())
2311        Itr->second += I->ExtraWeight;
2312      else
2313        DestWeights[I->BB] = I->ExtraWeight;
2314    }
2315
2316  // Update successor info. Add one edge to each unique successor.
2317  BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2318  for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2319         E = DestBBs.end(); I != E; ++I) {
2320    if (!SuccsHandled[(*I)->getNumber()]) {
2321      SuccsHandled[(*I)->getNumber()] = true;
2322      DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2323          DestWeights.find(*I);
2324      addSuccessorWithWeight(JumpTableBB, *I,
2325                             Itr != DestWeights.end() ? Itr->second : 0);
2326    }
2327  }
2328
2329  // Create a jump table index for this jump table.
2330  unsigned JTEncoding = TLI->getJumpTableEncoding();
2331  unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2332                       ->createJumpTableIndex(DestBBs);
2333
2334  // Set the jump table information so that we can codegen it as a second
2335  // MachineBasicBlock
2336  JumpTable JT(-1U, JTI, JumpTableBB, Default);
2337  JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2338  if (CR.CaseBB == SwitchBB)
2339    visitJumpTableHeader(JT, JTH, SwitchBB);
2340
2341  JTCases.push_back(JumpTableBlock(JTH, JT));
2342  return true;
2343}
2344
2345/// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2346/// 2 subtrees.
2347bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2348                                                  CaseRecVector& WorkList,
2349                                                  const Value* SV,
2350                                                  MachineBasicBlock* Default,
2351                                                  MachineBasicBlock* SwitchBB) {
2352  // Get the MachineFunction which holds the current MBB.  This is used when
2353  // inserting any additional MBBs necessary to represent the switch.
2354  MachineFunction *CurMF = FuncInfo.MF;
2355
2356  // Figure out which block is immediately after the current one.
2357  MachineFunction::iterator BBI = CR.CaseBB;
2358  ++BBI;
2359
2360  Case& FrontCase = *CR.Range.first;
2361  Case& BackCase  = *(CR.Range.second-1);
2362  const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2363
2364  // Size is the number of Cases represented by this range.
2365  unsigned Size = CR.Range.second - CR.Range.first;
2366
2367  const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2368  const APInt &Last  = cast<ConstantInt>(BackCase.High)->getValue();
2369  double FMetric = 0;
2370  CaseItr Pivot = CR.Range.first + Size/2;
2371
2372  // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2373  // (heuristically) allow us to emit JumpTable's later.
2374  APInt TSize(First.getBitWidth(), 0);
2375  for (CaseItr I = CR.Range.first, E = CR.Range.second;
2376       I!=E; ++I)
2377    TSize += I->size();
2378
2379  APInt LSize = FrontCase.size();
2380  APInt RSize = TSize-LSize;
2381  DEBUG(dbgs() << "Selecting best pivot: \n"
2382               << "First: " << First << ", Last: " << Last <<'\n'
2383               << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2384  for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2385       J!=E; ++I, ++J) {
2386    const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2387    const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2388    APInt Range = ComputeRange(LEnd, RBegin);
2389    assert((Range - 2ULL).isNonNegative() &&
2390           "Invalid case distance");
2391    // Use volatile double here to avoid excess precision issues on some hosts,
2392    // e.g. that use 80-bit X87 registers.
2393    volatile double LDensity =
2394       (double)LSize.roundToDouble() /
2395                           (LEnd - First + 1ULL).roundToDouble();
2396    volatile double RDensity =
2397      (double)RSize.roundToDouble() /
2398                           (Last - RBegin + 1ULL).roundToDouble();
2399    volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2400    // Should always split in some non-trivial place
2401    DEBUG(dbgs() <<"=>Step\n"
2402                 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2403                 << "LDensity: " << LDensity
2404                 << ", RDensity: " << RDensity << '\n'
2405                 << "Metric: " << Metric << '\n');
2406    if (FMetric < Metric) {
2407      Pivot = J;
2408      FMetric = Metric;
2409      DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2410    }
2411
2412    LSize += J->size();
2413    RSize -= J->size();
2414  }
2415
2416  const TargetLowering *TLI = TM.getTargetLowering();
2417  if (areJTsAllowed(*TLI)) {
2418    // If our case is dense we *really* should handle it earlier!
2419    assert((FMetric > 0) && "Should handle dense range earlier!");
2420  } else {
2421    Pivot = CR.Range.first + Size/2;
2422  }
2423
2424  CaseRange LHSR(CR.Range.first, Pivot);
2425  CaseRange RHSR(Pivot, CR.Range.second);
2426  const Constant *C = Pivot->Low;
2427  MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2428
2429  // We know that we branch to the LHS if the Value being switched on is
2430  // less than the Pivot value, C.  We use this to optimize our binary
2431  // tree a bit, by recognizing that if SV is greater than or equal to the
2432  // LHS's Case Value, and that Case Value is exactly one less than the
2433  // Pivot's Value, then we can branch directly to the LHS's Target,
2434  // rather than creating a leaf node for it.
2435  if ((LHSR.second - LHSR.first) == 1 &&
2436      LHSR.first->High == CR.GE &&
2437      cast<ConstantInt>(C)->getValue() ==
2438      (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2439    TrueBB = LHSR.first->BB;
2440  } else {
2441    TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2442    CurMF->insert(BBI, TrueBB);
2443    WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2444
2445    // Put SV in a virtual register to make it available from the new blocks.
2446    ExportFromCurrentBlock(SV);
2447  }
2448
2449  // Similar to the optimization above, if the Value being switched on is
2450  // known to be less than the Constant CR.LT, and the current Case Value
2451  // is CR.LT - 1, then we can branch directly to the target block for
2452  // the current Case Value, rather than emitting a RHS leaf node for it.
2453  if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2454      cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2455      (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2456    FalseBB = RHSR.first->BB;
2457  } else {
2458    FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2459    CurMF->insert(BBI, FalseBB);
2460    WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2461
2462    // Put SV in a virtual register to make it available from the new blocks.
2463    ExportFromCurrentBlock(SV);
2464  }
2465
2466  // Create a CaseBlock record representing a conditional branch to
2467  // the LHS node if the value being switched on SV is less than C.
2468  // Otherwise, branch to LHS.
2469  CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2470
2471  if (CR.CaseBB == SwitchBB)
2472    visitSwitchCase(CB, SwitchBB);
2473  else
2474    SwitchCases.push_back(CB);
2475
2476  return true;
2477}
2478
2479/// handleBitTestsSwitchCase - if current case range has few destination and
2480/// range span less, than machine word bitwidth, encode case range into series
2481/// of masks and emit bit tests with these masks.
2482bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2483                                                   CaseRecVector& WorkList,
2484                                                   const Value* SV,
2485                                                   MachineBasicBlock* Default,
2486                                                   MachineBasicBlock* SwitchBB) {
2487  const TargetLowering *TLI = TM.getTargetLowering();
2488  EVT PTy = TLI->getPointerTy();
2489  unsigned IntPtrBits = PTy.getSizeInBits();
2490
2491  Case& FrontCase = *CR.Range.first;
2492  Case& BackCase  = *(CR.Range.second-1);
2493
2494  // Get the MachineFunction which holds the current MBB.  This is used when
2495  // inserting any additional MBBs necessary to represent the switch.
2496  MachineFunction *CurMF = FuncInfo.MF;
2497
2498  // If target does not have legal shift left, do not emit bit tests at all.
2499  if (!TLI->isOperationLegal(ISD::SHL, PTy))
2500    return false;
2501
2502  size_t numCmps = 0;
2503  for (CaseItr I = CR.Range.first, E = CR.Range.second;
2504       I!=E; ++I) {
2505    // Single case counts one, case range - two.
2506    numCmps += (I->Low == I->High ? 1 : 2);
2507  }
2508
2509  // Count unique destinations
2510  SmallSet<MachineBasicBlock*, 4> Dests;
2511  for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2512    Dests.insert(I->BB);
2513    if (Dests.size() > 3)
2514      // Don't bother the code below, if there are too much unique destinations
2515      return false;
2516  }
2517  DEBUG(dbgs() << "Total number of unique destinations: "
2518        << Dests.size() << '\n'
2519        << "Total number of comparisons: " << numCmps << '\n');
2520
2521  // Compute span of values.
2522  const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2523  const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2524  APInt cmpRange = maxValue - minValue;
2525
2526  DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2527               << "Low bound: " << minValue << '\n'
2528               << "High bound: " << maxValue << '\n');
2529
2530  if (cmpRange.uge(IntPtrBits) ||
2531      (!(Dests.size() == 1 && numCmps >= 3) &&
2532       !(Dests.size() == 2 && numCmps >= 5) &&
2533       !(Dests.size() >= 3 && numCmps >= 6)))
2534    return false;
2535
2536  DEBUG(dbgs() << "Emitting bit tests\n");
2537  APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2538
2539  // Optimize the case where all the case values fit in a
2540  // word without having to subtract minValue. In this case,
2541  // we can optimize away the subtraction.
2542  if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2543    cmpRange = maxValue;
2544  } else {
2545    lowBound = minValue;
2546  }
2547
2548  CaseBitsVector CasesBits;
2549  unsigned i, count = 0;
2550
2551  for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2552    MachineBasicBlock* Dest = I->BB;
2553    for (i = 0; i < count; ++i)
2554      if (Dest == CasesBits[i].BB)
2555        break;
2556
2557    if (i == count) {
2558      assert((count < 3) && "Too much destinations to test!");
2559      CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2560      count++;
2561    }
2562
2563    const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2564    const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2565
2566    uint64_t lo = (lowValue - lowBound).getZExtValue();
2567    uint64_t hi = (highValue - lowBound).getZExtValue();
2568    CasesBits[i].ExtraWeight += I->ExtraWeight;
2569
2570    for (uint64_t j = lo; j <= hi; j++) {
2571      CasesBits[i].Mask |=  1ULL << j;
2572      CasesBits[i].Bits++;
2573    }
2574
2575  }
2576  std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2577
2578  BitTestInfo BTC;
2579
2580  // Figure out which block is immediately after the current one.
2581  MachineFunction::iterator BBI = CR.CaseBB;
2582  ++BBI;
2583
2584  const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2585
2586  DEBUG(dbgs() << "Cases:\n");
2587  for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2588    DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2589                 << ", Bits: " << CasesBits[i].Bits
2590                 << ", BB: " << CasesBits[i].BB << '\n');
2591
2592    MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2593    CurMF->insert(BBI, CaseBB);
2594    BTC.push_back(BitTestCase(CasesBits[i].Mask,
2595                              CaseBB,
2596                              CasesBits[i].BB, CasesBits[i].ExtraWeight));
2597
2598    // Put SV in a virtual register to make it available from the new blocks.
2599    ExportFromCurrentBlock(SV);
2600  }
2601
2602  BitTestBlock BTB(lowBound, cmpRange, SV,
2603                   -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2604                   CR.CaseBB, Default, BTC);
2605
2606  if (CR.CaseBB == SwitchBB)
2607    visitBitTestHeader(BTB, SwitchBB);
2608
2609  BitTestCases.push_back(BTB);
2610
2611  return true;
2612}
2613
2614/// Clusterify - Transform simple list of Cases into list of CaseRange's
2615size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2616                                       const SwitchInst& SI) {
2617  size_t numCmps = 0;
2618
2619  BranchProbabilityInfo *BPI = FuncInfo.BPI;
2620  // Start with "simple" cases
2621  for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2622       i != e; ++i) {
2623    const BasicBlock *SuccBB = i.getCaseSuccessor();
2624    MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2625
2626    uint32_t ExtraWeight =
2627      BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2628
2629    Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2630                         SMBB, ExtraWeight));
2631  }
2632  std::sort(Cases.begin(), Cases.end(), CaseCmp());
2633
2634  // Merge case into clusters
2635  if (Cases.size() >= 2)
2636    // Must recompute end() each iteration because it may be
2637    // invalidated by erase if we hold on to it
2638    for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2639         J != Cases.end(); ) {
2640      const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2641      const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2642      MachineBasicBlock* nextBB = J->BB;
2643      MachineBasicBlock* currentBB = I->BB;
2644
2645      // If the two neighboring cases go to the same destination, merge them
2646      // into a single case.
2647      if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2648        I->High = J->High;
2649        I->ExtraWeight += J->ExtraWeight;
2650        J = Cases.erase(J);
2651      } else {
2652        I = J++;
2653      }
2654    }
2655
2656  for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2657    if (I->Low != I->High)
2658      // A range counts double, since it requires two compares.
2659      ++numCmps;
2660  }
2661
2662  return numCmps;
2663}
2664
2665void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2666                                           MachineBasicBlock *Last) {
2667  // Update JTCases.
2668  for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2669    if (JTCases[i].first.HeaderBB == First)
2670      JTCases[i].first.HeaderBB = Last;
2671
2672  // Update BitTestCases.
2673  for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2674    if (BitTestCases[i].Parent == First)
2675      BitTestCases[i].Parent = Last;
2676}
2677
2678void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2679  MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2680
2681  // Figure out which block is immediately after the current one.
2682  MachineBasicBlock *NextBlock = nullptr;
2683  MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2684
2685  // If there is only the default destination, branch to it if it is not the
2686  // next basic block.  Otherwise, just fall through.
2687  if (!SI.getNumCases()) {
2688    // Update machine-CFG edges.
2689
2690    // If this is not a fall-through branch, emit the branch.
2691    SwitchMBB->addSuccessor(Default);
2692    if (Default != NextBlock)
2693      DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2694                              MVT::Other, getControlRoot(),
2695                              DAG.getBasicBlock(Default)));
2696
2697    return;
2698  }
2699
2700  // If there are any non-default case statements, create a vector of Cases
2701  // representing each one, and sort the vector so that we can efficiently
2702  // create a binary search tree from them.
2703  CaseVector Cases;
2704  size_t numCmps = Clusterify(Cases, SI);
2705  DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2706               << ". Total compares: " << numCmps << '\n');
2707  (void)numCmps;
2708
2709  // Get the Value to be switched on and default basic blocks, which will be
2710  // inserted into CaseBlock records, representing basic blocks in the binary
2711  // search tree.
2712  const Value *SV = SI.getCondition();
2713
2714  // Push the initial CaseRec onto the worklist
2715  CaseRecVector WorkList;
2716  WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2717                             CaseRange(Cases.begin(),Cases.end())));
2718
2719  while (!WorkList.empty()) {
2720    // Grab a record representing a case range to process off the worklist
2721    CaseRec CR = WorkList.back();
2722    WorkList.pop_back();
2723
2724    if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2725      continue;
2726
2727    // If the range has few cases (two or less) emit a series of specific
2728    // tests.
2729    if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2730      continue;
2731
2732    // If the switch has more than N blocks, and is at least 40% dense, and the
2733    // target supports indirect branches, then emit a jump table rather than
2734    // lowering the switch to a binary tree of conditional branches.
2735    // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2736    if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2737      continue;
2738
2739    // Emit binary tree. We need to pick a pivot, and push left and right ranges
2740    // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2741    handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2742  }
2743}
2744
2745void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2746  MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2747
2748  // Update machine-CFG edges with unique successors.
2749  SmallSet<BasicBlock*, 32> Done;
2750  for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2751    BasicBlock *BB = I.getSuccessor(i);
2752    bool Inserted = Done.insert(BB);
2753    if (!Inserted)
2754        continue;
2755
2756    MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2757    addSuccessorWithWeight(IndirectBrMBB, Succ);
2758  }
2759
2760  DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2761                          MVT::Other, getControlRoot(),
2762                          getValue(I.getAddress())));
2763}
2764
2765void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2766  if (DAG.getTarget().Options.TrapUnreachable)
2767    DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2768}
2769
2770void SelectionDAGBuilder::visitFSub(const User &I) {
2771  // -0.0 - X --> fneg
2772  Type *Ty = I.getType();
2773  if (isa<Constant>(I.getOperand(0)) &&
2774      I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2775    SDValue Op2 = getValue(I.getOperand(1));
2776    setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2777                             Op2.getValueType(), Op2));
2778    return;
2779  }
2780
2781  visitBinary(I, ISD::FSUB);
2782}
2783
2784void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2785  SDValue Op1 = getValue(I.getOperand(0));
2786  SDValue Op2 = getValue(I.getOperand(1));
2787
2788  bool nuw = false;
2789  bool nsw = false;
2790  bool exact = false;
2791  if (const OverflowingBinaryOperator *OFBinOp =
2792          dyn_cast<const OverflowingBinaryOperator>(&I)) {
2793    nuw = OFBinOp->hasNoUnsignedWrap();
2794    nsw = OFBinOp->hasNoSignedWrap();
2795  }
2796  if (const PossiblyExactOperator *ExactOp =
2797          dyn_cast<const PossiblyExactOperator>(&I))
2798    exact = ExactOp->isExact();
2799
2800  SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2801                                     Op1, Op2, nuw, nsw, exact);
2802  setValue(&I, BinNodeValue);
2803}
2804
2805void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2806  SDValue Op1 = getValue(I.getOperand(0));
2807  SDValue Op2 = getValue(I.getOperand(1));
2808
2809  EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType());
2810
2811  // Coerce the shift amount to the right type if we can.
2812  if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2813    unsigned ShiftSize = ShiftTy.getSizeInBits();
2814    unsigned Op2Size = Op2.getValueType().getSizeInBits();
2815    SDLoc DL = getCurSDLoc();
2816
2817    // If the operand is smaller than the shift count type, promote it.
2818    if (ShiftSize > Op2Size)
2819      Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2820
2821    // If the operand is larger than the shift count type but the shift
2822    // count type has enough bits to represent any shift value, truncate
2823    // it now. This is a common case and it exposes the truncate to
2824    // optimization early.
2825    else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2826      Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2827    // Otherwise we'll need to temporarily settle for some other convenient
2828    // type.  Type legalization will make adjustments once the shiftee is split.
2829    else
2830      Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2831  }
2832
2833  bool nuw = false;
2834  bool nsw = false;
2835  bool exact = false;
2836
2837  if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2838
2839    if (const OverflowingBinaryOperator *OFBinOp =
2840            dyn_cast<const OverflowingBinaryOperator>(&I)) {
2841      nuw = OFBinOp->hasNoUnsignedWrap();
2842      nsw = OFBinOp->hasNoSignedWrap();
2843    }
2844    if (const PossiblyExactOperator *ExactOp =
2845            dyn_cast<const PossiblyExactOperator>(&I))
2846      exact = ExactOp->isExact();
2847  }
2848
2849  SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2850                            nuw, nsw, exact);
2851  setValue(&I, Res);
2852}
2853
2854void SelectionDAGBuilder::visitSDiv(const User &I) {
2855  SDValue Op1 = getValue(I.getOperand(0));
2856  SDValue Op2 = getValue(I.getOperand(1));
2857
2858  // Turn exact SDivs into multiplications.
2859  // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2860  // exact bit.
2861  if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2862      !isa<ConstantSDNode>(Op1) &&
2863      isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2864    setValue(&I, TM.getTargetLowering()->BuildExactSDIV(Op1, Op2,
2865                                                        getCurSDLoc(), DAG));
2866  else
2867    setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2868                             Op1, Op2));
2869}
2870
2871void SelectionDAGBuilder::visitICmp(const User &I) {
2872  ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2873  if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2874    predicate = IC->getPredicate();
2875  else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2876    predicate = ICmpInst::Predicate(IC->getPredicate());
2877  SDValue Op1 = getValue(I.getOperand(0));
2878  SDValue Op2 = getValue(I.getOperand(1));
2879  ISD::CondCode Opcode = getICmpCondCode(predicate);
2880
2881  EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2882  setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2883}
2884
2885void SelectionDAGBuilder::visitFCmp(const User &I) {
2886  FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2887  if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2888    predicate = FC->getPredicate();
2889  else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2890    predicate = FCmpInst::Predicate(FC->getPredicate());
2891  SDValue Op1 = getValue(I.getOperand(0));
2892  SDValue Op2 = getValue(I.getOperand(1));
2893  ISD::CondCode Condition = getFCmpCondCode(predicate);
2894  if (TM.Options.NoNaNsFPMath)
2895    Condition = getFCmpCodeWithoutNaN(Condition);
2896  EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2897  setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2898}
2899
2900void SelectionDAGBuilder::visitSelect(const User &I) {
2901  SmallVector<EVT, 4> ValueVTs;
2902  ComputeValueVTs(*TM.getTargetLowering(), I.getType(), ValueVTs);
2903  unsigned NumValues = ValueVTs.size();
2904  if (NumValues == 0) return;
2905
2906  SmallVector<SDValue, 4> Values(NumValues);
2907  SDValue Cond     = getValue(I.getOperand(0));
2908  SDValue TrueVal  = getValue(I.getOperand(1));
2909  SDValue FalseVal = getValue(I.getOperand(2));
2910  ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2911    ISD::VSELECT : ISD::SELECT;
2912
2913  for (unsigned i = 0; i != NumValues; ++i)
2914    Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2915                            TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2916                            Cond,
2917                            SDValue(TrueVal.getNode(),
2918                                    TrueVal.getResNo() + i),
2919                            SDValue(FalseVal.getNode(),
2920                                    FalseVal.getResNo() + i));
2921
2922  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2923                           DAG.getVTList(ValueVTs), Values));
2924}
2925
2926void SelectionDAGBuilder::visitTrunc(const User &I) {
2927  // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2928  SDValue N = getValue(I.getOperand(0));
2929  EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2930  setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2931}
2932
2933void SelectionDAGBuilder::visitZExt(const User &I) {
2934  // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2935  // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2936  SDValue N = getValue(I.getOperand(0));
2937  EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2938  setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2939}
2940
2941void SelectionDAGBuilder::visitSExt(const User &I) {
2942  // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2943  // SExt also can't be a cast to bool for same reason. So, nothing much to do
2944  SDValue N = getValue(I.getOperand(0));
2945  EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2946  setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2947}
2948
2949void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2950  // FPTrunc is never a no-op cast, no need to check
2951  SDValue N = getValue(I.getOperand(0));
2952  const TargetLowering *TLI = TM.getTargetLowering();
2953  EVT DestVT = TLI->getValueType(I.getType());
2954  setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(),
2955                           DestVT, N,
2956                           DAG.getTargetConstant(0, TLI->getPointerTy())));
2957}
2958
2959void SelectionDAGBuilder::visitFPExt(const User &I) {
2960  // FPExt is never a no-op cast, no need to check
2961  SDValue N = getValue(I.getOperand(0));
2962  EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2963  setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2964}
2965
2966void SelectionDAGBuilder::visitFPToUI(const User &I) {
2967  // FPToUI is never a no-op cast, no need to check
2968  SDValue N = getValue(I.getOperand(0));
2969  EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2970  setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2971}
2972
2973void SelectionDAGBuilder::visitFPToSI(const User &I) {
2974  // FPToSI is never a no-op cast, no need to check
2975  SDValue N = getValue(I.getOperand(0));
2976  EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2977  setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2978}
2979
2980void SelectionDAGBuilder::visitUIToFP(const User &I) {
2981  // UIToFP is never a no-op cast, no need to check
2982  SDValue N = getValue(I.getOperand(0));
2983  EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2984  setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2985}
2986
2987void SelectionDAGBuilder::visitSIToFP(const User &I) {
2988  // SIToFP is never a no-op cast, no need to check
2989  SDValue N = getValue(I.getOperand(0));
2990  EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2991  setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2992}
2993
2994void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2995  // What to do depends on the size of the integer and the size of the pointer.
2996  // We can either truncate, zero extend, or no-op, accordingly.
2997  SDValue N = getValue(I.getOperand(0));
2998  EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2999  setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3000}
3001
3002void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3003  // What to do depends on the size of the integer and the size of the pointer.
3004  // We can either truncate, zero extend, or no-op, accordingly.
3005  SDValue N = getValue(I.getOperand(0));
3006  EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
3007  setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3008}
3009
3010void SelectionDAGBuilder::visitBitCast(const User &I) {
3011  SDValue N = getValue(I.getOperand(0));
3012  EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
3013
3014  // BitCast assures us that source and destination are the same size so this is
3015  // either a BITCAST or a no-op.
3016  if (DestVT != N.getValueType())
3017    setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3018                             DestVT, N)); // convert types.
3019  // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3020  // might fold any kind of constant expression to an integer constant and that
3021  // is not what we are looking for. Only regcognize a bitcast of a genuine
3022  // constant integer as an opaque constant.
3023  else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3024    setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3025                                 /*isOpaque*/true));
3026  else
3027    setValue(&I, N);            // noop cast.
3028}
3029
3030void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3031  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3032  const Value *SV = I.getOperand(0);
3033  SDValue N = getValue(SV);
3034  EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
3035
3036  unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3037  unsigned DestAS = I.getType()->getPointerAddressSpace();
3038
3039  if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3040    N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3041
3042  setValue(&I, N);
3043}
3044
3045void SelectionDAGBuilder::visitInsertElement(const User &I) {
3046  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3047  SDValue InVec = getValue(I.getOperand(0));
3048  SDValue InVal = getValue(I.getOperand(1));
3049  SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3050                                     getCurSDLoc(), TLI.getVectorIdxTy());
3051  setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3052                           TM.getTargetLowering()->getValueType(I.getType()),
3053                           InVec, InVal, InIdx));
3054}
3055
3056void SelectionDAGBuilder::visitExtractElement(const User &I) {
3057  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3058  SDValue InVec = getValue(I.getOperand(0));
3059  SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3060                                     getCurSDLoc(), TLI.getVectorIdxTy());
3061  setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3062                           TM.getTargetLowering()->getValueType(I.getType()),
3063                           InVec, InIdx));
3064}
3065
3066// Utility for visitShuffleVector - Return true if every element in Mask,
3067// beginning from position Pos and ending in Pos+Size, falls within the
3068// specified sequential range [L, L+Pos). or is undef.
3069static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3070                                unsigned Pos, unsigned Size, int Low) {
3071  for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3072    if (Mask[i] >= 0 && Mask[i] != Low)
3073      return false;
3074  return true;
3075}
3076
3077void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3078  SDValue Src1 = getValue(I.getOperand(0));
3079  SDValue Src2 = getValue(I.getOperand(1));
3080
3081  SmallVector<int, 8> Mask;
3082  ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3083  unsigned MaskNumElts = Mask.size();
3084
3085  const TargetLowering *TLI = TM.getTargetLowering();
3086  EVT VT = TLI->getValueType(I.getType());
3087  EVT SrcVT = Src1.getValueType();
3088  unsigned SrcNumElts = SrcVT.getVectorNumElements();
3089
3090  if (SrcNumElts == MaskNumElts) {
3091    setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3092                                      &Mask[0]));
3093    return;
3094  }
3095
3096  // Normalize the shuffle vector since mask and vector length don't match.
3097  if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3098    // Mask is longer than the source vectors and is a multiple of the source
3099    // vectors.  We can use concatenate vector to make the mask and vectors
3100    // lengths match.
3101    if (SrcNumElts*2 == MaskNumElts) {
3102      // First check for Src1 in low and Src2 in high
3103      if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3104          isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3105        // The shuffle is concatenating two vectors together.
3106        setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3107                                 VT, Src1, Src2));
3108        return;
3109      }
3110      // Then check for Src2 in low and Src1 in high
3111      if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3112          isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3113        // The shuffle is concatenating two vectors together.
3114        setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3115                                 VT, Src2, Src1));
3116        return;
3117      }
3118    }
3119
3120    // Pad both vectors with undefs to make them the same length as the mask.
3121    unsigned NumConcat = MaskNumElts / SrcNumElts;
3122    bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3123    bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3124    SDValue UndefVal = DAG.getUNDEF(SrcVT);
3125
3126    SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3127    SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3128    MOps1[0] = Src1;
3129    MOps2[0] = Src2;
3130
3131    Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3132                                                  getCurSDLoc(), VT, MOps1);
3133    Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3134                                                  getCurSDLoc(), VT, MOps2);
3135
3136    // Readjust mask for new input vector length.
3137    SmallVector<int, 8> MappedOps;
3138    for (unsigned i = 0; i != MaskNumElts; ++i) {
3139      int Idx = Mask[i];
3140      if (Idx >= (int)SrcNumElts)
3141        Idx -= SrcNumElts - MaskNumElts;
3142      MappedOps.push_back(Idx);
3143    }
3144
3145    setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3146                                      &MappedOps[0]));
3147    return;
3148  }
3149
3150  if (SrcNumElts > MaskNumElts) {
3151    // Analyze the access pattern of the vector to see if we can extract
3152    // two subvectors and do the shuffle. The analysis is done by calculating
3153    // the range of elements the mask access on both vectors.
3154    int MinRange[2] = { static_cast<int>(SrcNumElts),
3155                        static_cast<int>(SrcNumElts)};
3156    int MaxRange[2] = {-1, -1};
3157
3158    for (unsigned i = 0; i != MaskNumElts; ++i) {
3159      int Idx = Mask[i];
3160      unsigned Input = 0;
3161      if (Idx < 0)
3162        continue;
3163
3164      if (Idx >= (int)SrcNumElts) {
3165        Input = 1;
3166        Idx -= SrcNumElts;
3167      }
3168      if (Idx > MaxRange[Input])
3169        MaxRange[Input] = Idx;
3170      if (Idx < MinRange[Input])
3171        MinRange[Input] = Idx;
3172    }
3173
3174    // Check if the access is smaller than the vector size and can we find
3175    // a reasonable extract index.
3176    int RangeUse[2] = { -1, -1 };  // 0 = Unused, 1 = Extract, -1 = Can not
3177                                   // Extract.
3178    int StartIdx[2];  // StartIdx to extract from
3179    for (unsigned Input = 0; Input < 2; ++Input) {
3180      if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3181        RangeUse[Input] = 0; // Unused
3182        StartIdx[Input] = 0;
3183        continue;
3184      }
3185
3186      // Find a good start index that is a multiple of the mask length. Then
3187      // see if the rest of the elements are in range.
3188      StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3189      if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3190          StartIdx[Input] + MaskNumElts <= SrcNumElts)
3191        RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3192    }
3193
3194    if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3195      setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3196      return;
3197    }
3198    if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3199      // Extract appropriate subvector and generate a vector shuffle
3200      for (unsigned Input = 0; Input < 2; ++Input) {
3201        SDValue &Src = Input == 0 ? Src1 : Src2;
3202        if (RangeUse[Input] == 0)
3203          Src = DAG.getUNDEF(VT);
3204        else
3205          Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT,
3206                            Src, DAG.getConstant(StartIdx[Input],
3207                                                 TLI->getVectorIdxTy()));
3208      }
3209
3210      // Calculate new mask.
3211      SmallVector<int, 8> MappedOps;
3212      for (unsigned i = 0; i != MaskNumElts; ++i) {
3213        int Idx = Mask[i];
3214        if (Idx >= 0) {
3215          if (Idx < (int)SrcNumElts)
3216            Idx -= StartIdx[0];
3217          else
3218            Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3219        }
3220        MappedOps.push_back(Idx);
3221      }
3222
3223      setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3224                                        &MappedOps[0]));
3225      return;
3226    }
3227  }
3228
3229  // We can't use either concat vectors or extract subvectors so fall back to
3230  // replacing the shuffle with extract and build vector.
3231  // to insert and build vector.
3232  EVT EltVT = VT.getVectorElementType();
3233  EVT IdxVT = TLI->getVectorIdxTy();
3234  SmallVector<SDValue,8> Ops;
3235  for (unsigned i = 0; i != MaskNumElts; ++i) {
3236    int Idx = Mask[i];
3237    SDValue Res;
3238
3239    if (Idx < 0) {
3240      Res = DAG.getUNDEF(EltVT);
3241    } else {
3242      SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3243      if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3244
3245      Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3246                        EltVT, Src, DAG.getConstant(Idx, IdxVT));
3247    }
3248
3249    Ops.push_back(Res);
3250  }
3251
3252  setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3253}
3254
3255void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3256  const Value *Op0 = I.getOperand(0);
3257  const Value *Op1 = I.getOperand(1);
3258  Type *AggTy = I.getType();
3259  Type *ValTy = Op1->getType();
3260  bool IntoUndef = isa<UndefValue>(Op0);
3261  bool FromUndef = isa<UndefValue>(Op1);
3262
3263  unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3264
3265  const TargetLowering *TLI = TM.getTargetLowering();
3266  SmallVector<EVT, 4> AggValueVTs;
3267  ComputeValueVTs(*TLI, AggTy, AggValueVTs);
3268  SmallVector<EVT, 4> ValValueVTs;
3269  ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3270
3271  unsigned NumAggValues = AggValueVTs.size();
3272  unsigned NumValValues = ValValueVTs.size();
3273  SmallVector<SDValue, 4> Values(NumAggValues);
3274
3275  SDValue Agg = getValue(Op0);
3276  unsigned i = 0;
3277  // Copy the beginning value(s) from the original aggregate.
3278  for (; i != LinearIndex; ++i)
3279    Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3280                SDValue(Agg.getNode(), Agg.getResNo() + i);
3281  // Copy values from the inserted value(s).
3282  if (NumValValues) {
3283    SDValue Val = getValue(Op1);
3284    for (; i != LinearIndex + NumValValues; ++i)
3285      Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3286                  SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3287  }
3288  // Copy remaining value(s) from the original aggregate.
3289  for (; i != NumAggValues; ++i)
3290    Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3291                SDValue(Agg.getNode(), Agg.getResNo() + i);
3292
3293  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3294                           DAG.getVTList(AggValueVTs), Values));
3295}
3296
3297void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3298  const Value *Op0 = I.getOperand(0);
3299  Type *AggTy = Op0->getType();
3300  Type *ValTy = I.getType();
3301  bool OutOfUndef = isa<UndefValue>(Op0);
3302
3303  unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3304
3305  const TargetLowering *TLI = TM.getTargetLowering();
3306  SmallVector<EVT, 4> ValValueVTs;
3307  ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3308
3309  unsigned NumValValues = ValValueVTs.size();
3310
3311  // Ignore a extractvalue that produces an empty object
3312  if (!NumValValues) {
3313    setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3314    return;
3315  }
3316
3317  SmallVector<SDValue, 4> Values(NumValValues);
3318
3319  SDValue Agg = getValue(Op0);
3320  // Copy out the selected value(s).
3321  for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3322    Values[i - LinearIndex] =
3323      OutOfUndef ?
3324        DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3325        SDValue(Agg.getNode(), Agg.getResNo() + i);
3326
3327  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3328                           DAG.getVTList(ValValueVTs), Values));
3329}
3330
3331void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3332  Value *Op0 = I.getOperand(0);
3333  // Note that the pointer operand may be a vector of pointers. Take the scalar
3334  // element which holds a pointer.
3335  Type *Ty = Op0->getType()->getScalarType();
3336  unsigned AS = Ty->getPointerAddressSpace();
3337  SDValue N = getValue(Op0);
3338
3339  for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3340       OI != E; ++OI) {
3341    const Value *Idx = *OI;
3342    if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3343      unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3344      if (Field) {
3345        // N = N + Offset
3346        uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3347        N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3348                        DAG.getConstant(Offset, N.getValueType()));
3349      }
3350
3351      Ty = StTy->getElementType(Field);
3352    } else {
3353      Ty = cast<SequentialType>(Ty)->getElementType();
3354
3355      // If this is a constant subscript, handle it quickly.
3356      const TargetLowering *TLI = TM.getTargetLowering();
3357      if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3358        if (CI->isZero()) continue;
3359        uint64_t Offs =
3360            DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3361        SDValue OffsVal;
3362        EVT PTy = TLI->getPointerTy(AS);
3363        unsigned PtrBits = PTy.getSizeInBits();
3364        if (PtrBits < 64)
3365          OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3366                                DAG.getConstant(Offs, MVT::i64));
3367        else
3368          OffsVal = DAG.getConstant(Offs, PTy);
3369
3370        N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3371                        OffsVal);
3372        continue;
3373      }
3374
3375      // N = N + Idx * ElementSize;
3376      APInt ElementSize = APInt(TLI->getPointerSizeInBits(AS),
3377                                DL->getTypeAllocSize(Ty));
3378      SDValue IdxN = getValue(Idx);
3379
3380      // If the index is smaller or larger than intptr_t, truncate or extend
3381      // it.
3382      IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3383
3384      // If this is a multiply by a power of two, turn it into a shl
3385      // immediately.  This is a very common case.
3386      if (ElementSize != 1) {
3387        if (ElementSize.isPowerOf2()) {
3388          unsigned Amt = ElementSize.logBase2();
3389          IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3390                             N.getValueType(), IdxN,
3391                             DAG.getConstant(Amt, IdxN.getValueType()));
3392        } else {
3393          SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3394          IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3395                             N.getValueType(), IdxN, Scale);
3396        }
3397      }
3398
3399      N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3400                      N.getValueType(), N, IdxN);
3401    }
3402  }
3403
3404  setValue(&I, N);
3405}
3406
3407void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3408  // If this is a fixed sized alloca in the entry block of the function,
3409  // allocate it statically on the stack.
3410  if (FuncInfo.StaticAllocaMap.count(&I))
3411    return;   // getValue will auto-populate this.
3412
3413  Type *Ty = I.getAllocatedType();
3414  const TargetLowering *TLI = TM.getTargetLowering();
3415  uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
3416  unsigned Align =
3417    std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
3418             I.getAlignment());
3419
3420  SDValue AllocSize = getValue(I.getArraySize());
3421
3422  EVT IntPtr = TLI->getPointerTy();
3423  if (AllocSize.getValueType() != IntPtr)
3424    AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3425
3426  AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3427                          AllocSize,
3428                          DAG.getConstant(TySize, IntPtr));
3429
3430  // Handle alignment.  If the requested alignment is less than or equal to
3431  // the stack alignment, ignore it.  If the size is greater than or equal to
3432  // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3433  unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3434  if (Align <= StackAlign)
3435    Align = 0;
3436
3437  // Round the size of the allocation up to the stack alignment size
3438  // by add SA-1 to the size.
3439  AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3440                          AllocSize.getValueType(), AllocSize,
3441                          DAG.getIntPtrConstant(StackAlign-1));
3442
3443  // Mask out the low bits for alignment purposes.
3444  AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3445                          AllocSize.getValueType(), AllocSize,
3446                          DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3447
3448  SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3449  SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3450  SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3451  setValue(&I, DSA);
3452  DAG.setRoot(DSA.getValue(1));
3453
3454  assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3455}
3456
3457void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3458  if (I.isAtomic())
3459    return visitAtomicLoad(I);
3460
3461  const Value *SV = I.getOperand(0);
3462  SDValue Ptr = getValue(SV);
3463
3464  Type *Ty = I.getType();
3465
3466  bool isVolatile = I.isVolatile();
3467  bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3468  bool isInvariant = I.getMetadata("invariant.load") != nullptr;
3469  unsigned Alignment = I.getAlignment();
3470  const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3471  const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3472
3473  SmallVector<EVT, 4> ValueVTs;
3474  SmallVector<uint64_t, 4> Offsets;
3475  ComputeValueVTs(*TM.getTargetLowering(), Ty, ValueVTs, &Offsets);
3476  unsigned NumValues = ValueVTs.size();
3477  if (NumValues == 0)
3478    return;
3479
3480  SDValue Root;
3481  bool ConstantMemory = false;
3482  if (isVolatile || NumValues > MaxParallelChains)
3483    // Serialize volatile loads with other side effects.
3484    Root = getRoot();
3485  else if (AA->pointsToConstantMemory(
3486             AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3487    // Do not serialize (non-volatile) loads of constant memory with anything.
3488    Root = DAG.getEntryNode();
3489    ConstantMemory = true;
3490  } else {
3491    // Do not serialize non-volatile loads against each other.
3492    Root = DAG.getRoot();
3493  }
3494
3495  const TargetLowering *TLI = TM.getTargetLowering();
3496  if (isVolatile)
3497    Root = TLI->prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3498
3499  SmallVector<SDValue, 4> Values(NumValues);
3500  SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3501                                          NumValues));
3502  EVT PtrVT = Ptr.getValueType();
3503  unsigned ChainI = 0;
3504  for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3505    // Serializing loads here may result in excessive register pressure, and
3506    // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3507    // could recover a bit by hoisting nodes upward in the chain by recognizing
3508    // they are side-effect free or do not alias. The optimizer should really
3509    // avoid this case by converting large object/array copies to llvm.memcpy
3510    // (MaxParallelChains should always remain as failsafe).
3511    if (ChainI == MaxParallelChains) {
3512      assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3513      SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3514                                  makeArrayRef(Chains.data(), ChainI));
3515      Root = Chain;
3516      ChainI = 0;
3517    }
3518    SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3519                            PtrVT, Ptr,
3520                            DAG.getConstant(Offsets[i], PtrVT));
3521    SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3522                            A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3523                            isNonTemporal, isInvariant, Alignment, TBAAInfo,
3524                            Ranges);
3525
3526    Values[i] = L;
3527    Chains[ChainI] = L.getValue(1);
3528  }
3529
3530  if (!ConstantMemory) {
3531    SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3532                                makeArrayRef(Chains.data(), ChainI));
3533    if (isVolatile)
3534      DAG.setRoot(Chain);
3535    else
3536      PendingLoads.push_back(Chain);
3537  }
3538
3539  setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3540                           DAG.getVTList(ValueVTs), Values));
3541}
3542
3543void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3544  if (I.isAtomic())
3545    return visitAtomicStore(I);
3546
3547  const Value *SrcV = I.getOperand(0);
3548  const Value *PtrV = I.getOperand(1);
3549
3550  SmallVector<EVT, 4> ValueVTs;
3551  SmallVector<uint64_t, 4> Offsets;
3552  ComputeValueVTs(*TM.getTargetLowering(), SrcV->getType(), ValueVTs, &Offsets);
3553  unsigned NumValues = ValueVTs.size();
3554  if (NumValues == 0)
3555    return;
3556
3557  // Get the lowered operands. Note that we do this after
3558  // checking if NumResults is zero, because with zero results
3559  // the operands won't have values in the map.
3560  SDValue Src = getValue(SrcV);
3561  SDValue Ptr = getValue(PtrV);
3562
3563  SDValue Root = getRoot();
3564  SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3565                                          NumValues));
3566  EVT PtrVT = Ptr.getValueType();
3567  bool isVolatile = I.isVolatile();
3568  bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3569  unsigned Alignment = I.getAlignment();
3570  const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3571
3572  unsigned ChainI = 0;
3573  for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3574    // See visitLoad comments.
3575    if (ChainI == MaxParallelChains) {
3576      SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3577                                  makeArrayRef(Chains.data(), ChainI));
3578      Root = Chain;
3579      ChainI = 0;
3580    }
3581    SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3582                              DAG.getConstant(Offsets[i], PtrVT));
3583    SDValue St = DAG.getStore(Root, getCurSDLoc(),
3584                              SDValue(Src.getNode(), Src.getResNo() + i),
3585                              Add, MachinePointerInfo(PtrV, Offsets[i]),
3586                              isVolatile, isNonTemporal, Alignment, TBAAInfo);
3587    Chains[ChainI] = St;
3588  }
3589
3590  SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3591                                  makeArrayRef(Chains.data(), ChainI));
3592  DAG.setRoot(StoreNode);
3593}
3594
3595static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3596                                    SynchronizationScope Scope,
3597                                    bool Before, SDLoc dl,
3598                                    SelectionDAG &DAG,
3599                                    const TargetLowering &TLI) {
3600  // Fence, if necessary
3601  if (Before) {
3602    if (Order == AcquireRelease || Order == SequentiallyConsistent)
3603      Order = Release;
3604    else if (Order == Acquire || Order == Monotonic || Order == Unordered)
3605      return Chain;
3606  } else {
3607    if (Order == AcquireRelease)
3608      Order = Acquire;
3609    else if (Order == Release || Order == Monotonic || Order == Unordered)
3610      return Chain;
3611  }
3612  SDValue Ops[3];
3613  Ops[0] = Chain;
3614  Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3615  Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3616  return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops);
3617}
3618
3619void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3620  SDLoc dl = getCurSDLoc();
3621  AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3622  AtomicOrdering FailureOrder = I.getFailureOrdering();
3623  SynchronizationScope Scope = I.getSynchScope();
3624
3625  SDValue InChain = getRoot();
3626
3627  const TargetLowering *TLI = TM.getTargetLowering();
3628  if (TLI->getInsertFencesForAtomic())
3629    InChain = InsertFenceForAtomic(InChain, SuccessOrder, Scope, true, dl,
3630                                   DAG, *TLI);
3631
3632  MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3633  SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3634  SDValue L = DAG.getAtomicCmpSwap(
3635      ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3636      getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3637      getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3638      0 /* Alignment */,
3639      TLI->getInsertFencesForAtomic() ? Monotonic : SuccessOrder,
3640      TLI->getInsertFencesForAtomic() ? Monotonic : FailureOrder, Scope);
3641
3642  SDValue OutChain = L.getValue(2);
3643
3644  if (TLI->getInsertFencesForAtomic())
3645    OutChain = InsertFenceForAtomic(OutChain, SuccessOrder, Scope, false, dl,
3646                                    DAG, *TLI);
3647
3648  setValue(&I, L);
3649  DAG.setRoot(OutChain);
3650}
3651
3652void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3653  SDLoc dl = getCurSDLoc();
3654  ISD::NodeType NT;
3655  switch (I.getOperation()) {
3656  default: llvm_unreachable("Unknown atomicrmw operation");
3657  case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3658  case AtomicRMWInst::Add:  NT = ISD::ATOMIC_LOAD_ADD; break;
3659  case AtomicRMWInst::Sub:  NT = ISD::ATOMIC_LOAD_SUB; break;
3660  case AtomicRMWInst::And:  NT = ISD::ATOMIC_LOAD_AND; break;
3661  case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3662  case AtomicRMWInst::Or:   NT = ISD::ATOMIC_LOAD_OR; break;
3663  case AtomicRMWInst::Xor:  NT = ISD::ATOMIC_LOAD_XOR; break;
3664  case AtomicRMWInst::Max:  NT = ISD::ATOMIC_LOAD_MAX; break;
3665  case AtomicRMWInst::Min:  NT = ISD::ATOMIC_LOAD_MIN; break;
3666  case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3667  case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3668  }
3669  AtomicOrdering Order = I.getOrdering();
3670  SynchronizationScope Scope = I.getSynchScope();
3671
3672  SDValue InChain = getRoot();
3673
3674  const TargetLowering *TLI = TM.getTargetLowering();
3675  if (TLI->getInsertFencesForAtomic())
3676    InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3677                                   DAG, *TLI);
3678
3679  SDValue L =
3680    DAG.getAtomic(NT, dl,
3681                  getValue(I.getValOperand()).getSimpleValueType(),
3682                  InChain,
3683                  getValue(I.getPointerOperand()),
3684                  getValue(I.getValOperand()),
3685                  I.getPointerOperand(), 0 /* Alignment */,
3686                  TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3687                  Scope);
3688
3689  SDValue OutChain = L.getValue(1);
3690
3691  if (TLI->getInsertFencesForAtomic())
3692    OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3693                                    DAG, *TLI);
3694
3695  setValue(&I, L);
3696  DAG.setRoot(OutChain);
3697}
3698
3699void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3700  SDLoc dl = getCurSDLoc();
3701  const TargetLowering *TLI = TM.getTargetLowering();
3702  SDValue Ops[3];
3703  Ops[0] = getRoot();
3704  Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy());
3705  Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy());
3706  DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3707}
3708
3709void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3710  SDLoc dl = getCurSDLoc();
3711  AtomicOrdering Order = I.getOrdering();
3712  SynchronizationScope Scope = I.getSynchScope();
3713
3714  SDValue InChain = getRoot();
3715
3716  const TargetLowering *TLI = TM.getTargetLowering();
3717  EVT VT = TLI->getValueType(I.getType());
3718
3719  if (I.getAlignment() < VT.getSizeInBits() / 8)
3720    report_fatal_error("Cannot generate unaligned atomic load");
3721
3722  MachineMemOperand *MMO =
3723      DAG.getMachineFunction().
3724      getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3725                           MachineMemOperand::MOVolatile |
3726                           MachineMemOperand::MOLoad,
3727                           VT.getStoreSize(),
3728                           I.getAlignment() ? I.getAlignment() :
3729                                              DAG.getEVTAlignment(VT));
3730
3731  InChain = TLI->prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3732  SDValue L =
3733      DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3734                    getValue(I.getPointerOperand()), MMO,
3735                    TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3736                    Scope);
3737
3738  SDValue OutChain = L.getValue(1);
3739
3740  if (TLI->getInsertFencesForAtomic())
3741    OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3742                                    DAG, *TLI);
3743
3744  setValue(&I, L);
3745  DAG.setRoot(OutChain);
3746}
3747
3748void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3749  SDLoc dl = getCurSDLoc();
3750
3751  AtomicOrdering Order = I.getOrdering();
3752  SynchronizationScope Scope = I.getSynchScope();
3753
3754  SDValue InChain = getRoot();
3755
3756  const TargetLowering *TLI = TM.getTargetLowering();
3757  EVT VT = TLI->getValueType(I.getValueOperand()->getType());
3758
3759  if (I.getAlignment() < VT.getSizeInBits() / 8)
3760    report_fatal_error("Cannot generate unaligned atomic store");
3761
3762  if (TLI->getInsertFencesForAtomic())
3763    InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3764                                   DAG, *TLI);
3765
3766  SDValue OutChain =
3767    DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3768                  InChain,
3769                  getValue(I.getPointerOperand()),
3770                  getValue(I.getValueOperand()),
3771                  I.getPointerOperand(), I.getAlignment(),
3772                  TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3773                  Scope);
3774
3775  if (TLI->getInsertFencesForAtomic())
3776    OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3777                                    DAG, *TLI);
3778
3779  DAG.setRoot(OutChain);
3780}
3781
3782/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3783/// node.
3784void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3785                                               unsigned Intrinsic) {
3786  bool HasChain = !I.doesNotAccessMemory();
3787  bool OnlyLoad = HasChain && I.onlyReadsMemory();
3788
3789  // Build the operand list.
3790  SmallVector<SDValue, 8> Ops;
3791  if (HasChain) {  // If this intrinsic has side-effects, chainify it.
3792    if (OnlyLoad) {
3793      // We don't need to serialize loads against other loads.
3794      Ops.push_back(DAG.getRoot());
3795    } else {
3796      Ops.push_back(getRoot());
3797    }
3798  }
3799
3800  // Info is set by getTgtMemInstrinsic
3801  TargetLowering::IntrinsicInfo Info;
3802  const TargetLowering *TLI = TM.getTargetLowering();
3803  bool IsTgtIntrinsic = TLI->getTgtMemIntrinsic(Info, I, Intrinsic);
3804
3805  // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3806  if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3807      Info.opc == ISD::INTRINSIC_W_CHAIN)
3808    Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI->getPointerTy()));
3809
3810  // Add all operands of the call to the operand list.
3811  for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3812    SDValue Op = getValue(I.getArgOperand(i));
3813    Ops.push_back(Op);
3814  }
3815
3816  SmallVector<EVT, 4> ValueVTs;
3817  ComputeValueVTs(*TLI, I.getType(), ValueVTs);
3818
3819  if (HasChain)
3820    ValueVTs.push_back(MVT::Other);
3821
3822  SDVTList VTs = DAG.getVTList(ValueVTs);
3823
3824  // Create the node.
3825  SDValue Result;
3826  if (IsTgtIntrinsic) {
3827    // This is target intrinsic that touches memory
3828    Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3829                                     VTs, Ops, Info.memVT,
3830                                   MachinePointerInfo(Info.ptrVal, Info.offset),
3831                                     Info.align, Info.vol,
3832                                     Info.readMem, Info.writeMem);
3833  } else if (!HasChain) {
3834    Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3835  } else if (!I.getType()->isVoidTy()) {
3836    Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3837  } else {
3838    Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3839  }
3840
3841  if (HasChain) {
3842    SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3843    if (OnlyLoad)
3844      PendingLoads.push_back(Chain);
3845    else
3846      DAG.setRoot(Chain);
3847  }
3848
3849  if (!I.getType()->isVoidTy()) {
3850    if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3851      EVT VT = TLI->getValueType(PTy);
3852      Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3853    }
3854
3855    setValue(&I, Result);
3856  }
3857}
3858
3859/// GetSignificand - Get the significand and build it into a floating-point
3860/// number with exponent of 1:
3861///
3862///   Op = (Op & 0x007fffff) | 0x3f800000;
3863///
3864/// where Op is the hexadecimal representation of floating point value.
3865static SDValue
3866GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3867  SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3868                           DAG.getConstant(0x007fffff, MVT::i32));
3869  SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3870                           DAG.getConstant(0x3f800000, MVT::i32));
3871  return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3872}
3873
3874/// GetExponent - Get the exponent:
3875///
3876///   (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3877///
3878/// where Op is the hexadecimal representation of floating point value.
3879static SDValue
3880GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3881            SDLoc dl) {
3882  SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3883                           DAG.getConstant(0x7f800000, MVT::i32));
3884  SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3885                           DAG.getConstant(23, TLI.getPointerTy()));
3886  SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3887                           DAG.getConstant(127, MVT::i32));
3888  return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3889}
3890
3891/// getF32Constant - Get 32-bit floating point constant.
3892static SDValue
3893getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3894  return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3895                           MVT::f32);
3896}
3897
3898/// expandExp - Lower an exp intrinsic. Handles the special sequences for
3899/// limited-precision mode.
3900static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3901                         const TargetLowering &TLI) {
3902  if (Op.getValueType() == MVT::f32 &&
3903      LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3904
3905    // Put the exponent in the right bit position for later addition to the
3906    // final result:
3907    //
3908    //   #define LOG2OFe 1.4426950f
3909    //   IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3910    SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3911                             getF32Constant(DAG, 0x3fb8aa3b));
3912    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3913
3914    //   FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3915    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3916    SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3917
3918    //   IntegerPartOfX <<= 23;
3919    IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3920                                 DAG.getConstant(23, TLI.getPointerTy()));
3921
3922    SDValue TwoToFracPartOfX;
3923    if (LimitFloatPrecision <= 6) {
3924      // For floating-point precision of 6:
3925      //
3926      //   TwoToFractionalPartOfX =
3927      //     0.997535578f +
3928      //       (0.735607626f + 0.252464424f * x) * x;
3929      //
3930      // error 0.0144103317, which is 6 bits
3931      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3932                               getF32Constant(DAG, 0x3e814304));
3933      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3934                               getF32Constant(DAG, 0x3f3c50c8));
3935      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3936      TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3937                                     getF32Constant(DAG, 0x3f7f5e7e));
3938    } else if (LimitFloatPrecision <= 12) {
3939      // For floating-point precision of 12:
3940      //
3941      //   TwoToFractionalPartOfX =
3942      //     0.999892986f +
3943      //       (0.696457318f +
3944      //         (0.224338339f + 0.792043434e-1f * x) * x) * x;
3945      //
3946      // 0.000107046256 error, which is 13 to 14 bits
3947      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3948                               getF32Constant(DAG, 0x3da235e3));
3949      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3950                               getF32Constant(DAG, 0x3e65b8f3));
3951      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3952      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3953                               getF32Constant(DAG, 0x3f324b07));
3954      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3955      TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3956                                     getF32Constant(DAG, 0x3f7ff8fd));
3957    } else { // LimitFloatPrecision <= 18
3958      // For floating-point precision of 18:
3959      //
3960      //   TwoToFractionalPartOfX =
3961      //     0.999999982f +
3962      //       (0.693148872f +
3963      //         (0.240227044f +
3964      //           (0.554906021e-1f +
3965      //             (0.961591928e-2f +
3966      //               (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3967      //
3968      // error 2.47208000*10^(-7), which is better than 18 bits
3969      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3970                               getF32Constant(DAG, 0x3924b03e));
3971      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3972                               getF32Constant(DAG, 0x3ab24b87));
3973      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3974      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3975                               getF32Constant(DAG, 0x3c1d8c17));
3976      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3977      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3978                               getF32Constant(DAG, 0x3d634a1d));
3979      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3980      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3981                               getF32Constant(DAG, 0x3e75fe14));
3982      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3983      SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3984                                getF32Constant(DAG, 0x3f317234));
3985      SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3986      TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3987                                     getF32Constant(DAG, 0x3f800000));
3988    }
3989
3990    // Add the exponent into the result in integer domain.
3991    SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3992    return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3993                       DAG.getNode(ISD::ADD, dl, MVT::i32,
3994                                   t13, IntegerPartOfX));
3995  }
3996
3997  // No special expansion.
3998  return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3999}
4000
4001/// expandLog - Lower a log intrinsic. Handles the special sequences for
4002/// limited-precision mode.
4003static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4004                         const TargetLowering &TLI) {
4005  if (Op.getValueType() == MVT::f32 &&
4006      LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4007    SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4008
4009    // Scale the exponent by log(2) [0.69314718f].
4010    SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4011    SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4012                                        getF32Constant(DAG, 0x3f317218));
4013
4014    // Get the significand and build it into a floating-point number with
4015    // exponent of 1.
4016    SDValue X = GetSignificand(DAG, Op1, dl);
4017
4018    SDValue LogOfMantissa;
4019    if (LimitFloatPrecision <= 6) {
4020      // For floating-point precision of 6:
4021      //
4022      //   LogofMantissa =
4023      //     -1.1609546f +
4024      //       (1.4034025f - 0.23903021f * x) * x;
4025      //
4026      // error 0.0034276066, which is better than 8 bits
4027      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4028                               getF32Constant(DAG, 0xbe74c456));
4029      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4030                               getF32Constant(DAG, 0x3fb3a2b1));
4031      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4032      LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4033                                  getF32Constant(DAG, 0x3f949a29));
4034    } else if (LimitFloatPrecision <= 12) {
4035      // For floating-point precision of 12:
4036      //
4037      //   LogOfMantissa =
4038      //     -1.7417939f +
4039      //       (2.8212026f +
4040      //         (-1.4699568f +
4041      //           (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4042      //
4043      // error 0.000061011436, which is 14 bits
4044      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4045                               getF32Constant(DAG, 0xbd67b6d6));
4046      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4047                               getF32Constant(DAG, 0x3ee4f4b8));
4048      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4049      SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4050                               getF32Constant(DAG, 0x3fbc278b));
4051      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4052      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4053                               getF32Constant(DAG, 0x40348e95));
4054      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4055      LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4056                                  getF32Constant(DAG, 0x3fdef31a));
4057    } else { // LimitFloatPrecision <= 18
4058      // For floating-point precision of 18:
4059      //
4060      //   LogOfMantissa =
4061      //     -2.1072184f +
4062      //       (4.2372794f +
4063      //         (-3.7029485f +
4064      //           (2.2781945f +
4065      //             (-0.87823314f +
4066      //               (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4067      //
4068      // error 0.0000023660568, which is better than 18 bits
4069      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4070                               getF32Constant(DAG, 0xbc91e5ac));
4071      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4072                               getF32Constant(DAG, 0x3e4350aa));
4073      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4074      SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4075                               getF32Constant(DAG, 0x3f60d3e3));
4076      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4077      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4078                               getF32Constant(DAG, 0x4011cdf0));
4079      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4080      SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4081                               getF32Constant(DAG, 0x406cfd1c));
4082      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4083      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4084                               getF32Constant(DAG, 0x408797cb));
4085      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4086      LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4087                                  getF32Constant(DAG, 0x4006dcab));
4088    }
4089
4090    return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4091  }
4092
4093  // No special expansion.
4094  return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4095}
4096
4097/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4098/// limited-precision mode.
4099static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4100                          const TargetLowering &TLI) {
4101  if (Op.getValueType() == MVT::f32 &&
4102      LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4103    SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4104
4105    // Get the exponent.
4106    SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4107
4108    // Get the significand and build it into a floating-point number with
4109    // exponent of 1.
4110    SDValue X = GetSignificand(DAG, Op1, dl);
4111
4112    // Different possible minimax approximations of significand in
4113    // floating-point for various degrees of accuracy over [1,2].
4114    SDValue Log2ofMantissa;
4115    if (LimitFloatPrecision <= 6) {
4116      // For floating-point precision of 6:
4117      //
4118      //   Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4119      //
4120      // error 0.0049451742, which is more than 7 bits
4121      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4122                               getF32Constant(DAG, 0xbeb08fe0));
4123      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4124                               getF32Constant(DAG, 0x40019463));
4125      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4126      Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4127                                   getF32Constant(DAG, 0x3fd6633d));
4128    } else if (LimitFloatPrecision <= 12) {
4129      // For floating-point precision of 12:
4130      //
4131      //   Log2ofMantissa =
4132      //     -2.51285454f +
4133      //       (4.07009056f +
4134      //         (-2.12067489f +
4135      //           (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4136      //
4137      // error 0.0000876136000, which is better than 13 bits
4138      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4139                               getF32Constant(DAG, 0xbda7262e));
4140      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4141                               getF32Constant(DAG, 0x3f25280b));
4142      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4143      SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4144                               getF32Constant(DAG, 0x4007b923));
4145      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4146      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4147                               getF32Constant(DAG, 0x40823e2f));
4148      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4149      Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4150                                   getF32Constant(DAG, 0x4020d29c));
4151    } else { // LimitFloatPrecision <= 18
4152      // For floating-point precision of 18:
4153      //
4154      //   Log2ofMantissa =
4155      //     -3.0400495f +
4156      //       (6.1129976f +
4157      //         (-5.3420409f +
4158      //           (3.2865683f +
4159      //             (-1.2669343f +
4160      //               (0.27515199f -
4161      //                 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4162      //
4163      // error 0.0000018516, which is better than 18 bits
4164      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4165                               getF32Constant(DAG, 0xbcd2769e));
4166      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4167                               getF32Constant(DAG, 0x3e8ce0b9));
4168      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4169      SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4170                               getF32Constant(DAG, 0x3fa22ae7));
4171      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4172      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4173                               getF32Constant(DAG, 0x40525723));
4174      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4175      SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4176                               getF32Constant(DAG, 0x40aaf200));
4177      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4178      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4179                               getF32Constant(DAG, 0x40c39dad));
4180      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4181      Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4182                                   getF32Constant(DAG, 0x4042902c));
4183    }
4184
4185    return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4186  }
4187
4188  // No special expansion.
4189  return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4190}
4191
4192/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4193/// limited-precision mode.
4194static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4195                           const TargetLowering &TLI) {
4196  if (Op.getValueType() == MVT::f32 &&
4197      LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4198    SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4199
4200    // Scale the exponent by log10(2) [0.30102999f].
4201    SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4202    SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4203                                        getF32Constant(DAG, 0x3e9a209a));
4204
4205    // Get the significand and build it into a floating-point number with
4206    // exponent of 1.
4207    SDValue X = GetSignificand(DAG, Op1, dl);
4208
4209    SDValue Log10ofMantissa;
4210    if (LimitFloatPrecision <= 6) {
4211      // For floating-point precision of 6:
4212      //
4213      //   Log10ofMantissa =
4214      //     -0.50419619f +
4215      //       (0.60948995f - 0.10380950f * x) * x;
4216      //
4217      // error 0.0014886165, which is 6 bits
4218      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4219                               getF32Constant(DAG, 0xbdd49a13));
4220      SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4221                               getF32Constant(DAG, 0x3f1c0789));
4222      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4223      Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4224                                    getF32Constant(DAG, 0x3f011300));
4225    } else if (LimitFloatPrecision <= 12) {
4226      // For floating-point precision of 12:
4227      //
4228      //   Log10ofMantissa =
4229      //     -0.64831180f +
4230      //       (0.91751397f +
4231      //         (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4232      //
4233      // error 0.00019228036, which is better than 12 bits
4234      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4235                               getF32Constant(DAG, 0x3d431f31));
4236      SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4237                               getF32Constant(DAG, 0x3ea21fb2));
4238      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4239      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4240                               getF32Constant(DAG, 0x3f6ae232));
4241      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4242      Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4243                                    getF32Constant(DAG, 0x3f25f7c3));
4244    } else { // LimitFloatPrecision <= 18
4245      // For floating-point precision of 18:
4246      //
4247      //   Log10ofMantissa =
4248      //     -0.84299375f +
4249      //       (1.5327582f +
4250      //         (-1.0688956f +
4251      //           (0.49102474f +
4252      //             (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4253      //
4254      // error 0.0000037995730, which is better than 18 bits
4255      SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4256                               getF32Constant(DAG, 0x3c5d51ce));
4257      SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4258                               getF32Constant(DAG, 0x3e00685a));
4259      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4260      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4261                               getF32Constant(DAG, 0x3efb6798));
4262      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4263      SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4264                               getF32Constant(DAG, 0x3f88d192));
4265      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4266      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4267                               getF32Constant(DAG, 0x3fc4316c));
4268      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4269      Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4270                                    getF32Constant(DAG, 0x3f57ce70));
4271    }
4272
4273    return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4274  }
4275
4276  // No special expansion.
4277  return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4278}
4279
4280/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4281/// limited-precision mode.
4282static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4283                          const TargetLowering &TLI) {
4284  if (Op.getValueType() == MVT::f32 &&
4285      LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4286    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4287
4288    //   FractionalPartOfX = x - (float)IntegerPartOfX;
4289    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4290    SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4291
4292    //   IntegerPartOfX <<= 23;
4293    IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4294                                 DAG.getConstant(23, TLI.getPointerTy()));
4295
4296    SDValue TwoToFractionalPartOfX;
4297    if (LimitFloatPrecision <= 6) {
4298      // For floating-point precision of 6:
4299      //
4300      //   TwoToFractionalPartOfX =
4301      //     0.997535578f +
4302      //       (0.735607626f + 0.252464424f * x) * x;
4303      //
4304      // error 0.0144103317, which is 6 bits
4305      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4306                               getF32Constant(DAG, 0x3e814304));
4307      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4308                               getF32Constant(DAG, 0x3f3c50c8));
4309      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4310      TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4311                                           getF32Constant(DAG, 0x3f7f5e7e));
4312    } else if (LimitFloatPrecision <= 12) {
4313      // For floating-point precision of 12:
4314      //
4315      //   TwoToFractionalPartOfX =
4316      //     0.999892986f +
4317      //       (0.696457318f +
4318      //         (0.224338339f + 0.792043434e-1f * x) * x) * x;
4319      //
4320      // error 0.000107046256, which is 13 to 14 bits
4321      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4322                               getF32Constant(DAG, 0x3da235e3));
4323      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4324                               getF32Constant(DAG, 0x3e65b8f3));
4325      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4326      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4327                               getF32Constant(DAG, 0x3f324b07));
4328      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4329      TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4330                                           getF32Constant(DAG, 0x3f7ff8fd));
4331    } else { // LimitFloatPrecision <= 18
4332      // For floating-point precision of 18:
4333      //
4334      //   TwoToFractionalPartOfX =
4335      //     0.999999982f +
4336      //       (0.693148872f +
4337      //         (0.240227044f +
4338      //           (0.554906021e-1f +
4339      //             (0.961591928e-2f +
4340      //               (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4341      // error 2.47208000*10^(-7), which is better than 18 bits
4342      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4343                               getF32Constant(DAG, 0x3924b03e));
4344      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4345                               getF32Constant(DAG, 0x3ab24b87));
4346      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4347      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4348                               getF32Constant(DAG, 0x3c1d8c17));
4349      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4350      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4351                               getF32Constant(DAG, 0x3d634a1d));
4352      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4353      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4354                               getF32Constant(DAG, 0x3e75fe14));
4355      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4356      SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4357                                getF32Constant(DAG, 0x3f317234));
4358      SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4359      TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4360                                           getF32Constant(DAG, 0x3f800000));
4361    }
4362
4363    // Add the exponent into the result in integer domain.
4364    SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4365                              TwoToFractionalPartOfX);
4366    return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4367                       DAG.getNode(ISD::ADD, dl, MVT::i32,
4368                                   t13, IntegerPartOfX));
4369  }
4370
4371  // No special expansion.
4372  return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4373}
4374
4375/// visitPow - Lower a pow intrinsic. Handles the special sequences for
4376/// limited-precision mode with x == 10.0f.
4377static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4378                         SelectionDAG &DAG, const TargetLowering &TLI) {
4379  bool IsExp10 = false;
4380  if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4381      LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4382    if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4383      APFloat Ten(10.0f);
4384      IsExp10 = LHSC->isExactlyValue(Ten);
4385    }
4386  }
4387
4388  if (IsExp10) {
4389    // Put the exponent in the right bit position for later addition to the
4390    // final result:
4391    //
4392    //   #define LOG2OF10 3.3219281f
4393    //   IntegerPartOfX = (int32_t)(x * LOG2OF10);
4394    SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4395                             getF32Constant(DAG, 0x40549a78));
4396    SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4397
4398    //   FractionalPartOfX = x - (float)IntegerPartOfX;
4399    SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4400    SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4401
4402    //   IntegerPartOfX <<= 23;
4403    IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4404                                 DAG.getConstant(23, TLI.getPointerTy()));
4405
4406    SDValue TwoToFractionalPartOfX;
4407    if (LimitFloatPrecision <= 6) {
4408      // For floating-point precision of 6:
4409      //
4410      //   twoToFractionalPartOfX =
4411      //     0.997535578f +
4412      //       (0.735607626f + 0.252464424f * x) * x;
4413      //
4414      // error 0.0144103317, which is 6 bits
4415      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4416                               getF32Constant(DAG, 0x3e814304));
4417      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4418                               getF32Constant(DAG, 0x3f3c50c8));
4419      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4420      TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4421                                           getF32Constant(DAG, 0x3f7f5e7e));
4422    } else if (LimitFloatPrecision <= 12) {
4423      // For floating-point precision of 12:
4424      //
4425      //   TwoToFractionalPartOfX =
4426      //     0.999892986f +
4427      //       (0.696457318f +
4428      //         (0.224338339f + 0.792043434e-1f * x) * x) * x;
4429      //
4430      // error 0.000107046256, which is 13 to 14 bits
4431      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4432                               getF32Constant(DAG, 0x3da235e3));
4433      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4434                               getF32Constant(DAG, 0x3e65b8f3));
4435      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4436      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4437                               getF32Constant(DAG, 0x3f324b07));
4438      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4439      TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4440                                           getF32Constant(DAG, 0x3f7ff8fd));
4441    } else { // LimitFloatPrecision <= 18
4442      // For floating-point precision of 18:
4443      //
4444      //   TwoToFractionalPartOfX =
4445      //     0.999999982f +
4446      //       (0.693148872f +
4447      //         (0.240227044f +
4448      //           (0.554906021e-1f +
4449      //             (0.961591928e-2f +
4450      //               (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4451      // error 2.47208000*10^(-7), which is better than 18 bits
4452      SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4453                               getF32Constant(DAG, 0x3924b03e));
4454      SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4455                               getF32Constant(DAG, 0x3ab24b87));
4456      SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4457      SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4458                               getF32Constant(DAG, 0x3c1d8c17));
4459      SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4460      SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4461                               getF32Constant(DAG, 0x3d634a1d));
4462      SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4463      SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4464                               getF32Constant(DAG, 0x3e75fe14));
4465      SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4466      SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4467                                getF32Constant(DAG, 0x3f317234));
4468      SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4469      TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4470                                           getF32Constant(DAG, 0x3f800000));
4471    }
4472
4473    SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4474    return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4475                       DAG.getNode(ISD::ADD, dl, MVT::i32,
4476                                   t13,