SelectionDAGBuilder.cpp revision 4fe5b640ee935f983db9445dc9fdb4009d4fa639
1//===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements routines for translating from LLVM IR into SelectionDAG IR. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "isel" 15#include "SelectionDAGBuilder.h" 16#include "SDNodeDbgValue.h" 17#include "llvm/ADT/BitVector.h" 18#include "llvm/ADT/Optional.h" 19#include "llvm/ADT/SmallSet.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/Analysis/BranchProbabilityInfo.h" 22#include "llvm/Analysis/ConstantFolding.h" 23#include "llvm/Analysis/ValueTracking.h" 24#include "llvm/CodeGen/Analysis.h" 25#include "llvm/CodeGen/FastISel.h" 26#include "llvm/CodeGen/FunctionLoweringInfo.h" 27#include "llvm/CodeGen/GCMetadata.h" 28#include "llvm/CodeGen/GCStrategy.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineJumpTableInfo.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/SelectionDAG.h" 36#include "llvm/CodeGen/StackMaps.h" 37#include "llvm/DebugInfo.h" 38#include "llvm/IR/CallingConv.h" 39#include "llvm/IR/Constants.h" 40#include "llvm/IR/DataLayout.h" 41#include "llvm/IR/DerivedTypes.h" 42#include "llvm/IR/Function.h" 43#include "llvm/IR/GlobalVariable.h" 44#include "llvm/IR/InlineAsm.h" 45#include "llvm/IR/Instructions.h" 46#include "llvm/IR/IntrinsicInst.h" 47#include "llvm/IR/Intrinsics.h" 48#include "llvm/IR/LLVMContext.h" 49#include "llvm/IR/Module.h" 50#include "llvm/Support/CommandLine.h" 51#include "llvm/Support/Debug.h" 52#include "llvm/Support/ErrorHandling.h" 53#include "llvm/Support/MathExtras.h" 54#include "llvm/Support/raw_ostream.h" 55#include "llvm/Target/TargetFrameLowering.h" 56#include "llvm/Target/TargetInstrInfo.h" 57#include "llvm/Target/TargetIntrinsicInfo.h" 58#include "llvm/Target/TargetLibraryInfo.h" 59#include "llvm/Target/TargetLowering.h" 60#include "llvm/Target/TargetOptions.h" 61#include "llvm/Target/TargetSelectionDAGInfo.h" 62#include <algorithm> 63using namespace llvm; 64 65/// LimitFloatPrecision - Generate low-precision inline sequences for 66/// some float libcalls (6, 8 or 12 bits). 67static unsigned LimitFloatPrecision; 68 69static cl::opt<unsigned, true> 70LimitFPPrecision("limit-float-precision", 71 cl::desc("Generate low-precision inline sequences " 72 "for some float libcalls"), 73 cl::location(LimitFloatPrecision), 74 cl::init(0)); 75 76// Limit the width of DAG chains. This is important in general to prevent 77// prevent DAG-based analysis from blowing up. For example, alias analysis and 78// load clustering may not complete in reasonable time. It is difficult to 79// recognize and avoid this situation within each individual analysis, and 80// future analyses are likely to have the same behavior. Limiting DAG width is 81// the safe approach, and will be especially important with global DAGs. 82// 83// MaxParallelChains default is arbitrarily high to avoid affecting 84// optimization, but could be lowered to improve compile time. Any ld-ld-st-st 85// sequence over this should have been converted to llvm.memcpy by the 86// frontend. It easy to induce this behavior with .ll code such as: 87// %buffer = alloca [4096 x i8] 88// %data = load [4096 x i8]* %argPtr 89// store [4096 x i8] %data, [4096 x i8]* %buffer 90static const unsigned MaxParallelChains = 64; 91 92static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL, 93 const SDValue *Parts, unsigned NumParts, 94 MVT PartVT, EVT ValueVT, const Value *V); 95 96/// getCopyFromParts - Create a value that contains the specified legal parts 97/// combined into the value they represent. If the parts combine to a type 98/// larger then ValueVT then AssertOp can be used to specify whether the extra 99/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 100/// (ISD::AssertSext). 101static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL, 102 const SDValue *Parts, 103 unsigned NumParts, MVT PartVT, EVT ValueVT, 104 const Value *V, 105 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 106 if (ValueVT.isVector()) 107 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, 108 PartVT, ValueVT, V); 109 110 assert(NumParts > 0 && "No parts to assemble!"); 111 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 112 SDValue Val = Parts[0]; 113 114 if (NumParts > 1) { 115 // Assemble the value from multiple parts. 116 if (ValueVT.isInteger()) { 117 unsigned PartBits = PartVT.getSizeInBits(); 118 unsigned ValueBits = ValueVT.getSizeInBits(); 119 120 // Assemble the power of 2 part. 121 unsigned RoundParts = NumParts & (NumParts - 1) ? 122 1 << Log2_32(NumParts) : NumParts; 123 unsigned RoundBits = PartBits * RoundParts; 124 EVT RoundVT = RoundBits == ValueBits ? 125 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 126 SDValue Lo, Hi; 127 128 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 129 130 if (RoundParts > 2) { 131 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 132 PartVT, HalfVT, V); 133 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 134 RoundParts / 2, PartVT, HalfVT, V); 135 } else { 136 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 137 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 138 } 139 140 if (TLI.isBigEndian()) 141 std::swap(Lo, Hi); 142 143 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 144 145 if (RoundParts < NumParts) { 146 // Assemble the trailing non-power-of-2 part. 147 unsigned OddParts = NumParts - RoundParts; 148 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 149 Hi = getCopyFromParts(DAG, DL, 150 Parts + RoundParts, OddParts, PartVT, OddVT, V); 151 152 // Combine the round and odd parts. 153 Lo = Val; 154 if (TLI.isBigEndian()) 155 std::swap(Lo, Hi); 156 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 157 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 158 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 159 DAG.getConstant(Lo.getValueType().getSizeInBits(), 160 TLI.getPointerTy())); 161 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 162 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 163 } 164 } else if (PartVT.isFloatingPoint()) { 165 // FP split into multiple FP parts (for ppcf128) 166 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 && 167 "Unexpected split"); 168 SDValue Lo, Hi; 169 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 170 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 171 if (TLI.isBigEndian()) 172 std::swap(Lo, Hi); 173 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 174 } else { 175 // FP split into integer parts (soft fp) 176 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 177 !PartVT.isVector() && "Unexpected split"); 178 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 179 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V); 180 } 181 } 182 183 // There is now one part, held in Val. Correct it to match ValueVT. 184 EVT PartEVT = Val.getValueType(); 185 186 if (PartEVT == ValueVT) 187 return Val; 188 189 if (PartEVT.isInteger() && ValueVT.isInteger()) { 190 if (ValueVT.bitsLT(PartEVT)) { 191 // For a truncate, see if we have any information to 192 // indicate whether the truncated bits will always be 193 // zero or sign-extension. 194 if (AssertOp != ISD::DELETED_NODE) 195 Val = DAG.getNode(AssertOp, DL, PartEVT, Val, 196 DAG.getValueType(ValueVT)); 197 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 198 } 199 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 200 } 201 202 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 203 // FP_ROUND's are always exact here. 204 if (ValueVT.bitsLT(Val.getValueType())) 205 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 206 DAG.getTargetConstant(1, TLI.getPointerTy())); 207 208 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 209 } 210 211 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits()) 212 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 213 214 llvm_unreachable("Unknown mismatch!"); 215} 216 217/// getCopyFromPartsVector - Create a value that contains the specified legal 218/// parts combined into the value they represent. If the parts combine to a 219/// type larger then ValueVT then AssertOp can be used to specify whether the 220/// extra bits are known to be zero (ISD::AssertZext) or sign extended from 221/// ValueVT (ISD::AssertSext). 222static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL, 223 const SDValue *Parts, unsigned NumParts, 224 MVT PartVT, EVT ValueVT, const Value *V) { 225 assert(ValueVT.isVector() && "Not a vector value"); 226 assert(NumParts > 0 && "No parts to assemble!"); 227 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 228 SDValue Val = Parts[0]; 229 230 // Handle a multi-element vector. 231 if (NumParts > 1) { 232 EVT IntermediateVT; 233 MVT RegisterVT; 234 unsigned NumIntermediates; 235 unsigned NumRegs = 236 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 237 NumIntermediates, RegisterVT); 238 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 239 NumParts = NumRegs; // Silence a compiler warning. 240 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 241 assert(RegisterVT == Parts[0].getSimpleValueType() && 242 "Part type doesn't match part!"); 243 244 // Assemble the parts into intermediate operands. 245 SmallVector<SDValue, 8> Ops(NumIntermediates); 246 if (NumIntermediates == NumParts) { 247 // If the register was not expanded, truncate or copy the value, 248 // as appropriate. 249 for (unsigned i = 0; i != NumParts; ++i) 250 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 251 PartVT, IntermediateVT, V); 252 } else if (NumParts > 0) { 253 // If the intermediate type was expanded, build the intermediate 254 // operands from the parts. 255 assert(NumParts % NumIntermediates == 0 && 256 "Must expand into a divisible number of parts!"); 257 unsigned Factor = NumParts / NumIntermediates; 258 for (unsigned i = 0; i != NumIntermediates; ++i) 259 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 260 PartVT, IntermediateVT, V); 261 } 262 263 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 264 // intermediate operands. 265 Val = DAG.getNode(IntermediateVT.isVector() ? 266 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 267 ValueVT, &Ops[0], NumIntermediates); 268 } 269 270 // There is now one part, held in Val. Correct it to match ValueVT. 271 EVT PartEVT = Val.getValueType(); 272 273 if (PartEVT == ValueVT) 274 return Val; 275 276 if (PartEVT.isVector()) { 277 // If the element type of the source/dest vectors are the same, but the 278 // parts vector has more elements than the value vector, then we have a 279 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 280 // elements we want. 281 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) { 282 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 283 "Cannot narrow, it would be a lossy transformation"); 284 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 285 DAG.getConstant(0, TLI.getVectorIdxTy())); 286 } 287 288 // Vector/Vector bitcast. 289 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) 290 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 291 292 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 293 "Cannot handle this kind of promotion"); 294 // Promoted vector extract 295 bool Smaller = ValueVT.bitsLE(PartEVT); 296 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 297 DL, ValueVT, Val); 298 299 } 300 301 // Trivial bitcast if the types are the same size and the destination 302 // vector type is legal. 303 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() && 304 TLI.isTypeLegal(ValueVT)) 305 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 306 307 // Handle cases such as i8 -> <1 x i1> 308 if (ValueVT.getVectorNumElements() != 1) { 309 LLVMContext &Ctx = *DAG.getContext(); 310 Twine ErrMsg("non-trivial scalar-to-vector conversion"); 311 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) { 312 if (const CallInst *CI = dyn_cast<CallInst>(I)) 313 if (isa<InlineAsm>(CI->getCalledValue())) 314 ErrMsg = ErrMsg + ", possible invalid constraint for vector type"; 315 Ctx.emitError(I, ErrMsg); 316 } else { 317 Ctx.emitError(ErrMsg); 318 } 319 return DAG.getUNDEF(ValueVT); 320 } 321 322 if (ValueVT.getVectorNumElements() == 1 && 323 ValueVT.getVectorElementType() != PartEVT) { 324 bool Smaller = ValueVT.bitsLE(PartEVT); 325 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 326 DL, ValueVT.getScalarType(), Val); 327 } 328 329 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 330} 331 332static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl, 333 SDValue Val, SDValue *Parts, unsigned NumParts, 334 MVT PartVT, const Value *V); 335 336/// getCopyToParts - Create a series of nodes that contain the specified value 337/// split into legal parts. If the parts contain more bits than Val, then, for 338/// integers, ExtendKind can be used to specify how to generate the extra bits. 339static void getCopyToParts(SelectionDAG &DAG, SDLoc DL, 340 SDValue Val, SDValue *Parts, unsigned NumParts, 341 MVT PartVT, const Value *V, 342 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 343 EVT ValueVT = Val.getValueType(); 344 345 // Handle the vector case separately. 346 if (ValueVT.isVector()) 347 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V); 348 349 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 350 unsigned PartBits = PartVT.getSizeInBits(); 351 unsigned OrigNumParts = NumParts; 352 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 353 354 if (NumParts == 0) 355 return; 356 357 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 358 EVT PartEVT = PartVT; 359 if (PartEVT == ValueVT) { 360 assert(NumParts == 1 && "No-op copy with multiple parts!"); 361 Parts[0] = Val; 362 return; 363 } 364 365 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 366 // If the parts cover more bits than the value has, promote the value. 367 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 368 assert(NumParts == 1 && "Do not know what to promote to!"); 369 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 370 } else { 371 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 372 ValueVT.isInteger() && 373 "Unknown mismatch!"); 374 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 375 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 376 if (PartVT == MVT::x86mmx) 377 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 378 } 379 } else if (PartBits == ValueVT.getSizeInBits()) { 380 // Different types of the same size. 381 assert(NumParts == 1 && PartEVT != ValueVT); 382 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 383 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 384 // If the parts cover less bits than value has, truncate the value. 385 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && 386 ValueVT.isInteger() && 387 "Unknown mismatch!"); 388 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 389 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 390 if (PartVT == MVT::x86mmx) 391 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 392 } 393 394 // The value may have changed - recompute ValueVT. 395 ValueVT = Val.getValueType(); 396 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 397 "Failed to tile the value with PartVT!"); 398 399 if (NumParts == 1) { 400 if (PartEVT != ValueVT) { 401 LLVMContext &Ctx = *DAG.getContext(); 402 Twine ErrMsg("scalar-to-vector conversion failed"); 403 if (const Instruction *I = dyn_cast_or_null<Instruction>(V)) { 404 if (const CallInst *CI = dyn_cast<CallInst>(I)) 405 if (isa<InlineAsm>(CI->getCalledValue())) 406 ErrMsg = ErrMsg + ", possible invalid constraint for vector type"; 407 Ctx.emitError(I, ErrMsg); 408 } else { 409 Ctx.emitError(ErrMsg); 410 } 411 } 412 413 Parts[0] = Val; 414 return; 415 } 416 417 // Expand the value into multiple parts. 418 if (NumParts & (NumParts - 1)) { 419 // The number of parts is not a power of 2. Split off and copy the tail. 420 assert(PartVT.isInteger() && ValueVT.isInteger() && 421 "Do not know what to expand to!"); 422 unsigned RoundParts = 1 << Log2_32(NumParts); 423 unsigned RoundBits = RoundParts * PartBits; 424 unsigned OddParts = NumParts - RoundParts; 425 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 426 DAG.getIntPtrConstant(RoundBits)); 427 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V); 428 429 if (TLI.isBigEndian()) 430 // The odd parts were reversed by getCopyToParts - unreverse them. 431 std::reverse(Parts + RoundParts, Parts + NumParts); 432 433 NumParts = RoundParts; 434 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 435 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 436 } 437 438 // The number of parts is a power of 2. Repeatedly bisect the value using 439 // EXTRACT_ELEMENT. 440 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 441 EVT::getIntegerVT(*DAG.getContext(), 442 ValueVT.getSizeInBits()), 443 Val); 444 445 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 446 for (unsigned i = 0; i < NumParts; i += StepSize) { 447 unsigned ThisBits = StepSize * PartBits / 2; 448 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 449 SDValue &Part0 = Parts[i]; 450 SDValue &Part1 = Parts[i+StepSize/2]; 451 452 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 453 ThisVT, Part0, DAG.getIntPtrConstant(1)); 454 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 455 ThisVT, Part0, DAG.getIntPtrConstant(0)); 456 457 if (ThisBits == PartBits && ThisVT != PartVT) { 458 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 459 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 460 } 461 } 462 } 463 464 if (TLI.isBigEndian()) 465 std::reverse(Parts, Parts + OrigNumParts); 466} 467 468 469/// getCopyToPartsVector - Create a series of nodes that contain the specified 470/// value split into legal parts. 471static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL, 472 SDValue Val, SDValue *Parts, unsigned NumParts, 473 MVT PartVT, const Value *V) { 474 EVT ValueVT = Val.getValueType(); 475 assert(ValueVT.isVector() && "Not a vector"); 476 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 477 478 if (NumParts == 1) { 479 EVT PartEVT = PartVT; 480 if (PartEVT == ValueVT) { 481 // Nothing to do. 482 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 483 // Bitconvert vector->vector case. 484 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 485 } else if (PartVT.isVector() && 486 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() && 487 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 488 EVT ElementVT = PartVT.getVectorElementType(); 489 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 490 // undef elements. 491 SmallVector<SDValue, 16> Ops; 492 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 493 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 494 ElementVT, Val, DAG.getConstant(i, 495 TLI.getVectorIdxTy()))); 496 497 for (unsigned i = ValueVT.getVectorNumElements(), 498 e = PartVT.getVectorNumElements(); i != e; ++i) 499 Ops.push_back(DAG.getUNDEF(ElementVT)); 500 501 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 502 503 // FIXME: Use CONCAT for 2x -> 4x. 504 505 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 506 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 507 } else if (PartVT.isVector() && 508 PartEVT.getVectorElementType().bitsGE( 509 ValueVT.getVectorElementType()) && 510 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 511 512 // Promoted vector extract 513 bool Smaller = PartEVT.bitsLE(ValueVT); 514 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 515 DL, PartVT, Val); 516 } else{ 517 // Vector -> scalar conversion. 518 assert(ValueVT.getVectorNumElements() == 1 && 519 "Only trivial vector-to-scalar conversions should get here!"); 520 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 521 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy())); 522 523 bool Smaller = ValueVT.bitsLE(PartVT); 524 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 525 DL, PartVT, Val); 526 } 527 528 Parts[0] = Val; 529 return; 530 } 531 532 // Handle a multi-element vector. 533 EVT IntermediateVT; 534 MVT RegisterVT; 535 unsigned NumIntermediates; 536 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 537 IntermediateVT, 538 NumIntermediates, RegisterVT); 539 unsigned NumElements = ValueVT.getVectorNumElements(); 540 541 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 542 NumParts = NumRegs; // Silence a compiler warning. 543 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 544 545 // Split the vector into intermediate operands. 546 SmallVector<SDValue, 8> Ops(NumIntermediates); 547 for (unsigned i = 0; i != NumIntermediates; ++i) { 548 if (IntermediateVT.isVector()) 549 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 550 IntermediateVT, Val, 551 DAG.getConstant(i * (NumElements / NumIntermediates), 552 TLI.getVectorIdxTy())); 553 else 554 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 555 IntermediateVT, Val, 556 DAG.getConstant(i, TLI.getVectorIdxTy())); 557 } 558 559 // Split the intermediate operands into legal parts. 560 if (NumParts == NumIntermediates) { 561 // If the register was not expanded, promote or copy the value, 562 // as appropriate. 563 for (unsigned i = 0; i != NumParts; ++i) 564 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V); 565 } else if (NumParts > 0) { 566 // If the intermediate type was expanded, split each the value into 567 // legal parts. 568 assert(NumParts % NumIntermediates == 0 && 569 "Must expand into a divisible number of parts!"); 570 unsigned Factor = NumParts / NumIntermediates; 571 for (unsigned i = 0; i != NumIntermediates; ++i) 572 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V); 573 } 574} 575 576namespace { 577 /// RegsForValue - This struct represents the registers (physical or virtual) 578 /// that a particular set of values is assigned, and the type information 579 /// about the value. The most common situation is to represent one value at a 580 /// time, but struct or array values are handled element-wise as multiple 581 /// values. The splitting of aggregates is performed recursively, so that we 582 /// never have aggregate-typed registers. The values at this point do not 583 /// necessarily have legal types, so each value may require one or more 584 /// registers of some legal type. 585 /// 586 struct RegsForValue { 587 /// ValueVTs - The value types of the values, which may not be legal, and 588 /// may need be promoted or synthesized from one or more registers. 589 /// 590 SmallVector<EVT, 4> ValueVTs; 591 592 /// RegVTs - The value types of the registers. This is the same size as 593 /// ValueVTs and it records, for each value, what the type of the assigned 594 /// register or registers are. (Individual values are never synthesized 595 /// from more than one type of register.) 596 /// 597 /// With virtual registers, the contents of RegVTs is redundant with TLI's 598 /// getRegisterType member function, however when with physical registers 599 /// it is necessary to have a separate record of the types. 600 /// 601 SmallVector<MVT, 4> RegVTs; 602 603 /// Regs - This list holds the registers assigned to the values. 604 /// Each legal or promoted value requires one register, and each 605 /// expanded value requires multiple registers. 606 /// 607 SmallVector<unsigned, 4> Regs; 608 609 RegsForValue() {} 610 611 RegsForValue(const SmallVector<unsigned, 4> ®s, 612 MVT regvt, EVT valuevt) 613 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 614 615 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 616 unsigned Reg, Type *Ty) { 617 ComputeValueVTs(tli, Ty, ValueVTs); 618 619 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 620 EVT ValueVT = ValueVTs[Value]; 621 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 622 MVT RegisterVT = tli.getRegisterType(Context, ValueVT); 623 for (unsigned i = 0; i != NumRegs; ++i) 624 Regs.push_back(Reg + i); 625 RegVTs.push_back(RegisterVT); 626 Reg += NumRegs; 627 } 628 } 629 630 /// areValueTypesLegal - Return true if types of all the values are legal. 631 bool areValueTypesLegal(const TargetLowering &TLI) { 632 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 633 MVT RegisterVT = RegVTs[Value]; 634 if (!TLI.isTypeLegal(RegisterVT)) 635 return false; 636 } 637 return true; 638 } 639 640 /// append - Add the specified values to this one. 641 void append(const RegsForValue &RHS) { 642 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 643 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 644 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 645 } 646 647 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 648 /// this value and returns the result as a ValueVTs value. This uses 649 /// Chain/Flag as the input and updates them for the output Chain/Flag. 650 /// If the Flag pointer is NULL, no flag is used. 651 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 652 SDLoc dl, 653 SDValue &Chain, SDValue *Flag, 654 const Value *V = 0) const; 655 656 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 657 /// specified value into the registers specified by this object. This uses 658 /// Chain/Flag as the input and updates them for the output Chain/Flag. 659 /// If the Flag pointer is NULL, no flag is used. 660 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, 661 SDValue &Chain, SDValue *Flag, const Value *V) const; 662 663 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 664 /// operand list. This adds the code marker, matching input operand index 665 /// (if applicable), and includes the number of values added into it. 666 void AddInlineAsmOperands(unsigned Kind, 667 bool HasMatching, unsigned MatchingIdx, 668 SelectionDAG &DAG, 669 std::vector<SDValue> &Ops) const; 670 }; 671} 672 673/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 674/// this value and returns the result as a ValueVT value. This uses 675/// Chain/Flag as the input and updates them for the output Chain/Flag. 676/// If the Flag pointer is NULL, no flag is used. 677SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 678 FunctionLoweringInfo &FuncInfo, 679 SDLoc dl, 680 SDValue &Chain, SDValue *Flag, 681 const Value *V) const { 682 // A Value with type {} or [0 x %t] needs no registers. 683 if (ValueVTs.empty()) 684 return SDValue(); 685 686 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 687 688 // Assemble the legal parts into the final values. 689 SmallVector<SDValue, 4> Values(ValueVTs.size()); 690 SmallVector<SDValue, 8> Parts; 691 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 692 // Copy the legal parts from the registers. 693 EVT ValueVT = ValueVTs[Value]; 694 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 695 MVT RegisterVT = RegVTs[Value]; 696 697 Parts.resize(NumRegs); 698 for (unsigned i = 0; i != NumRegs; ++i) { 699 SDValue P; 700 if (Flag == 0) { 701 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 702 } else { 703 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 704 *Flag = P.getValue(2); 705 } 706 707 Chain = P.getValue(1); 708 Parts[i] = P; 709 710 // If the source register was virtual and if we know something about it, 711 // add an assert node. 712 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 713 !RegisterVT.isInteger() || RegisterVT.isVector()) 714 continue; 715 716 const FunctionLoweringInfo::LiveOutInfo *LOI = 717 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 718 if (!LOI) 719 continue; 720 721 unsigned RegSize = RegisterVT.getSizeInBits(); 722 unsigned NumSignBits = LOI->NumSignBits; 723 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 724 725 if (NumZeroBits == RegSize) { 726 // The current value is a zero. 727 // Explicitly express that as it would be easier for 728 // optimizations to kick in. 729 Parts[i] = DAG.getConstant(0, RegisterVT); 730 continue; 731 } 732 733 // FIXME: We capture more information than the dag can represent. For 734 // now, just use the tightest assertzext/assertsext possible. 735 bool isSExt = true; 736 EVT FromVT(MVT::Other); 737 if (NumSignBits == RegSize) 738 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 739 else if (NumZeroBits >= RegSize-1) 740 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 741 else if (NumSignBits > RegSize-8) 742 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 743 else if (NumZeroBits >= RegSize-8) 744 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 745 else if (NumSignBits > RegSize-16) 746 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 747 else if (NumZeroBits >= RegSize-16) 748 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 749 else if (NumSignBits > RegSize-32) 750 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 751 else if (NumZeroBits >= RegSize-32) 752 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 753 else 754 continue; 755 756 // Add an assertion node. 757 assert(FromVT != MVT::Other); 758 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 759 RegisterVT, P, DAG.getValueType(FromVT)); 760 } 761 762 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 763 NumRegs, RegisterVT, ValueVT, V); 764 Part += NumRegs; 765 Parts.clear(); 766 } 767 768 return DAG.getNode(ISD::MERGE_VALUES, dl, 769 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 770 &Values[0], ValueVTs.size()); 771} 772 773/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 774/// specified value into the registers specified by this object. This uses 775/// Chain/Flag as the input and updates them for the output Chain/Flag. 776/// If the Flag pointer is NULL, no flag is used. 777void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, 778 SDValue &Chain, SDValue *Flag, 779 const Value *V) const { 780 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 781 782 // Get the list of the values's legal parts. 783 unsigned NumRegs = Regs.size(); 784 SmallVector<SDValue, 8> Parts(NumRegs); 785 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 786 EVT ValueVT = ValueVTs[Value]; 787 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 788 MVT RegisterVT = RegVTs[Value]; 789 ISD::NodeType ExtendKind = 790 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND; 791 792 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 793 &Parts[Part], NumParts, RegisterVT, V, ExtendKind); 794 Part += NumParts; 795 } 796 797 // Copy the parts into the registers. 798 SmallVector<SDValue, 8> Chains(NumRegs); 799 for (unsigned i = 0; i != NumRegs; ++i) { 800 SDValue Part; 801 if (Flag == 0) { 802 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 803 } else { 804 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 805 *Flag = Part.getValue(1); 806 } 807 808 Chains[i] = Part.getValue(0); 809 } 810 811 if (NumRegs == 1 || Flag) 812 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 813 // flagged to it. That is the CopyToReg nodes and the user are considered 814 // a single scheduling unit. If we create a TokenFactor and return it as 815 // chain, then the TokenFactor is both a predecessor (operand) of the 816 // user as well as a successor (the TF operands are flagged to the user). 817 // c1, f1 = CopyToReg 818 // c2, f2 = CopyToReg 819 // c3 = TokenFactor c1, c2 820 // ... 821 // = op c3, ..., f2 822 Chain = Chains[NumRegs-1]; 823 else 824 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 825} 826 827/// AddInlineAsmOperands - Add this value to the specified inlineasm node 828/// operand list. This adds the code marker and includes the number of 829/// values added into it. 830void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 831 unsigned MatchingIdx, 832 SelectionDAG &DAG, 833 std::vector<SDValue> &Ops) const { 834 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 835 836 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 837 if (HasMatching) 838 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 839 else if (!Regs.empty() && 840 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 841 // Put the register class of the virtual registers in the flag word. That 842 // way, later passes can recompute register class constraints for inline 843 // assembly as well as normal instructions. 844 // Don't do this for tied operands that can use the regclass information 845 // from the def. 846 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 847 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 848 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 849 } 850 851 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 852 Ops.push_back(Res); 853 854 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 855 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 856 MVT RegisterVT = RegVTs[Value]; 857 for (unsigned i = 0; i != NumRegs; ++i) { 858 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 859 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 860 } 861 } 862} 863 864void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa, 865 const TargetLibraryInfo *li) { 866 AA = &aa; 867 GFI = gfi; 868 LibInfo = li; 869 TD = DAG.getTarget().getDataLayout(); 870 Context = DAG.getContext(); 871 LPadToCallSiteMap.clear(); 872} 873 874/// clear - Clear out the current SelectionDAG and the associated 875/// state and prepare this SelectionDAGBuilder object to be used 876/// for a new block. This doesn't clear out information about 877/// additional blocks that are needed to complete switch lowering 878/// or PHI node updating; that information is cleared out as it is 879/// consumed. 880void SelectionDAGBuilder::clear() { 881 NodeMap.clear(); 882 UnusedArgNodeMap.clear(); 883 PendingLoads.clear(); 884 PendingExports.clear(); 885 CurInst = NULL; 886 HasTailCall = false; 887} 888 889/// clearDanglingDebugInfo - Clear the dangling debug information 890/// map. This function is separated from the clear so that debug 891/// information that is dangling in a basic block can be properly 892/// resolved in a different basic block. This allows the 893/// SelectionDAG to resolve dangling debug information attached 894/// to PHI nodes. 895void SelectionDAGBuilder::clearDanglingDebugInfo() { 896 DanglingDebugInfoMap.clear(); 897} 898 899/// getRoot - Return the current virtual root of the Selection DAG, 900/// flushing any PendingLoad items. This must be done before emitting 901/// a store or any other node that may need to be ordered after any 902/// prior load instructions. 903/// 904SDValue SelectionDAGBuilder::getRoot() { 905 if (PendingLoads.empty()) 906 return DAG.getRoot(); 907 908 if (PendingLoads.size() == 1) { 909 SDValue Root = PendingLoads[0]; 910 DAG.setRoot(Root); 911 PendingLoads.clear(); 912 return Root; 913 } 914 915 // Otherwise, we have to make a token factor node. 916 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, 917 &PendingLoads[0], PendingLoads.size()); 918 PendingLoads.clear(); 919 DAG.setRoot(Root); 920 return Root; 921} 922 923/// getControlRoot - Similar to getRoot, but instead of flushing all the 924/// PendingLoad items, flush all the PendingExports items. It is necessary 925/// to do this before emitting a terminator instruction. 926/// 927SDValue SelectionDAGBuilder::getControlRoot() { 928 SDValue Root = DAG.getRoot(); 929 930 if (PendingExports.empty()) 931 return Root; 932 933 // Turn all of the CopyToReg chains into one factored node. 934 if (Root.getOpcode() != ISD::EntryToken) { 935 unsigned i = 0, e = PendingExports.size(); 936 for (; i != e; ++i) { 937 assert(PendingExports[i].getNode()->getNumOperands() > 1); 938 if (PendingExports[i].getNode()->getOperand(0) == Root) 939 break; // Don't add the root if we already indirectly depend on it. 940 } 941 942 if (i == e) 943 PendingExports.push_back(Root); 944 } 945 946 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, 947 &PendingExports[0], 948 PendingExports.size()); 949 PendingExports.clear(); 950 DAG.setRoot(Root); 951 return Root; 952} 953 954void SelectionDAGBuilder::visit(const Instruction &I) { 955 // Set up outgoing PHI node register values before emitting the terminator. 956 if (isa<TerminatorInst>(&I)) 957 HandlePHINodesInSuccessorBlocks(I.getParent()); 958 959 ++SDNodeOrder; 960 961 CurInst = &I; 962 963 visit(I.getOpcode(), I); 964 965 if (!isa<TerminatorInst>(&I) && !HasTailCall) 966 CopyToExportRegsIfNeeded(&I); 967 968 CurInst = NULL; 969} 970 971void SelectionDAGBuilder::visitPHI(const PHINode &) { 972 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 973} 974 975void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 976 // Note: this doesn't use InstVisitor, because it has to work with 977 // ConstantExpr's in addition to instructions. 978 switch (Opcode) { 979 default: llvm_unreachable("Unknown instruction type encountered!"); 980 // Build the switch statement using the Instruction.def file. 981#define HANDLE_INST(NUM, OPCODE, CLASS) \ 982 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break; 983#include "llvm/IR/Instruction.def" 984 } 985} 986 987// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 988// generate the debug data structures now that we've seen its definition. 989void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 990 SDValue Val) { 991 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 992 if (DDI.getDI()) { 993 const DbgValueInst *DI = DDI.getDI(); 994 DebugLoc dl = DDI.getdl(); 995 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 996 MDNode *Variable = DI->getVariable(); 997 uint64_t Offset = DI->getOffset(); 998 SDDbgValue *SDV; 999 if (Val.getNode()) { 1000 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 1001 SDV = DAG.getDbgValue(Variable, Val.getNode(), 1002 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 1003 DAG.AddDbgValue(SDV, Val.getNode(), false); 1004 } 1005 } else 1006 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); 1007 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 1008 } 1009} 1010 1011/// getValue - Return an SDValue for the given Value. 1012SDValue SelectionDAGBuilder::getValue(const Value *V) { 1013 // If we already have an SDValue for this value, use it. It's important 1014 // to do this first, so that we don't create a CopyFromReg if we already 1015 // have a regular SDValue. 1016 SDValue &N = NodeMap[V]; 1017 if (N.getNode()) return N; 1018 1019 // If there's a virtual register allocated and initialized for this 1020 // value, use it. 1021 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 1022 if (It != FuncInfo.ValueMap.end()) { 1023 unsigned InReg = It->second; 1024 RegsForValue RFV(*DAG.getContext(), *TM.getTargetLowering(), 1025 InReg, V->getType()); 1026 SDValue Chain = DAG.getEntryNode(); 1027 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V); 1028 resolveDanglingDebugInfo(V, N); 1029 return N; 1030 } 1031 1032 // Otherwise create a new SDValue and remember it. 1033 SDValue Val = getValueImpl(V); 1034 NodeMap[V] = Val; 1035 resolveDanglingDebugInfo(V, Val); 1036 return Val; 1037} 1038 1039/// getNonRegisterValue - Return an SDValue for the given Value, but 1040/// don't look in FuncInfo.ValueMap for a virtual register. 1041SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1042 // If we already have an SDValue for this value, use it. 1043 SDValue &N = NodeMap[V]; 1044 if (N.getNode()) return N; 1045 1046 // Otherwise create a new SDValue and remember it. 1047 SDValue Val = getValueImpl(V); 1048 NodeMap[V] = Val; 1049 resolveDanglingDebugInfo(V, Val); 1050 return Val; 1051} 1052 1053/// getValueImpl - Helper function for getValue and getNonRegisterValue. 1054/// Create an SDValue for the given value. 1055SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1056 const TargetLowering *TLI = TM.getTargetLowering(); 1057 1058 if (const Constant *C = dyn_cast<Constant>(V)) { 1059 EVT VT = TLI->getValueType(V->getType(), true); 1060 1061 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1062 return DAG.getConstant(*CI, VT); 1063 1064 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1065 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT); 1066 1067 if (isa<ConstantPointerNull>(C)) { 1068 unsigned AS = V->getType()->getPointerAddressSpace(); 1069 return DAG.getConstant(0, TLI->getPointerTy(AS)); 1070 } 1071 1072 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1073 return DAG.getConstantFP(*CFP, VT); 1074 1075 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1076 return DAG.getUNDEF(VT); 1077 1078 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1079 visit(CE->getOpcode(), *CE); 1080 SDValue N1 = NodeMap[V]; 1081 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1082 return N1; 1083 } 1084 1085 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1086 SmallVector<SDValue, 4> Constants; 1087 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1088 OI != OE; ++OI) { 1089 SDNode *Val = getValue(*OI).getNode(); 1090 // If the operand is an empty aggregate, there are no values. 1091 if (!Val) continue; 1092 // Add each leaf value from the operand to the Constants list 1093 // to form a flattened list of all the values. 1094 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1095 Constants.push_back(SDValue(Val, i)); 1096 } 1097 1098 return DAG.getMergeValues(&Constants[0], Constants.size(), 1099 getCurSDLoc()); 1100 } 1101 1102 if (const ConstantDataSequential *CDS = 1103 dyn_cast<ConstantDataSequential>(C)) { 1104 SmallVector<SDValue, 4> Ops; 1105 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) { 1106 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode(); 1107 // Add each leaf value from the operand to the Constants list 1108 // to form a flattened list of all the values. 1109 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1110 Ops.push_back(SDValue(Val, i)); 1111 } 1112 1113 if (isa<ArrayType>(CDS->getType())) 1114 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc()); 1115 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), 1116 VT, &Ops[0], Ops.size()); 1117 } 1118 1119 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1120 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1121 "Unknown struct or array constant!"); 1122 1123 SmallVector<EVT, 4> ValueVTs; 1124 ComputeValueVTs(*TLI, C->getType(), ValueVTs); 1125 unsigned NumElts = ValueVTs.size(); 1126 if (NumElts == 0) 1127 return SDValue(); // empty struct 1128 SmallVector<SDValue, 4> Constants(NumElts); 1129 for (unsigned i = 0; i != NumElts; ++i) { 1130 EVT EltVT = ValueVTs[i]; 1131 if (isa<UndefValue>(C)) 1132 Constants[i] = DAG.getUNDEF(EltVT); 1133 else if (EltVT.isFloatingPoint()) 1134 Constants[i] = DAG.getConstantFP(0, EltVT); 1135 else 1136 Constants[i] = DAG.getConstant(0, EltVT); 1137 } 1138 1139 return DAG.getMergeValues(&Constants[0], NumElts, 1140 getCurSDLoc()); 1141 } 1142 1143 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1144 return DAG.getBlockAddress(BA, VT); 1145 1146 VectorType *VecTy = cast<VectorType>(V->getType()); 1147 unsigned NumElements = VecTy->getNumElements(); 1148 1149 // Now that we know the number and type of the elements, get that number of 1150 // elements into the Ops array based on what kind of constant it is. 1151 SmallVector<SDValue, 16> Ops; 1152 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) { 1153 for (unsigned i = 0; i != NumElements; ++i) 1154 Ops.push_back(getValue(CV->getOperand(i))); 1155 } else { 1156 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1157 EVT EltVT = TLI->getValueType(VecTy->getElementType()); 1158 1159 SDValue Op; 1160 if (EltVT.isFloatingPoint()) 1161 Op = DAG.getConstantFP(0, EltVT); 1162 else 1163 Op = DAG.getConstant(0, EltVT); 1164 Ops.assign(NumElements, Op); 1165 } 1166 1167 // Create a BUILD_VECTOR node. 1168 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), 1169 VT, &Ops[0], Ops.size()); 1170 } 1171 1172 // If this is a static alloca, generate it as the frameindex instead of 1173 // computation. 1174 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1175 DenseMap<const AllocaInst*, int>::iterator SI = 1176 FuncInfo.StaticAllocaMap.find(AI); 1177 if (SI != FuncInfo.StaticAllocaMap.end()) 1178 return DAG.getFrameIndex(SI->second, TLI->getPointerTy()); 1179 } 1180 1181 // If this is an instruction which fast-isel has deferred, select it now. 1182 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1183 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1184 RegsForValue RFV(*DAG.getContext(), *TLI, InReg, Inst->getType()); 1185 SDValue Chain = DAG.getEntryNode(); 1186 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, NULL, V); 1187 } 1188 1189 llvm_unreachable("Can't get register for value!"); 1190} 1191 1192void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1193 const TargetLowering *TLI = TM.getTargetLowering(); 1194 SDValue Chain = getControlRoot(); 1195 SmallVector<ISD::OutputArg, 8> Outs; 1196 SmallVector<SDValue, 8> OutVals; 1197 1198 if (!FuncInfo.CanLowerReturn) { 1199 unsigned DemoteReg = FuncInfo.DemoteRegister; 1200 const Function *F = I.getParent()->getParent(); 1201 1202 // Emit a store of the return value through the virtual register. 1203 // Leave Outs empty so that LowerReturn won't try to load return 1204 // registers the usual way. 1205 SmallVector<EVT, 1> PtrValueVTs; 1206 ComputeValueVTs(*TLI, PointerType::getUnqual(F->getReturnType()), 1207 PtrValueVTs); 1208 1209 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1210 SDValue RetOp = getValue(I.getOperand(0)); 1211 1212 SmallVector<EVT, 4> ValueVTs; 1213 SmallVector<uint64_t, 4> Offsets; 1214 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1215 unsigned NumValues = ValueVTs.size(); 1216 1217 SmallVector<SDValue, 4> Chains(NumValues); 1218 for (unsigned i = 0; i != NumValues; ++i) { 1219 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), 1220 RetPtr.getValueType(), RetPtr, 1221 DAG.getIntPtrConstant(Offsets[i])); 1222 Chains[i] = 1223 DAG.getStore(Chain, getCurSDLoc(), 1224 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1225 // FIXME: better loc info would be nice. 1226 Add, MachinePointerInfo(), false, false, 0); 1227 } 1228 1229 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 1230 MVT::Other, &Chains[0], NumValues); 1231 } else if (I.getNumOperands() != 0) { 1232 SmallVector<EVT, 4> ValueVTs; 1233 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs); 1234 unsigned NumValues = ValueVTs.size(); 1235 if (NumValues) { 1236 SDValue RetOp = getValue(I.getOperand(0)); 1237 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1238 EVT VT = ValueVTs[j]; 1239 1240 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1241 1242 const Function *F = I.getParent()->getParent(); 1243 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex, 1244 Attribute::SExt)) 1245 ExtendKind = ISD::SIGN_EXTEND; 1246 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex, 1247 Attribute::ZExt)) 1248 ExtendKind = ISD::ZERO_EXTEND; 1249 1250 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1251 VT = TLI->getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind); 1252 1253 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), VT); 1254 MVT PartVT = TLI->getRegisterType(*DAG.getContext(), VT); 1255 SmallVector<SDValue, 4> Parts(NumParts); 1256 getCopyToParts(DAG, getCurSDLoc(), 1257 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1258 &Parts[0], NumParts, PartVT, &I, ExtendKind); 1259 1260 // 'inreg' on function refers to return value 1261 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1262 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex, 1263 Attribute::InReg)) 1264 Flags.setInReg(); 1265 1266 // Propagate extension type if any 1267 if (ExtendKind == ISD::SIGN_EXTEND) 1268 Flags.setSExt(); 1269 else if (ExtendKind == ISD::ZERO_EXTEND) 1270 Flags.setZExt(); 1271 1272 for (unsigned i = 0; i < NumParts; ++i) { 1273 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1274 VT, /*isfixed=*/true, 0, 0)); 1275 OutVals.push_back(Parts[i]); 1276 } 1277 } 1278 } 1279 } 1280 1281 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1282 CallingConv::ID CallConv = 1283 DAG.getMachineFunction().getFunction()->getCallingConv(); 1284 Chain = TM.getTargetLowering()->LowerReturn(Chain, CallConv, isVarArg, 1285 Outs, OutVals, getCurSDLoc(), 1286 DAG); 1287 1288 // Verify that the target's LowerReturn behaved as expected. 1289 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1290 "LowerReturn didn't return a valid chain!"); 1291 1292 // Update the DAG with the new chain value resulting from return lowering. 1293 DAG.setRoot(Chain); 1294} 1295 1296/// CopyToExportRegsIfNeeded - If the given value has virtual registers 1297/// created for it, emit nodes to copy the value into the virtual 1298/// registers. 1299void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1300 // Skip empty types 1301 if (V->getType()->isEmptyTy()) 1302 return; 1303 1304 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1305 if (VMI != FuncInfo.ValueMap.end()) { 1306 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1307 CopyValueToVirtualRegister(V, VMI->second); 1308 } 1309} 1310 1311/// ExportFromCurrentBlock - If this condition isn't known to be exported from 1312/// the current basic block, add it to ValueMap now so that we'll get a 1313/// CopyTo/FromReg. 1314void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1315 // No need to export constants. 1316 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1317 1318 // Already exported? 1319 if (FuncInfo.isExportedInst(V)) return; 1320 1321 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1322 CopyValueToVirtualRegister(V, Reg); 1323} 1324 1325bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1326 const BasicBlock *FromBB) { 1327 // The operands of the setcc have to be in this block. We don't know 1328 // how to export them from some other block. 1329 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1330 // Can export from current BB. 1331 if (VI->getParent() == FromBB) 1332 return true; 1333 1334 // Is already exported, noop. 1335 return FuncInfo.isExportedInst(V); 1336 } 1337 1338 // If this is an argument, we can export it if the BB is the entry block or 1339 // if it is already exported. 1340 if (isa<Argument>(V)) { 1341 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1342 return true; 1343 1344 // Otherwise, can only export this if it is already exported. 1345 return FuncInfo.isExportedInst(V); 1346 } 1347 1348 // Otherwise, constants can always be exported. 1349 return true; 1350} 1351 1352/// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1353uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src, 1354 const MachineBasicBlock *Dst) const { 1355 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1356 if (!BPI) 1357 return 0; 1358 const BasicBlock *SrcBB = Src->getBasicBlock(); 1359 const BasicBlock *DstBB = Dst->getBasicBlock(); 1360 return BPI->getEdgeWeight(SrcBB, DstBB); 1361} 1362 1363void SelectionDAGBuilder:: 1364addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1365 uint32_t Weight /* = 0 */) { 1366 if (!Weight) 1367 Weight = getEdgeWeight(Src, Dst); 1368 Src->addSuccessor(Dst, Weight); 1369} 1370 1371 1372static bool InBlock(const Value *V, const BasicBlock *BB) { 1373 if (const Instruction *I = dyn_cast<Instruction>(V)) 1374 return I->getParent() == BB; 1375 return true; 1376} 1377 1378/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1379/// This function emits a branch and is used at the leaves of an OR or an 1380/// AND operator tree. 1381/// 1382void 1383SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1384 MachineBasicBlock *TBB, 1385 MachineBasicBlock *FBB, 1386 MachineBasicBlock *CurBB, 1387 MachineBasicBlock *SwitchBB) { 1388 const BasicBlock *BB = CurBB->getBasicBlock(); 1389 1390 // If the leaf of the tree is a comparison, merge the condition into 1391 // the caseblock. 1392 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1393 // The operands of the cmp have to be in this block. We don't know 1394 // how to export them from some other block. If this is the first block 1395 // of the sequence, no exporting is needed. 1396 if (CurBB == SwitchBB || 1397 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1398 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1399 ISD::CondCode Condition; 1400 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1401 Condition = getICmpCondCode(IC->getPredicate()); 1402 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1403 Condition = getFCmpCondCode(FC->getPredicate()); 1404 if (TM.Options.NoNaNsFPMath) 1405 Condition = getFCmpCodeWithoutNaN(Condition); 1406 } else { 1407 Condition = ISD::SETEQ; // silence warning. 1408 llvm_unreachable("Unknown compare instruction"); 1409 } 1410 1411 CaseBlock CB(Condition, BOp->getOperand(0), 1412 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1413 SwitchCases.push_back(CB); 1414 return; 1415 } 1416 } 1417 1418 // Create a CaseBlock record representing this branch. 1419 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1420 NULL, TBB, FBB, CurBB); 1421 SwitchCases.push_back(CB); 1422} 1423 1424/// FindMergedConditions - If Cond is an expression like 1425void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1426 MachineBasicBlock *TBB, 1427 MachineBasicBlock *FBB, 1428 MachineBasicBlock *CurBB, 1429 MachineBasicBlock *SwitchBB, 1430 unsigned Opc) { 1431 // If this node is not part of the or/and tree, emit it as a branch. 1432 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1433 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1434 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1435 BOp->getParent() != CurBB->getBasicBlock() || 1436 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1437 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1438 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1439 return; 1440 } 1441 1442 // Create TmpBB after CurBB. 1443 MachineFunction::iterator BBI = CurBB; 1444 MachineFunction &MF = DAG.getMachineFunction(); 1445 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1446 CurBB->getParent()->insert(++BBI, TmpBB); 1447 1448 if (Opc == Instruction::Or) { 1449 // Codegen X | Y as: 1450 // jmp_if_X TBB 1451 // jmp TmpBB 1452 // TmpBB: 1453 // jmp_if_Y TBB 1454 // jmp FBB 1455 // 1456 1457 // Emit the LHS condition. 1458 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1459 1460 // Emit the RHS condition into TmpBB. 1461 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1462 } else { 1463 assert(Opc == Instruction::And && "Unknown merge op!"); 1464 // Codegen X & Y as: 1465 // jmp_if_X TmpBB 1466 // jmp FBB 1467 // TmpBB: 1468 // jmp_if_Y TBB 1469 // jmp FBB 1470 // 1471 // This requires creation of TmpBB after CurBB. 1472 1473 // Emit the LHS condition. 1474 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1475 1476 // Emit the RHS condition into TmpBB. 1477 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1478 } 1479} 1480 1481/// If the set of cases should be emitted as a series of branches, return true. 1482/// If we should emit this as a bunch of and/or'd together conditions, return 1483/// false. 1484bool 1485SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) { 1486 if (Cases.size() != 2) return true; 1487 1488 // If this is two comparisons of the same values or'd or and'd together, they 1489 // will get folded into a single comparison, so don't emit two blocks. 1490 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1491 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1492 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1493 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1494 return false; 1495 } 1496 1497 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1498 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1499 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1500 Cases[0].CC == Cases[1].CC && 1501 isa<Constant>(Cases[0].CmpRHS) && 1502 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1503 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1504 return false; 1505 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1506 return false; 1507 } 1508 1509 return true; 1510} 1511 1512void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1513 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1514 1515 // Update machine-CFG edges. 1516 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1517 1518 // Figure out which block is immediately after the current one. 1519 MachineBasicBlock *NextBlock = 0; 1520 MachineFunction::iterator BBI = BrMBB; 1521 if (++BBI != FuncInfo.MF->end()) 1522 NextBlock = BBI; 1523 1524 if (I.isUnconditional()) { 1525 // Update machine-CFG edges. 1526 BrMBB->addSuccessor(Succ0MBB); 1527 1528 // If this is not a fall-through branch, emit the branch. 1529 if (Succ0MBB != NextBlock) 1530 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), 1531 MVT::Other, getControlRoot(), 1532 DAG.getBasicBlock(Succ0MBB))); 1533 1534 return; 1535 } 1536 1537 // If this condition is one of the special cases we handle, do special stuff 1538 // now. 1539 const Value *CondVal = I.getCondition(); 1540 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1541 1542 // If this is a series of conditions that are or'd or and'd together, emit 1543 // this as a sequence of branches instead of setcc's with and/or operations. 1544 // As long as jumps are not expensive, this should improve performance. 1545 // For example, instead of something like: 1546 // cmp A, B 1547 // C = seteq 1548 // cmp D, E 1549 // F = setle 1550 // or C, F 1551 // jnz foo 1552 // Emit: 1553 // cmp A, B 1554 // je foo 1555 // cmp D, E 1556 // jle foo 1557 // 1558 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1559 if (!TM.getTargetLowering()->isJumpExpensive() && 1560 BOp->hasOneUse() && 1561 (BOp->getOpcode() == Instruction::And || 1562 BOp->getOpcode() == Instruction::Or)) { 1563 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1564 BOp->getOpcode()); 1565 // If the compares in later blocks need to use values not currently 1566 // exported from this block, export them now. This block should always 1567 // be the first entry. 1568 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1569 1570 // Allow some cases to be rejected. 1571 if (ShouldEmitAsBranches(SwitchCases)) { 1572 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1573 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1574 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1575 } 1576 1577 // Emit the branch for this block. 1578 visitSwitchCase(SwitchCases[0], BrMBB); 1579 SwitchCases.erase(SwitchCases.begin()); 1580 return; 1581 } 1582 1583 // Okay, we decided not to do this, remove any inserted MBB's and clear 1584 // SwitchCases. 1585 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1586 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1587 1588 SwitchCases.clear(); 1589 } 1590 } 1591 1592 // Create a CaseBlock record representing this branch. 1593 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1594 NULL, Succ0MBB, Succ1MBB, BrMBB); 1595 1596 // Use visitSwitchCase to actually insert the fast branch sequence for this 1597 // cond branch. 1598 visitSwitchCase(CB, BrMBB); 1599} 1600 1601/// visitSwitchCase - Emits the necessary code to represent a single node in 1602/// the binary search tree resulting from lowering a switch instruction. 1603void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1604 MachineBasicBlock *SwitchBB) { 1605 SDValue Cond; 1606 SDValue CondLHS = getValue(CB.CmpLHS); 1607 SDLoc dl = getCurSDLoc(); 1608 1609 // Build the setcc now. 1610 if (CB.CmpMHS == NULL) { 1611 // Fold "(X == true)" to X and "(X == false)" to !X to 1612 // handle common cases produced by branch lowering. 1613 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1614 CB.CC == ISD::SETEQ) 1615 Cond = CondLHS; 1616 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1617 CB.CC == ISD::SETEQ) { 1618 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1619 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1620 } else 1621 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1622 } else { 1623 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1624 1625 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1626 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1627 1628 SDValue CmpOp = getValue(CB.CmpMHS); 1629 EVT VT = CmpOp.getValueType(); 1630 1631 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1632 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1633 ISD::SETLE); 1634 } else { 1635 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1636 VT, CmpOp, DAG.getConstant(Low, VT)); 1637 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1638 DAG.getConstant(High-Low, VT), ISD::SETULE); 1639 } 1640 } 1641 1642 // Update successor info 1643 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1644 // TrueBB and FalseBB are always different unless the incoming IR is 1645 // degenerate. This only happens when running llc on weird IR. 1646 if (CB.TrueBB != CB.FalseBB) 1647 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1648 1649 // Set NextBlock to be the MBB immediately after the current one, if any. 1650 // This is used to avoid emitting unnecessary branches to the next block. 1651 MachineBasicBlock *NextBlock = 0; 1652 MachineFunction::iterator BBI = SwitchBB; 1653 if (++BBI != FuncInfo.MF->end()) 1654 NextBlock = BBI; 1655 1656 // If the lhs block is the next block, invert the condition so that we can 1657 // fall through to the lhs instead of the rhs block. 1658 if (CB.TrueBB == NextBlock) { 1659 std::swap(CB.TrueBB, CB.FalseBB); 1660 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1661 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1662 } 1663 1664 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1665 MVT::Other, getControlRoot(), Cond, 1666 DAG.getBasicBlock(CB.TrueBB)); 1667 1668 // Insert the false branch. Do this even if it's a fall through branch, 1669 // this makes it easier to do DAG optimizations which require inverting 1670 // the branch condition. 1671 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1672 DAG.getBasicBlock(CB.FalseBB)); 1673 1674 DAG.setRoot(BrCond); 1675} 1676 1677/// visitJumpTable - Emit JumpTable node in the current MBB 1678void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1679 // Emit the code for the jump table 1680 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1681 EVT PTy = TM.getTargetLowering()->getPointerTy(); 1682 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(), 1683 JT.Reg, PTy); 1684 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1685 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(), 1686 MVT::Other, Index.getValue(1), 1687 Table, Index); 1688 DAG.setRoot(BrJumpTable); 1689} 1690 1691/// visitJumpTableHeader - This function emits necessary code to produce index 1692/// in the JumpTable from switch case. 1693void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1694 JumpTableHeader &JTH, 1695 MachineBasicBlock *SwitchBB) { 1696 // Subtract the lowest switch case value from the value being switched on and 1697 // conditional branch to default mbb if the result is greater than the 1698 // difference between smallest and largest cases. 1699 SDValue SwitchOp = getValue(JTH.SValue); 1700 EVT VT = SwitchOp.getValueType(); 1701 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp, 1702 DAG.getConstant(JTH.First, VT)); 1703 1704 // The SDNode we just created, which holds the value being switched on minus 1705 // the smallest case value, needs to be copied to a virtual register so it 1706 // can be used as an index into the jump table in a subsequent basic block. 1707 // This value may be smaller or larger than the target's pointer type, and 1708 // therefore require extension or truncating. 1709 const TargetLowering *TLI = TM.getTargetLowering(); 1710 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI->getPointerTy()); 1711 1712 unsigned JumpTableReg = FuncInfo.CreateReg(TLI->getPointerTy()); 1713 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(), 1714 JumpTableReg, SwitchOp); 1715 JT.Reg = JumpTableReg; 1716 1717 // Emit the range check for the jump table, and branch to the default block 1718 // for the switch statement if the value being switched on exceeds the largest 1719 // case in the switch. 1720 SDValue CMP = DAG.getSetCC(getCurSDLoc(), 1721 TLI->getSetCCResultType(*DAG.getContext(), 1722 Sub.getValueType()), 1723 Sub, 1724 DAG.getConstant(JTH.Last - JTH.First,VT), 1725 ISD::SETUGT); 1726 1727 // Set NextBlock to be the MBB immediately after the current one, if any. 1728 // This is used to avoid emitting unnecessary branches to the next block. 1729 MachineBasicBlock *NextBlock = 0; 1730 MachineFunction::iterator BBI = SwitchBB; 1731 1732 if (++BBI != FuncInfo.MF->end()) 1733 NextBlock = BBI; 1734 1735 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(), 1736 MVT::Other, CopyTo, CMP, 1737 DAG.getBasicBlock(JT.Default)); 1738 1739 if (JT.MBB != NextBlock) 1740 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond, 1741 DAG.getBasicBlock(JT.MBB)); 1742 1743 DAG.setRoot(BrCond); 1744} 1745 1746/// Codegen a new tail for a stack protector check ParentMBB which has had its 1747/// tail spliced into a stack protector check success bb. 1748/// 1749/// For a high level explanation of how this fits into the stack protector 1750/// generation see the comment on the declaration of class 1751/// StackProtectorDescriptor. 1752void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD, 1753 MachineBasicBlock *ParentBB) { 1754 1755 // First create the loads to the guard/stack slot for the comparison. 1756 const TargetLowering *TLI = TM.getTargetLowering(); 1757 EVT PtrTy = TLI->getPointerTy(); 1758 1759 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo(); 1760 int FI = MFI->getStackProtectorIndex(); 1761 1762 const Value *IRGuard = SPD.getGuard(); 1763 SDValue GuardPtr = getValue(IRGuard); 1764 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy); 1765 1766 unsigned Align = 1767 TLI->getDataLayout()->getPrefTypeAlignment(IRGuard->getType()); 1768 SDValue Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(), 1769 GuardPtr, MachinePointerInfo(IRGuard, 0), 1770 true, false, false, Align); 1771 1772 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(), 1773 StackSlotPtr, 1774 MachinePointerInfo::getFixedStack(FI), 1775 true, false, false, Align); 1776 1777 // Perform the comparison via a subtract/getsetcc. 1778 EVT VT = Guard.getValueType(); 1779 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot); 1780 1781 SDValue Cmp = DAG.getSetCC(getCurSDLoc(), 1782 TLI->getSetCCResultType(*DAG.getContext(), 1783 Sub.getValueType()), 1784 Sub, DAG.getConstant(0, VT), 1785 ISD::SETNE); 1786 1787 // If the sub is not 0, then we know the guard/stackslot do not equal, so 1788 // branch to failure MBB. 1789 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(), 1790 MVT::Other, StackSlot.getOperand(0), 1791 Cmp, DAG.getBasicBlock(SPD.getFailureMBB())); 1792 // Otherwise branch to success MBB. 1793 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(), 1794 MVT::Other, BrCond, 1795 DAG.getBasicBlock(SPD.getSuccessMBB())); 1796 1797 DAG.setRoot(Br); 1798} 1799 1800/// Codegen the failure basic block for a stack protector check. 1801/// 1802/// A failure stack protector machine basic block consists simply of a call to 1803/// __stack_chk_fail(). 1804/// 1805/// For a high level explanation of how this fits into the stack protector 1806/// generation see the comment on the declaration of class 1807/// StackProtectorDescriptor. 1808void 1809SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) { 1810 const TargetLowering *TLI = TM.getTargetLowering(); 1811 SDValue Chain = TLI->makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, 1812 MVT::isVoid, 0, 0, false, getCurSDLoc(), 1813 false, false).second; 1814 DAG.setRoot(Chain); 1815} 1816 1817/// visitBitTestHeader - This function emits necessary code to produce value 1818/// suitable for "bit tests" 1819void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1820 MachineBasicBlock *SwitchBB) { 1821 // Subtract the minimum value 1822 SDValue SwitchOp = getValue(B.SValue); 1823 EVT VT = SwitchOp.getValueType(); 1824 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp, 1825 DAG.getConstant(B.First, VT)); 1826 1827 // Check range 1828 const TargetLowering *TLI = TM.getTargetLowering(); 1829 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(), 1830 TLI->getSetCCResultType(*DAG.getContext(), 1831 Sub.getValueType()), 1832 Sub, DAG.getConstant(B.Range, VT), 1833 ISD::SETUGT); 1834 1835 // Determine the type of the test operands. 1836 bool UsePtrType = false; 1837 if (!TLI->isTypeLegal(VT)) 1838 UsePtrType = true; 1839 else { 1840 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1841 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1842 // Switch table case range are encoded into series of masks. 1843 // Just use pointer type, it's guaranteed to fit. 1844 UsePtrType = true; 1845 break; 1846 } 1847 } 1848 if (UsePtrType) { 1849 VT = TLI->getPointerTy(); 1850 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT); 1851 } 1852 1853 B.RegVT = VT.getSimpleVT(); 1854 B.Reg = FuncInfo.CreateReg(B.RegVT); 1855 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(), 1856 B.Reg, Sub); 1857 1858 // Set NextBlock to be the MBB immediately after the current one, if any. 1859 // This is used to avoid emitting unnecessary branches to the next block. 1860 MachineBasicBlock *NextBlock = 0; 1861 MachineFunction::iterator BBI = SwitchBB; 1862 if (++BBI != FuncInfo.MF->end()) 1863 NextBlock = BBI; 1864 1865 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1866 1867 addSuccessorWithWeight(SwitchBB, B.Default); 1868 addSuccessorWithWeight(SwitchBB, MBB); 1869 1870 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(), 1871 MVT::Other, CopyTo, RangeCmp, 1872 DAG.getBasicBlock(B.Default)); 1873 1874 if (MBB != NextBlock) 1875 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo, 1876 DAG.getBasicBlock(MBB)); 1877 1878 DAG.setRoot(BrRange); 1879} 1880 1881/// visitBitTestCase - this function produces one "bit test" 1882void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1883 MachineBasicBlock* NextMBB, 1884 uint32_t BranchWeightToNext, 1885 unsigned Reg, 1886 BitTestCase &B, 1887 MachineBasicBlock *SwitchBB) { 1888 MVT VT = BB.RegVT; 1889 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(), 1890 Reg, VT); 1891 SDValue Cmp; 1892 unsigned PopCount = CountPopulation_64(B.Mask); 1893 const TargetLowering *TLI = TM.getTargetLowering(); 1894 if (PopCount == 1) { 1895 // Testing for a single bit; just compare the shift count with what it 1896 // would need to be to shift a 1 bit in that position. 1897 Cmp = DAG.getSetCC(getCurSDLoc(), 1898 TLI->getSetCCResultType(*DAG.getContext(), VT), 1899 ShiftOp, 1900 DAG.getConstant(countTrailingZeros(B.Mask), VT), 1901 ISD::SETEQ); 1902 } else if (PopCount == BB.Range) { 1903 // There is only one zero bit in the range, test for it directly. 1904 Cmp = DAG.getSetCC(getCurSDLoc(), 1905 TLI->getSetCCResultType(*DAG.getContext(), VT), 1906 ShiftOp, 1907 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1908 ISD::SETNE); 1909 } else { 1910 // Make desired shift 1911 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT, 1912 DAG.getConstant(1, VT), ShiftOp); 1913 1914 // Emit bit tests and jumps 1915 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(), 1916 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1917 Cmp = DAG.getSetCC(getCurSDLoc(), 1918 TLI->getSetCCResultType(*DAG.getContext(), VT), 1919 AndOp, DAG.getConstant(0, VT), 1920 ISD::SETNE); 1921 } 1922 1923 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight. 1924 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight); 1925 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext. 1926 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext); 1927 1928 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(), 1929 MVT::Other, getControlRoot(), 1930 Cmp, DAG.getBasicBlock(B.TargetBB)); 1931 1932 // Set NextBlock to be the MBB immediately after the current one, if any. 1933 // This is used to avoid emitting unnecessary branches to the next block. 1934 MachineBasicBlock *NextBlock = 0; 1935 MachineFunction::iterator BBI = SwitchBB; 1936 if (++BBI != FuncInfo.MF->end()) 1937 NextBlock = BBI; 1938 1939 if (NextMBB != NextBlock) 1940 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd, 1941 DAG.getBasicBlock(NextMBB)); 1942 1943 DAG.setRoot(BrAnd); 1944} 1945 1946void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1947 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1948 1949 // Retrieve successors. 1950 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1951 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1952 1953 const Value *Callee(I.getCalledValue()); 1954 const Function *Fn = dyn_cast<Function>(Callee); 1955 if (isa<InlineAsm>(Callee)) 1956 visitInlineAsm(&I); 1957 else if (Fn && Fn->isIntrinsic()) { 1958 assert(Fn->getIntrinsicID() == Intrinsic::donothing); 1959 // Ignore invokes to @llvm.donothing: jump directly to the next BB. 1960 } else 1961 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1962 1963 // If the value of the invoke is used outside of its defining block, make it 1964 // available as a virtual register. 1965 CopyToExportRegsIfNeeded(&I); 1966 1967 // Update successor info 1968 addSuccessorWithWeight(InvokeMBB, Return); 1969 addSuccessorWithWeight(InvokeMBB, LandingPad); 1970 1971 // Drop into normal successor. 1972 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), 1973 MVT::Other, getControlRoot(), 1974 DAG.getBasicBlock(Return))); 1975} 1976 1977void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1978 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1979} 1980 1981void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1982 assert(FuncInfo.MBB->isLandingPad() && 1983 "Call to landingpad not in landing pad!"); 1984 1985 MachineBasicBlock *MBB = FuncInfo.MBB; 1986 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1987 AddLandingPadInfo(LP, MMI, MBB); 1988 1989 // If there aren't registers to copy the values into (e.g., during SjLj 1990 // exceptions), then don't bother to create these DAG nodes. 1991 const TargetLowering *TLI = TM.getTargetLowering(); 1992 if (TLI->getExceptionPointerRegister() == 0 && 1993 TLI->getExceptionSelectorRegister() == 0) 1994 return; 1995 1996 SmallVector<EVT, 2> ValueVTs; 1997 ComputeValueVTs(*TLI, LP.getType(), ValueVTs); 1998 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported"); 1999 2000 // Get the two live-in registers as SDValues. The physregs have already been 2001 // copied into virtual registers. 2002 SDValue Ops[2]; 2003 Ops[0] = DAG.getZExtOrTrunc( 2004 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), 2005 FuncInfo.ExceptionPointerVirtReg, TLI->getPointerTy()), 2006 getCurSDLoc(), ValueVTs[0]); 2007 Ops[1] = DAG.getZExtOrTrunc( 2008 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), 2009 FuncInfo.ExceptionSelectorVirtReg, TLI->getPointerTy()), 2010 getCurSDLoc(), ValueVTs[1]); 2011 2012 // Merge into one. 2013 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 2014 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 2015 &Ops[0], 2); 2016 setValue(&LP, Res); 2017} 2018 2019/// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 2020/// small case ranges). 2021bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 2022 CaseRecVector& WorkList, 2023 const Value* SV, 2024 MachineBasicBlock *Default, 2025 MachineBasicBlock *SwitchBB) { 2026 // Size is the number of Cases represented by this range. 2027 size_t Size = CR.Range.second - CR.Range.first; 2028 if (Size > 3) 2029 return false; 2030 2031 // Get the MachineFunction which holds the current MBB. This is used when 2032 // inserting any additional MBBs necessary to represent the switch. 2033 MachineFunction *CurMF = FuncInfo.MF; 2034 2035 // Figure out which block is immediately after the current one. 2036 MachineBasicBlock *NextBlock = 0; 2037 MachineFunction::iterator BBI = CR.CaseBB; 2038 2039 if (++BBI != FuncInfo.MF->end()) 2040 NextBlock = BBI; 2041 2042 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2043 // If any two of the cases has the same destination, and if one value 2044 // is the same as the other, but has one bit unset that the other has set, 2045 // use bit manipulation to do two compares at once. For example: 2046 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 2047 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 2048 // TODO: Handle cases where CR.CaseBB != SwitchBB. 2049 if (Size == 2 && CR.CaseBB == SwitchBB) { 2050 Case &Small = *CR.Range.first; 2051 Case &Big = *(CR.Range.second-1); 2052 2053 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 2054 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 2055 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 2056 2057 // Check that there is only one bit different. 2058 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 2059 (SmallValue | BigValue) == BigValue) { 2060 // Isolate the common bit. 2061 APInt CommonBit = BigValue & ~SmallValue; 2062 assert((SmallValue | CommonBit) == BigValue && 2063 CommonBit.countPopulation() == 1 && "Not a common bit?"); 2064 2065 SDValue CondLHS = getValue(SV); 2066 EVT VT = CondLHS.getValueType(); 2067 SDLoc DL = getCurSDLoc(); 2068 2069 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 2070 DAG.getConstant(CommonBit, VT)); 2071 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 2072 Or, DAG.getConstant(BigValue, VT), 2073 ISD::SETEQ); 2074 2075 // Update successor info. 2076 // Both Small and Big will jump to Small.BB, so we sum up the weights. 2077 addSuccessorWithWeight(SwitchBB, Small.BB, 2078 Small.ExtraWeight + Big.ExtraWeight); 2079 addSuccessorWithWeight(SwitchBB, Default, 2080 // The default destination is the first successor in IR. 2081 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0); 2082 2083 // Insert the true branch. 2084 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 2085 getControlRoot(), Cond, 2086 DAG.getBasicBlock(Small.BB)); 2087 2088 // Insert the false branch. 2089 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 2090 DAG.getBasicBlock(Default)); 2091 2092 DAG.setRoot(BrCond); 2093 return true; 2094 } 2095 } 2096 } 2097 2098 // Order cases by weight so the most likely case will be checked first. 2099 uint32_t UnhandledWeights = 0; 2100 if (BPI) { 2101 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) { 2102 uint32_t IWeight = I->ExtraWeight; 2103 UnhandledWeights += IWeight; 2104 for (CaseItr J = CR.Range.first; J < I; ++J) { 2105 uint32_t JWeight = J->ExtraWeight; 2106 if (IWeight > JWeight) 2107 std::swap(*I, *J); 2108 } 2109 } 2110 } 2111 // Rearrange the case blocks so that the last one falls through if possible. 2112 Case &BackCase = *(CR.Range.second-1); 2113 if (Size > 1 && 2114 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 2115 // The last case block won't fall through into 'NextBlock' if we emit the 2116 // branches in this order. See if rearranging a case value would help. 2117 // We start at the bottom as it's the case with the least weight. 2118 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I) 2119 if (I->BB == NextBlock) { 2120 std::swap(*I, BackCase); 2121 break; 2122 } 2123 } 2124 2125 // Create a CaseBlock record representing a conditional branch to 2126 // the Case's target mbb if the value being switched on SV is equal 2127 // to C. 2128 MachineBasicBlock *CurBlock = CR.CaseBB; 2129 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2130 MachineBasicBlock *FallThrough; 2131 if (I != E-1) { 2132 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 2133 CurMF->insert(BBI, FallThrough); 2134 2135 // Put SV in a virtual register to make it available from the new blocks. 2136 ExportFromCurrentBlock(SV); 2137 } else { 2138 // If the last case doesn't match, go to the default block. 2139 FallThrough = Default; 2140 } 2141 2142 const Value *RHS, *LHS, *MHS; 2143 ISD::CondCode CC; 2144 if (I->High == I->Low) { 2145 // This is just small small case range :) containing exactly 1 case 2146 CC = ISD::SETEQ; 2147 LHS = SV; RHS = I->High; MHS = NULL; 2148 } else { 2149 CC = ISD::SETLE; 2150 LHS = I->Low; MHS = SV; RHS = I->High; 2151 } 2152 2153 // The false weight should be sum of all un-handled cases. 2154 UnhandledWeights -= I->ExtraWeight; 2155 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 2156 /* me */ CurBlock, 2157 /* trueweight */ I->ExtraWeight, 2158 /* falseweight */ UnhandledWeights); 2159 2160 // If emitting the first comparison, just call visitSwitchCase to emit the 2161 // code into the current block. Otherwise, push the CaseBlock onto the 2162 // vector to be later processed by SDISel, and insert the node's MBB 2163 // before the next MBB. 2164 if (CurBlock == SwitchBB) 2165 visitSwitchCase(CB, SwitchBB); 2166 else 2167 SwitchCases.push_back(CB); 2168 2169 CurBlock = FallThrough; 2170 } 2171 2172 return true; 2173} 2174 2175static inline bool areJTsAllowed(const TargetLowering &TLI) { 2176 return TLI.supportJumpTables() && 2177 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2178 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2179} 2180 2181static APInt ComputeRange(const APInt &First, const APInt &Last) { 2182 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2183 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 2184 return (LastExt - FirstExt + 1ULL); 2185} 2186 2187/// handleJTSwitchCase - Emit jumptable for current switch case range 2188bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2189 CaseRecVector &WorkList, 2190 const Value *SV, 2191 MachineBasicBlock *Default, 2192 MachineBasicBlock *SwitchBB) { 2193 Case& FrontCase = *CR.Range.first; 2194 Case& BackCase = *(CR.Range.second-1); 2195 2196 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2197 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2198 2199 APInt TSize(First.getBitWidth(), 0); 2200 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2201 TSize += I->size(); 2202 2203 const TargetLowering *TLI = TM.getTargetLowering(); 2204 if (!areJTsAllowed(*TLI) || TSize.ult(TLI->getMinimumJumpTableEntries())) 2205 return false; 2206 2207 APInt Range = ComputeRange(First, Last); 2208 // The density is TSize / Range. Require at least 40%. 2209 // It should not be possible for IntTSize to saturate for sane code, but make 2210 // sure we handle Range saturation correctly. 2211 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10); 2212 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10); 2213 if (IntTSize * 10 < IntRange * 4) 2214 return false; 2215 2216 DEBUG(dbgs() << "Lowering jump table\n" 2217 << "First entry: " << First << ". Last entry: " << Last << '\n' 2218 << "Range: " << Range << ". Size: " << TSize << ".\n\n"); 2219 2220 // Get the MachineFunction which holds the current MBB. This is used when 2221 // inserting any additional MBBs necessary to represent the switch. 2222 MachineFunction *CurMF = FuncInfo.MF; 2223 2224 // Figure out which block is immediately after the current one. 2225 MachineFunction::iterator BBI = CR.CaseBB; 2226 ++BBI; 2227 2228 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2229 2230 // Create a new basic block to hold the code for loading the address 2231 // of the jump table, and jumping to it. Update successor information; 2232 // we will either branch to the default case for the switch, or the jump 2233 // table. 2234 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2235 CurMF->insert(BBI, JumpTableBB); 2236 2237 addSuccessorWithWeight(CR.CaseBB, Default); 2238 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2239 2240 // Build a vector of destination BBs, corresponding to each target 2241 // of the jump table. If the value of the jump table slot corresponds to 2242 // a case statement, push the case's BB onto the vector, otherwise, push 2243 // the default BB. 2244 std::vector<MachineBasicBlock*> DestBBs; 2245 APInt TEI = First; 2246 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2247 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2248 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2249 2250 if (Low.sle(TEI) && TEI.sle(High)) { 2251 DestBBs.push_back(I->BB); 2252 if (TEI==High) 2253 ++I; 2254 } else { 2255 DestBBs.push_back(Default); 2256 } 2257 } 2258 2259 // Calculate weight for each unique destination in CR. 2260 DenseMap<MachineBasicBlock*, uint32_t> DestWeights; 2261 if (FuncInfo.BPI) 2262 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 2263 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr = 2264 DestWeights.find(I->BB); 2265 if (Itr != DestWeights.end()) 2266 Itr->second += I->ExtraWeight; 2267 else 2268 DestWeights[I->BB] = I->ExtraWeight; 2269 } 2270 2271 // Update successor info. Add one edge to each unique successor. 2272 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2273 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2274 E = DestBBs.end(); I != E; ++I) { 2275 if (!SuccsHandled[(*I)->getNumber()]) { 2276 SuccsHandled[(*I)->getNumber()] = true; 2277 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr = 2278 DestWeights.find(*I); 2279 addSuccessorWithWeight(JumpTableBB, *I, 2280 Itr != DestWeights.end() ? Itr->second : 0); 2281 } 2282 } 2283 2284 // Create a jump table index for this jump table. 2285 unsigned JTEncoding = TLI->getJumpTableEncoding(); 2286 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2287 ->createJumpTableIndex(DestBBs); 2288 2289 // Set the jump table information so that we can codegen it as a second 2290 // MachineBasicBlock 2291 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2292 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2293 if (CR.CaseBB == SwitchBB) 2294 visitJumpTableHeader(JT, JTH, SwitchBB); 2295 2296 JTCases.push_back(JumpTableBlock(JTH, JT)); 2297 return true; 2298} 2299 2300/// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2301/// 2 subtrees. 2302bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2303 CaseRecVector& WorkList, 2304 const Value* SV, 2305 MachineBasicBlock* Default, 2306 MachineBasicBlock* SwitchBB) { 2307 // Get the MachineFunction which holds the current MBB. This is used when 2308 // inserting any additional MBBs necessary to represent the switch. 2309 MachineFunction *CurMF = FuncInfo.MF; 2310 2311 // Figure out which block is immediately after the current one. 2312 MachineFunction::iterator BBI = CR.CaseBB; 2313 ++BBI; 2314 2315 Case& FrontCase = *CR.Range.first; 2316 Case& BackCase = *(CR.Range.second-1); 2317 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2318 2319 // Size is the number of Cases represented by this range. 2320 unsigned Size = CR.Range.second - CR.Range.first; 2321 2322 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2323 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2324 double FMetric = 0; 2325 CaseItr Pivot = CR.Range.first + Size/2; 2326 2327 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2328 // (heuristically) allow us to emit JumpTable's later. 2329 APInt TSize(First.getBitWidth(), 0); 2330 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2331 I!=E; ++I) 2332 TSize += I->size(); 2333 2334 APInt LSize = FrontCase.size(); 2335 APInt RSize = TSize-LSize; 2336 DEBUG(dbgs() << "Selecting best pivot: \n" 2337 << "First: " << First << ", Last: " << Last <<'\n' 2338 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2339 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2340 J!=E; ++I, ++J) { 2341 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2342 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2343 APInt Range = ComputeRange(LEnd, RBegin); 2344 assert((Range - 2ULL).isNonNegative() && 2345 "Invalid case distance"); 2346 // Use volatile double here to avoid excess precision issues on some hosts, 2347 // e.g. that use 80-bit X87 registers. 2348 volatile double LDensity = 2349 (double)LSize.roundToDouble() / 2350 (LEnd - First + 1ULL).roundToDouble(); 2351 volatile double RDensity = 2352 (double)RSize.roundToDouble() / 2353 (Last - RBegin + 1ULL).roundToDouble(); 2354 double Metric = Range.logBase2()*(LDensity+RDensity); 2355 // Should always split in some non-trivial place 2356 DEBUG(dbgs() <<"=>Step\n" 2357 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2358 << "LDensity: " << LDensity 2359 << ", RDensity: " << RDensity << '\n' 2360 << "Metric: " << Metric << '\n'); 2361 if (FMetric < Metric) { 2362 Pivot = J; 2363 FMetric = Metric; 2364 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2365 } 2366 2367 LSize += J->size(); 2368 RSize -= J->size(); 2369 } 2370 2371 const TargetLowering *TLI = TM.getTargetLowering(); 2372 if (areJTsAllowed(*TLI)) { 2373 // If our case is dense we *really* should handle it earlier! 2374 assert((FMetric > 0) && "Should handle dense range earlier!"); 2375 } else { 2376 Pivot = CR.Range.first + Size/2; 2377 } 2378 2379 CaseRange LHSR(CR.Range.first, Pivot); 2380 CaseRange RHSR(Pivot, CR.Range.second); 2381 const Constant *C = Pivot->Low; 2382 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2383 2384 // We know that we branch to the LHS if the Value being switched on is 2385 // less than the Pivot value, C. We use this to optimize our binary 2386 // tree a bit, by recognizing that if SV is greater than or equal to the 2387 // LHS's Case Value, and that Case Value is exactly one less than the 2388 // Pivot's Value, then we can branch directly to the LHS's Target, 2389 // rather than creating a leaf node for it. 2390 if ((LHSR.second - LHSR.first) == 1 && 2391 LHSR.first->High == CR.GE && 2392 cast<ConstantInt>(C)->getValue() == 2393 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2394 TrueBB = LHSR.first->BB; 2395 } else { 2396 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2397 CurMF->insert(BBI, TrueBB); 2398 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2399 2400 // Put SV in a virtual register to make it available from the new blocks. 2401 ExportFromCurrentBlock(SV); 2402 } 2403 2404 // Similar to the optimization above, if the Value being switched on is 2405 // known to be less than the Constant CR.LT, and the current Case Value 2406 // is CR.LT - 1, then we can branch directly to the target block for 2407 // the current Case Value, rather than emitting a RHS leaf node for it. 2408 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2409 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2410 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2411 FalseBB = RHSR.first->BB; 2412 } else { 2413 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2414 CurMF->insert(BBI, FalseBB); 2415 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2416 2417 // Put SV in a virtual register to make it available from the new blocks. 2418 ExportFromCurrentBlock(SV); 2419 } 2420 2421 // Create a CaseBlock record representing a conditional branch to 2422 // the LHS node if the value being switched on SV is less than C. 2423 // Otherwise, branch to LHS. 2424 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2425 2426 if (CR.CaseBB == SwitchBB) 2427 visitSwitchCase(CB, SwitchBB); 2428 else 2429 SwitchCases.push_back(CB); 2430 2431 return true; 2432} 2433 2434/// handleBitTestsSwitchCase - if current case range has few destination and 2435/// range span less, than machine word bitwidth, encode case range into series 2436/// of masks and emit bit tests with these masks. 2437bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2438 CaseRecVector& WorkList, 2439 const Value* SV, 2440 MachineBasicBlock* Default, 2441 MachineBasicBlock* SwitchBB) { 2442 const TargetLowering *TLI = TM.getTargetLowering(); 2443 EVT PTy = TLI->getPointerTy(); 2444 unsigned IntPtrBits = PTy.getSizeInBits(); 2445 2446 Case& FrontCase = *CR.Range.first; 2447 Case& BackCase = *(CR.Range.second-1); 2448 2449 // Get the MachineFunction which holds the current MBB. This is used when 2450 // inserting any additional MBBs necessary to represent the switch. 2451 MachineFunction *CurMF = FuncInfo.MF; 2452 2453 // If target does not have legal shift left, do not emit bit tests at all. 2454 if (!TLI->isOperationLegal(ISD::SHL, PTy)) 2455 return false; 2456 2457 size_t numCmps = 0; 2458 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2459 I!=E; ++I) { 2460 // Single case counts one, case range - two. 2461 numCmps += (I->Low == I->High ? 1 : 2); 2462 } 2463 2464 // Count unique destinations 2465 SmallSet<MachineBasicBlock*, 4> Dests; 2466 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2467 Dests.insert(I->BB); 2468 if (Dests.size() > 3) 2469 // Don't bother the code below, if there are too much unique destinations 2470 return false; 2471 } 2472 DEBUG(dbgs() << "Total number of unique destinations: " 2473 << Dests.size() << '\n' 2474 << "Total number of comparisons: " << numCmps << '\n'); 2475 2476 // Compute span of values. 2477 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2478 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2479 APInt cmpRange = maxValue - minValue; 2480 2481 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2482 << "Low bound: " << minValue << '\n' 2483 << "High bound: " << maxValue << '\n'); 2484 2485 if (cmpRange.uge(IntPtrBits) || 2486 (!(Dests.size() == 1 && numCmps >= 3) && 2487 !(Dests.size() == 2 && numCmps >= 5) && 2488 !(Dests.size() >= 3 && numCmps >= 6))) 2489 return false; 2490 2491 DEBUG(dbgs() << "Emitting bit tests\n"); 2492 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2493 2494 // Optimize the case where all the case values fit in a 2495 // word without having to subtract minValue. In this case, 2496 // we can optimize away the subtraction. 2497 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2498 cmpRange = maxValue; 2499 } else { 2500 lowBound = minValue; 2501 } 2502 2503 CaseBitsVector CasesBits; 2504 unsigned i, count = 0; 2505 2506 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2507 MachineBasicBlock* Dest = I->BB; 2508 for (i = 0; i < count; ++i) 2509 if (Dest == CasesBits[i].BB) 2510 break; 2511 2512 if (i == count) { 2513 assert((count < 3) && "Too much destinations to test!"); 2514 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/)); 2515 count++; 2516 } 2517 2518 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2519 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2520 2521 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2522 uint64_t hi = (highValue - lowBound).getZExtValue(); 2523 CasesBits[i].ExtraWeight += I->ExtraWeight; 2524 2525 for (uint64_t j = lo; j <= hi; j++) { 2526 CasesBits[i].Mask |= 1ULL << j; 2527 CasesBits[i].Bits++; 2528 } 2529 2530 } 2531 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2532 2533 BitTestInfo BTC; 2534 2535 // Figure out which block is immediately after the current one. 2536 MachineFunction::iterator BBI = CR.CaseBB; 2537 ++BBI; 2538 2539 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2540 2541 DEBUG(dbgs() << "Cases:\n"); 2542 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2543 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2544 << ", Bits: " << CasesBits[i].Bits 2545 << ", BB: " << CasesBits[i].BB << '\n'); 2546 2547 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2548 CurMF->insert(BBI, CaseBB); 2549 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2550 CaseBB, 2551 CasesBits[i].BB, CasesBits[i].ExtraWeight)); 2552 2553 // Put SV in a virtual register to make it available from the new blocks. 2554 ExportFromCurrentBlock(SV); 2555 } 2556 2557 BitTestBlock BTB(lowBound, cmpRange, SV, 2558 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2559 CR.CaseBB, Default, BTC); 2560 2561 if (CR.CaseBB == SwitchBB) 2562 visitBitTestHeader(BTB, SwitchBB); 2563 2564 BitTestCases.push_back(BTB); 2565 2566 return true; 2567} 2568 2569/// Clusterify - Transform simple list of Cases into list of CaseRange's 2570size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2571 const SwitchInst& SI) { 2572 size_t numCmps = 0; 2573 2574 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2575 // Start with "simple" cases 2576 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end(); 2577 i != e; ++i) { 2578 const BasicBlock *SuccBB = i.getCaseSuccessor(); 2579 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2580 2581 uint32_t ExtraWeight = 2582 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0; 2583 2584 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(), 2585 SMBB, ExtraWeight)); 2586 } 2587 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2588 2589 // Merge case into clusters 2590 if (Cases.size() >= 2) 2591 // Must recompute end() each iteration because it may be 2592 // invalidated by erase if we hold on to it 2593 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2594 J != Cases.end(); ) { 2595 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2596 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2597 MachineBasicBlock* nextBB = J->BB; 2598 MachineBasicBlock* currentBB = I->BB; 2599 2600 // If the two neighboring cases go to the same destination, merge them 2601 // into a single case. 2602 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2603 I->High = J->High; 2604 I->ExtraWeight += J->ExtraWeight; 2605 J = Cases.erase(J); 2606 } else { 2607 I = J++; 2608 } 2609 } 2610 2611 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2612 if (I->Low != I->High) 2613 // A range counts double, since it requires two compares. 2614 ++numCmps; 2615 } 2616 2617 return numCmps; 2618} 2619 2620void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2621 MachineBasicBlock *Last) { 2622 // Update JTCases. 2623 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2624 if (JTCases[i].first.HeaderBB == First) 2625 JTCases[i].first.HeaderBB = Last; 2626 2627 // Update BitTestCases. 2628 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2629 if (BitTestCases[i].Parent == First) 2630 BitTestCases[i].Parent = Last; 2631} 2632 2633void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2634 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2635 2636 // Figure out which block is immediately after the current one. 2637 MachineBasicBlock *NextBlock = 0; 2638 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2639 2640 // If there is only the default destination, branch to it if it is not the 2641 // next basic block. Otherwise, just fall through. 2642 if (!SI.getNumCases()) { 2643 // Update machine-CFG edges. 2644 2645 // If this is not a fall-through branch, emit the branch. 2646 SwitchMBB->addSuccessor(Default); 2647 if (Default != NextBlock) 2648 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), 2649 MVT::Other, getControlRoot(), 2650 DAG.getBasicBlock(Default))); 2651 2652 return; 2653 } 2654 2655 // If there are any non-default case statements, create a vector of Cases 2656 // representing each one, and sort the vector so that we can efficiently 2657 // create a binary search tree from them. 2658 CaseVector Cases; 2659 size_t numCmps = Clusterify(Cases, SI); 2660 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2661 << ". Total compares: " << numCmps << '\n'); 2662 (void)numCmps; 2663 2664 // Get the Value to be switched on and default basic blocks, which will be 2665 // inserted into CaseBlock records, representing basic blocks in the binary 2666 // search tree. 2667 const Value *SV = SI.getCondition(); 2668 2669 // Push the initial CaseRec onto the worklist 2670 CaseRecVector WorkList; 2671 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2672 CaseRange(Cases.begin(),Cases.end()))); 2673 2674 while (!WorkList.empty()) { 2675 // Grab a record representing a case range to process off the worklist 2676 CaseRec CR = WorkList.back(); 2677 WorkList.pop_back(); 2678 2679 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2680 continue; 2681 2682 // If the range has few cases (two or less) emit a series of specific 2683 // tests. 2684 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2685 continue; 2686 2687 // If the switch has more than N blocks, and is at least 40% dense, and the 2688 // target supports indirect branches, then emit a jump table rather than 2689 // lowering the switch to a binary tree of conditional branches. 2690 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries(). 2691 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2692 continue; 2693 2694 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2695 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2696 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2697 } 2698} 2699 2700void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2701 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2702 2703 // Update machine-CFG edges with unique successors. 2704 SmallSet<BasicBlock*, 32> Done; 2705 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) { 2706 BasicBlock *BB = I.getSuccessor(i); 2707 bool Inserted = Done.insert(BB); 2708 if (!Inserted) 2709 continue; 2710 2711 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB]; 2712 addSuccessorWithWeight(IndirectBrMBB, Succ); 2713 } 2714 2715 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(), 2716 MVT::Other, getControlRoot(), 2717 getValue(I.getAddress()))); 2718} 2719 2720void SelectionDAGBuilder::visitFSub(const User &I) { 2721 // -0.0 - X --> fneg 2722 Type *Ty = I.getType(); 2723 if (isa<Constant>(I.getOperand(0)) && 2724 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2725 SDValue Op2 = getValue(I.getOperand(1)); 2726 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(), 2727 Op2.getValueType(), Op2)); 2728 return; 2729 } 2730 2731 visitBinary(I, ISD::FSUB); 2732} 2733 2734void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2735 SDValue Op1 = getValue(I.getOperand(0)); 2736 SDValue Op2 = getValue(I.getOperand(1)); 2737 setValue(&I, DAG.getNode(OpCode, getCurSDLoc(), 2738 Op1.getValueType(), Op1, Op2)); 2739} 2740 2741void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2742 SDValue Op1 = getValue(I.getOperand(0)); 2743 SDValue Op2 = getValue(I.getOperand(1)); 2744 2745 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType()); 2746 2747 // Coerce the shift amount to the right type if we can. 2748 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2749 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2750 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2751 SDLoc DL = getCurSDLoc(); 2752 2753 // If the operand is smaller than the shift count type, promote it. 2754 if (ShiftSize > Op2Size) 2755 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2756 2757 // If the operand is larger than the shift count type but the shift 2758 // count type has enough bits to represent any shift value, truncate 2759 // it now. This is a common case and it exposes the truncate to 2760 // optimization early. 2761 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2762 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2763 // Otherwise we'll need to temporarily settle for some other convenient 2764 // type. Type legalization will make adjustments once the shiftee is split. 2765 else 2766 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2767 } 2768 2769 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), 2770 Op1.getValueType(), Op1, Op2)); 2771} 2772 2773void SelectionDAGBuilder::visitSDiv(const User &I) { 2774 SDValue Op1 = getValue(I.getOperand(0)); 2775 SDValue Op2 = getValue(I.getOperand(1)); 2776 2777 // Turn exact SDivs into multiplications. 2778 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2779 // exact bit. 2780 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2781 !isa<ConstantSDNode>(Op1) && 2782 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2783 setValue(&I, TM.getTargetLowering()->BuildExactSDIV(Op1, Op2, 2784 getCurSDLoc(), DAG)); 2785 else 2786 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), 2787 Op1, Op2)); 2788} 2789 2790void SelectionDAGBuilder::visitICmp(const User &I) { 2791 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2792 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2793 predicate = IC->getPredicate(); 2794 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2795 predicate = ICmpInst::Predicate(IC->getPredicate()); 2796 SDValue Op1 = getValue(I.getOperand(0)); 2797 SDValue Op2 = getValue(I.getOperand(1)); 2798 ISD::CondCode Opcode = getICmpCondCode(predicate); 2799 2800 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2801 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); 2802} 2803 2804void SelectionDAGBuilder::visitFCmp(const User &I) { 2805 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2806 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2807 predicate = FC->getPredicate(); 2808 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2809 predicate = FCmpInst::Predicate(FC->getPredicate()); 2810 SDValue Op1 = getValue(I.getOperand(0)); 2811 SDValue Op2 = getValue(I.getOperand(1)); 2812 ISD::CondCode Condition = getFCmpCondCode(predicate); 2813 if (TM.Options.NoNaNsFPMath) 2814 Condition = getFCmpCodeWithoutNaN(Condition); 2815 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2816 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); 2817} 2818 2819void SelectionDAGBuilder::visitSelect(const User &I) { 2820 SmallVector<EVT, 4> ValueVTs; 2821 ComputeValueVTs(*TM.getTargetLowering(), I.getType(), ValueVTs); 2822 unsigned NumValues = ValueVTs.size(); 2823 if (NumValues == 0) return; 2824 2825 SmallVector<SDValue, 4> Values(NumValues); 2826 SDValue Cond = getValue(I.getOperand(0)); 2827 SDValue TrueVal = getValue(I.getOperand(1)); 2828 SDValue FalseVal = getValue(I.getOperand(2)); 2829 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2830 ISD::VSELECT : ISD::SELECT; 2831 2832 for (unsigned i = 0; i != NumValues; ++i) 2833 Values[i] = DAG.getNode(OpCode, getCurSDLoc(), 2834 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2835 Cond, 2836 SDValue(TrueVal.getNode(), 2837 TrueVal.getResNo() + i), 2838 SDValue(FalseVal.getNode(), 2839 FalseVal.getResNo() + i)); 2840 2841 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 2842 DAG.getVTList(&ValueVTs[0], NumValues), 2843 &Values[0], NumValues)); 2844} 2845 2846void SelectionDAGBuilder::visitTrunc(const User &I) { 2847 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2848 SDValue N = getValue(I.getOperand(0)); 2849 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2850 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); 2851} 2852 2853void SelectionDAGBuilder::visitZExt(const User &I) { 2854 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2855 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2856 SDValue N = getValue(I.getOperand(0)); 2857 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2858 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N)); 2859} 2860 2861void SelectionDAGBuilder::visitSExt(const User &I) { 2862 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2863 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2864 SDValue N = getValue(I.getOperand(0)); 2865 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2866 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N)); 2867} 2868 2869void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2870 // FPTrunc is never a no-op cast, no need to check 2871 SDValue N = getValue(I.getOperand(0)); 2872 const TargetLowering *TLI = TM.getTargetLowering(); 2873 EVT DestVT = TLI->getValueType(I.getType()); 2874 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), 2875 DestVT, N, 2876 DAG.getTargetConstant(0, TLI->getPointerTy()))); 2877} 2878 2879void SelectionDAGBuilder::visitFPExt(const User &I) { 2880 // FPExt is never a no-op cast, no need to check 2881 SDValue N = getValue(I.getOperand(0)); 2882 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2883 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N)); 2884} 2885 2886void SelectionDAGBuilder::visitFPToUI(const User &I) { 2887 // FPToUI is never a no-op cast, no need to check 2888 SDValue N = getValue(I.getOperand(0)); 2889 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2890 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N)); 2891} 2892 2893void SelectionDAGBuilder::visitFPToSI(const User &I) { 2894 // FPToSI is never a no-op cast, no need to check 2895 SDValue N = getValue(I.getOperand(0)); 2896 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2897 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N)); 2898} 2899 2900void SelectionDAGBuilder::visitUIToFP(const User &I) { 2901 // UIToFP is never a no-op cast, no need to check 2902 SDValue N = getValue(I.getOperand(0)); 2903 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2904 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N)); 2905} 2906 2907void SelectionDAGBuilder::visitSIToFP(const User &I) { 2908 // SIToFP is never a no-op cast, no need to check 2909 SDValue N = getValue(I.getOperand(0)); 2910 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2911 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N)); 2912} 2913 2914void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2915 // What to do depends on the size of the integer and the size of the pointer. 2916 // We can either truncate, zero extend, or no-op, accordingly. 2917 SDValue N = getValue(I.getOperand(0)); 2918 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2919 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT)); 2920} 2921 2922void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2923 // What to do depends on the size of the integer and the size of the pointer. 2924 // We can either truncate, zero extend, or no-op, accordingly. 2925 SDValue N = getValue(I.getOperand(0)); 2926 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2927 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT)); 2928} 2929 2930void SelectionDAGBuilder::visitBitCast(const User &I) { 2931 SDValue N = getValue(I.getOperand(0)); 2932 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2933 2934 // BitCast assures us that source and destination are the same size so this is 2935 // either a BITCAST or a no-op. 2936 if (DestVT != N.getValueType()) 2937 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(), 2938 DestVT, N)); // convert types. 2939 else 2940 setValue(&I, N); // noop cast. 2941} 2942 2943void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) { 2944 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2945 const Value *SV = I.getOperand(0); 2946 SDValue N = getValue(SV); 2947 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType()); 2948 2949 unsigned SrcAS = SV->getType()->getPointerAddressSpace(); 2950 unsigned DestAS = I.getType()->getPointerAddressSpace(); 2951 2952 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS)) 2953 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS); 2954 2955 setValue(&I, N); 2956} 2957 2958void SelectionDAGBuilder::visitInsertElement(const User &I) { 2959 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2960 SDValue InVec = getValue(I.getOperand(0)); 2961 SDValue InVal = getValue(I.getOperand(1)); 2962 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), 2963 getCurSDLoc(), TLI.getVectorIdxTy()); 2964 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(), 2965 TM.getTargetLowering()->getValueType(I.getType()), 2966 InVec, InVal, InIdx)); 2967} 2968 2969void SelectionDAGBuilder::visitExtractElement(const User &I) { 2970 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 2971 SDValue InVec = getValue(I.getOperand(0)); 2972 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), 2973 getCurSDLoc(), TLI.getVectorIdxTy()); 2974 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(), 2975 TM.getTargetLowering()->getValueType(I.getType()), 2976 InVec, InIdx)); 2977} 2978 2979// Utility for visitShuffleVector - Return true if every element in Mask, 2980// beginning from position Pos and ending in Pos+Size, falls within the 2981// specified sequential range [L, L+Pos). or is undef. 2982static bool isSequentialInRange(const SmallVectorImpl<int> &Mask, 2983 unsigned Pos, unsigned Size, int Low) { 2984 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low) 2985 if (Mask[i] >= 0 && Mask[i] != Low) 2986 return false; 2987 return true; 2988} 2989 2990void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2991 SDValue Src1 = getValue(I.getOperand(0)); 2992 SDValue Src2 = getValue(I.getOperand(1)); 2993 2994 SmallVector<int, 8> Mask; 2995 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask); 2996 unsigned MaskNumElts = Mask.size(); 2997 2998 const TargetLowering *TLI = TM.getTargetLowering(); 2999 EVT VT = TLI->getValueType(I.getType()); 3000 EVT SrcVT = Src1.getValueType(); 3001 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 3002 3003 if (SrcNumElts == MaskNumElts) { 3004 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, 3005 &Mask[0])); 3006 return; 3007 } 3008 3009 // Normalize the shuffle vector since mask and vector length don't match. 3010 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 3011 // Mask is longer than the source vectors and is a multiple of the source 3012 // vectors. We can use concatenate vector to make the mask and vectors 3013 // lengths match. 3014 if (SrcNumElts*2 == MaskNumElts) { 3015 // First check for Src1 in low and Src2 in high 3016 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) && 3017 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) { 3018 // The shuffle is concatenating two vectors together. 3019 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(), 3020 VT, Src1, Src2)); 3021 return; 3022 } 3023 // Then check for Src2 in low and Src1 in high 3024 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) && 3025 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) { 3026 // The shuffle is concatenating two vectors together. 3027 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(), 3028 VT, Src2, Src1)); 3029 return; 3030 } 3031 } 3032 3033 // Pad both vectors with undefs to make them the same length as the mask. 3034 unsigned NumConcat = MaskNumElts / SrcNumElts; 3035 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 3036 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 3037 SDValue UndefVal = DAG.getUNDEF(SrcVT); 3038 3039 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 3040 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 3041 MOps1[0] = Src1; 3042 MOps2[0] = Src2; 3043 3044 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 3045 getCurSDLoc(), VT, 3046 &MOps1[0], NumConcat); 3047 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 3048 getCurSDLoc(), VT, 3049 &MOps2[0], NumConcat); 3050 3051 // Readjust mask for new input vector length. 3052 SmallVector<int, 8> MappedOps; 3053 for (unsigned i = 0; i != MaskNumElts; ++i) { 3054 int Idx = Mask[i]; 3055 if (Idx >= (int)SrcNumElts) 3056 Idx -= SrcNumElts - MaskNumElts; 3057 MappedOps.push_back(Idx); 3058 } 3059 3060 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, 3061 &MappedOps[0])); 3062 return; 3063 } 3064 3065 if (SrcNumElts > MaskNumElts) { 3066 // Analyze the access pattern of the vector to see if we can extract 3067 // two subvectors and do the shuffle. The analysis is done by calculating 3068 // the range of elements the mask access on both vectors. 3069 int MinRange[2] = { static_cast<int>(SrcNumElts), 3070 static_cast<int>(SrcNumElts)}; 3071 int MaxRange[2] = {-1, -1}; 3072 3073 for (unsigned i = 0; i != MaskNumElts; ++i) { 3074 int Idx = Mask[i]; 3075 unsigned Input = 0; 3076 if (Idx < 0) 3077 continue; 3078 3079 if (Idx >= (int)SrcNumElts) { 3080 Input = 1; 3081 Idx -= SrcNumElts; 3082 } 3083 if (Idx > MaxRange[Input]) 3084 MaxRange[Input] = Idx; 3085 if (Idx < MinRange[Input]) 3086 MinRange[Input] = Idx; 3087 } 3088 3089 // Check if the access is smaller than the vector size and can we find 3090 // a reasonable extract index. 3091 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not 3092 // Extract. 3093 int StartIdx[2]; // StartIdx to extract from 3094 for (unsigned Input = 0; Input < 2; ++Input) { 3095 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) { 3096 RangeUse[Input] = 0; // Unused 3097 StartIdx[Input] = 0; 3098 continue; 3099 } 3100 3101 // Find a good start index that is a multiple of the mask length. Then 3102 // see if the rest of the elements are in range. 3103 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 3104 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 3105 StartIdx[Input] + MaskNumElts <= SrcNumElts) 3106 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 3107 } 3108 3109 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 3110 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 3111 return; 3112 } 3113 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) { 3114 // Extract appropriate subvector and generate a vector shuffle 3115 for (unsigned Input = 0; Input < 2; ++Input) { 3116 SDValue &Src = Input == 0 ? Src1 : Src2; 3117 if (RangeUse[Input] == 0) 3118 Src = DAG.getUNDEF(VT); 3119 else 3120 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, 3121 Src, DAG.getConstant(StartIdx[Input], 3122 TLI->getVectorIdxTy())); 3123 } 3124 3125 // Calculate new mask. 3126 SmallVector<int, 8> MappedOps; 3127 for (unsigned i = 0; i != MaskNumElts; ++i) { 3128 int Idx = Mask[i]; 3129 if (Idx >= 0) { 3130 if (Idx < (int)SrcNumElts) 3131 Idx -= StartIdx[0]; 3132 else 3133 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts; 3134 } 3135 MappedOps.push_back(Idx); 3136 } 3137 3138 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2, 3139 &MappedOps[0])); 3140 return; 3141 } 3142 } 3143 3144 // We can't use either concat vectors or extract subvectors so fall back to 3145 // replacing the shuffle with extract and build vector. 3146 // to insert and build vector. 3147 EVT EltVT = VT.getVectorElementType(); 3148 EVT IdxVT = TLI->getVectorIdxTy(); 3149 SmallVector<SDValue,8> Ops; 3150 for (unsigned i = 0; i != MaskNumElts; ++i) { 3151 int Idx = Mask[i]; 3152 SDValue Res; 3153 3154 if (Idx < 0) { 3155 Res = DAG.getUNDEF(EltVT); 3156 } else { 3157 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2; 3158 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts; 3159 3160 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(), 3161 EltVT, Src, DAG.getConstant(Idx, IdxVT)); 3162 } 3163 3164 Ops.push_back(Res); 3165 } 3166 3167 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), 3168 VT, &Ops[0], Ops.size())); 3169} 3170 3171void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 3172 const Value *Op0 = I.getOperand(0); 3173 const Value *Op1 = I.getOperand(1); 3174 Type *AggTy = I.getType(); 3175 Type *ValTy = Op1->getType(); 3176 bool IntoUndef = isa<UndefValue>(Op0); 3177 bool FromUndef = isa<UndefValue>(Op1); 3178 3179 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3180 3181 const TargetLowering *TLI = TM.getTargetLowering(); 3182 SmallVector<EVT, 4> AggValueVTs; 3183 ComputeValueVTs(*TLI, AggTy, AggValueVTs); 3184 SmallVector<EVT, 4> ValValueVTs; 3185 ComputeValueVTs(*TLI, ValTy, ValValueVTs); 3186 3187 unsigned NumAggValues = AggValueVTs.size(); 3188 unsigned NumValValues = ValValueVTs.size(); 3189 SmallVector<SDValue, 4> Values(NumAggValues); 3190 3191 SDValue Agg = getValue(Op0); 3192 unsigned i = 0; 3193 // Copy the beginning value(s) from the original aggregate. 3194 for (; i != LinearIndex; ++i) 3195 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3196 SDValue(Agg.getNode(), Agg.getResNo() + i); 3197 // Copy values from the inserted value(s). 3198 if (NumValValues) { 3199 SDValue Val = getValue(Op1); 3200 for (; i != LinearIndex + NumValValues; ++i) 3201 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3202 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 3203 } 3204 // Copy remaining value(s) from the original aggregate. 3205 for (; i != NumAggValues; ++i) 3206 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 3207 SDValue(Agg.getNode(), Agg.getResNo() + i); 3208 3209 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 3210 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3211 &Values[0], NumAggValues)); 3212} 3213 3214void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3215 const Value *Op0 = I.getOperand(0); 3216 Type *AggTy = Op0->getType(); 3217 Type *ValTy = I.getType(); 3218 bool OutOfUndef = isa<UndefValue>(Op0); 3219 3220 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3221 3222 const TargetLowering *TLI = TM.getTargetLowering(); 3223 SmallVector<EVT, 4> ValValueVTs; 3224 ComputeValueVTs(*TLI, ValTy, ValValueVTs); 3225 3226 unsigned NumValValues = ValValueVTs.size(); 3227 3228 // Ignore a extractvalue that produces an empty object 3229 if (!NumValValues) { 3230 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3231 return; 3232 } 3233 3234 SmallVector<SDValue, 4> Values(NumValValues); 3235 3236 SDValue Agg = getValue(Op0); 3237 // Copy out the selected value(s). 3238 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3239 Values[i - LinearIndex] = 3240 OutOfUndef ? 3241 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3242 SDValue(Agg.getNode(), Agg.getResNo() + i); 3243 3244 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 3245 DAG.getVTList(&ValValueVTs[0], NumValValues), 3246 &Values[0], NumValValues)); 3247} 3248 3249void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3250 Value *Op0 = I.getOperand(0); 3251 // Note that the pointer operand may be a vector of pointers. Take the scalar 3252 // element which holds a pointer. 3253 Type *Ty = Op0->getType()->getScalarType(); 3254 unsigned AS = Ty->getPointerAddressSpace(); 3255 SDValue N = getValue(Op0); 3256 3257 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3258 OI != E; ++OI) { 3259 const Value *Idx = *OI; 3260 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3261 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue(); 3262 if (Field) { 3263 // N = N + Offset 3264 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3265 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, 3266 DAG.getConstant(Offset, N.getValueType())); 3267 } 3268 3269 Ty = StTy->getElementType(Field); 3270 } else { 3271 Ty = cast<SequentialType>(Ty)->getElementType(); 3272 3273 // If this is a constant subscript, handle it quickly. 3274 const TargetLowering *TLI = TM.getTargetLowering(); 3275 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3276 if (CI->isZero()) continue; 3277 uint64_t Offs = 3278 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3279 SDValue OffsVal; 3280 EVT PTy = TLI->getPointerTy(AS); 3281 unsigned PtrBits = PTy.getSizeInBits(); 3282 if (PtrBits < 64) 3283 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy, 3284 DAG.getConstant(Offs, MVT::i64)); 3285 else 3286 OffsVal = DAG.getConstant(Offs, PTy); 3287 3288 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, 3289 OffsVal); 3290 continue; 3291 } 3292 3293 // N = N + Idx * ElementSize; 3294 APInt ElementSize = APInt(TLI->getPointerSizeInBits(AS), 3295 TD->getTypeAllocSize(Ty)); 3296 SDValue IdxN = getValue(Idx); 3297 3298 // If the index is smaller or larger than intptr_t, truncate or extend 3299 // it. 3300 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType()); 3301 3302 // If this is a multiply by a power of two, turn it into a shl 3303 // immediately. This is a very common case. 3304 if (ElementSize != 1) { 3305 if (ElementSize.isPowerOf2()) { 3306 unsigned Amt = ElementSize.logBase2(); 3307 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(), 3308 N.getValueType(), IdxN, 3309 DAG.getConstant(Amt, IdxN.getValueType())); 3310 } else { 3311 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType()); 3312 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(), 3313 N.getValueType(), IdxN, Scale); 3314 } 3315 } 3316 3317 N = DAG.getNode(ISD::ADD, getCurSDLoc(), 3318 N.getValueType(), N, IdxN); 3319 } 3320 } 3321 3322 setValue(&I, N); 3323} 3324 3325void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3326 // If this is a fixed sized alloca in the entry block of the function, 3327 // allocate it statically on the stack. 3328 if (FuncInfo.StaticAllocaMap.count(&I)) 3329 return; // getValue will auto-populate this. 3330 3331 Type *Ty = I.getAllocatedType(); 3332 const TargetLowering *TLI = TM.getTargetLowering(); 3333 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty); 3334 unsigned Align = 3335 std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty), 3336 I.getAlignment()); 3337 3338 SDValue AllocSize = getValue(I.getArraySize()); 3339 3340 EVT IntPtr = TLI->getPointerTy(); 3341 if (AllocSize.getValueType() != IntPtr) 3342 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr); 3343 3344 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr, 3345 AllocSize, 3346 DAG.getConstant(TySize, IntPtr)); 3347 3348 // Handle alignment. If the requested alignment is less than or equal to 3349 // the stack alignment, ignore it. If the size is greater than or equal to 3350 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3351 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3352 if (Align <= StackAlign) 3353 Align = 0; 3354 3355 // Round the size of the allocation up to the stack alignment size 3356 // by add SA-1 to the size. 3357 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(), 3358 AllocSize.getValueType(), AllocSize, 3359 DAG.getIntPtrConstant(StackAlign-1)); 3360 3361 // Mask out the low bits for alignment purposes. 3362 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(), 3363 AllocSize.getValueType(), AllocSize, 3364 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3365 3366 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3367 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3368 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), 3369 VTs, Ops, 3); 3370 setValue(&I, DSA); 3371 DAG.setRoot(DSA.getValue(1)); 3372 3373 // Inform the Frame Information that we have just allocated a variable-sized 3374 // object. 3375 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3376} 3377 3378void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3379 if (I.isAtomic()) 3380 return visitAtomicLoad(I); 3381 3382 const Value *SV = I.getOperand(0); 3383 SDValue Ptr = getValue(SV); 3384 3385 Type *Ty = I.getType(); 3386 3387 bool isVolatile = I.isVolatile(); 3388 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3389 bool isInvariant = I.getMetadata("invariant.load") != 0; 3390 unsigned Alignment = I.getAlignment(); 3391 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3392 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range); 3393 3394 SmallVector<EVT, 4> ValueVTs; 3395 SmallVector<uint64_t, 4> Offsets; 3396 ComputeValueVTs(*TM.getTargetLowering(), Ty, ValueVTs, &Offsets); 3397 unsigned NumValues = ValueVTs.size(); 3398 if (NumValues == 0) 3399 return; 3400 3401 SDValue Root; 3402 bool ConstantMemory = false; 3403 if (I.isVolatile() || NumValues > MaxParallelChains) 3404 // Serialize volatile loads with other side effects. 3405 Root = getRoot(); 3406 else if (AA->pointsToConstantMemory( 3407 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3408 // Do not serialize (non-volatile) loads of constant memory with anything. 3409 Root = DAG.getEntryNode(); 3410 ConstantMemory = true; 3411 } else { 3412 // Do not serialize non-volatile loads against each other. 3413 Root = DAG.getRoot(); 3414 } 3415 3416 SmallVector<SDValue, 4> Values(NumValues); 3417 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3418 NumValues)); 3419 EVT PtrVT = Ptr.getValueType(); 3420 unsigned ChainI = 0; 3421 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3422 // Serializing loads here may result in excessive register pressure, and 3423 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3424 // could recover a bit by hoisting nodes upward in the chain by recognizing 3425 // they are side-effect free or do not alias. The optimizer should really 3426 // avoid this case by converting large object/array copies to llvm.memcpy 3427 // (MaxParallelChains should always remain as failsafe). 3428 if (ChainI == MaxParallelChains) { 3429 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3430 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 3431 MVT::Other, &Chains[0], ChainI); 3432 Root = Chain; 3433 ChainI = 0; 3434 } 3435 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(), 3436 PtrVT, Ptr, 3437 DAG.getConstant(Offsets[i], PtrVT)); 3438 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root, 3439 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3440 isNonTemporal, isInvariant, Alignment, TBAAInfo, 3441 Ranges); 3442 3443 Values[i] = L; 3444 Chains[ChainI] = L.getValue(1); 3445 } 3446 3447 if (!ConstantMemory) { 3448 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 3449 MVT::Other, &Chains[0], ChainI); 3450 if (isVolatile) 3451 DAG.setRoot(Chain); 3452 else 3453 PendingLoads.push_back(Chain); 3454 } 3455 3456 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 3457 DAG.getVTList(&ValueVTs[0], NumValues), 3458 &Values[0], NumValues)); 3459} 3460 3461void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3462 if (I.isAtomic()) 3463 return visitAtomicStore(I); 3464 3465 const Value *SrcV = I.getOperand(0); 3466 const Value *PtrV = I.getOperand(1); 3467 3468 SmallVector<EVT, 4> ValueVTs; 3469 SmallVector<uint64_t, 4> Offsets; 3470 ComputeValueVTs(*TM.getTargetLowering(), SrcV->getType(), ValueVTs, &Offsets); 3471 unsigned NumValues = ValueVTs.size(); 3472 if (NumValues == 0) 3473 return; 3474 3475 // Get the lowered operands. Note that we do this after 3476 // checking if NumResults is zero, because with zero results 3477 // the operands won't have values in the map. 3478 SDValue Src = getValue(SrcV); 3479 SDValue Ptr = getValue(PtrV); 3480 3481 SDValue Root = getRoot(); 3482 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3483 NumValues)); 3484 EVT PtrVT = Ptr.getValueType(); 3485 bool isVolatile = I.isVolatile(); 3486 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3487 unsigned Alignment = I.getAlignment(); 3488 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3489 3490 unsigned ChainI = 0; 3491 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3492 // See visitLoad comments. 3493 if (ChainI == MaxParallelChains) { 3494 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 3495 MVT::Other, &Chains[0], ChainI); 3496 Root = Chain; 3497 ChainI = 0; 3498 } 3499 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr, 3500 DAG.getConstant(Offsets[i], PtrVT)); 3501 SDValue St = DAG.getStore(Root, getCurSDLoc(), 3502 SDValue(Src.getNode(), Src.getResNo() + i), 3503 Add, MachinePointerInfo(PtrV, Offsets[i]), 3504 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3505 Chains[ChainI] = St; 3506 } 3507 3508 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 3509 MVT::Other, &Chains[0], ChainI); 3510 DAG.setRoot(StoreNode); 3511} 3512 3513static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3514 SynchronizationScope Scope, 3515 bool Before, SDLoc dl, 3516 SelectionDAG &DAG, 3517 const TargetLowering &TLI) { 3518 // Fence, if necessary 3519 if (Before) { 3520 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3521 Order = Release; 3522 else if (Order == Acquire || Order == Monotonic) 3523 return Chain; 3524 } else { 3525 if (Order == AcquireRelease) 3526 Order = Acquire; 3527 else if (Order == Release || Order == Monotonic) 3528 return Chain; 3529 } 3530 SDValue Ops[3]; 3531 Ops[0] = Chain; 3532 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3533 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3534 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3535} 3536 3537void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3538 SDLoc dl = getCurSDLoc(); 3539 AtomicOrdering Order = I.getOrdering(); 3540 SynchronizationScope Scope = I.getSynchScope(); 3541 3542 SDValue InChain = getRoot(); 3543 3544 const TargetLowering *TLI = TM.getTargetLowering(); 3545 if (TLI->getInsertFencesForAtomic()) 3546 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3547 DAG, *TLI); 3548 3549 SDValue L = 3550 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3551 getValue(I.getCompareOperand()).getSimpleValueType(), 3552 InChain, 3553 getValue(I.getPointerOperand()), 3554 getValue(I.getCompareOperand()), 3555 getValue(I.getNewValOperand()), 3556 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3557 TLI->getInsertFencesForAtomic() ? Monotonic : Order, 3558 Scope); 3559 3560 SDValue OutChain = L.getValue(1); 3561 3562 if (TLI->getInsertFencesForAtomic()) 3563 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3564 DAG, *TLI); 3565 3566 setValue(&I, L); 3567 DAG.setRoot(OutChain); 3568} 3569 3570void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3571 SDLoc dl = getCurSDLoc(); 3572 ISD::NodeType NT; 3573 switch (I.getOperation()) { 3574 default: llvm_unreachable("Unknown atomicrmw operation"); 3575 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3576 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3577 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3578 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3579 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3580 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3581 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3582 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3583 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3584 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3585 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3586 } 3587 AtomicOrdering Order = I.getOrdering(); 3588 SynchronizationScope Scope = I.getSynchScope(); 3589 3590 SDValue InChain = getRoot(); 3591 3592 const TargetLowering *TLI = TM.getTargetLowering(); 3593 if (TLI->getInsertFencesForAtomic()) 3594 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3595 DAG, *TLI); 3596 3597 SDValue L = 3598 DAG.getAtomic(NT, dl, 3599 getValue(I.getValOperand()).getSimpleValueType(), 3600 InChain, 3601 getValue(I.getPointerOperand()), 3602 getValue(I.getValOperand()), 3603 I.getPointerOperand(), 0 /* Alignment */, 3604 TLI->getInsertFencesForAtomic() ? Monotonic : Order, 3605 Scope); 3606 3607 SDValue OutChain = L.getValue(1); 3608 3609 if (TLI->getInsertFencesForAtomic()) 3610 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3611 DAG, *TLI); 3612 3613 setValue(&I, L); 3614 DAG.setRoot(OutChain); 3615} 3616 3617void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3618 SDLoc dl = getCurSDLoc(); 3619 const TargetLowering *TLI = TM.getTargetLowering(); 3620 SDValue Ops[3]; 3621 Ops[0] = getRoot(); 3622 Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy()); 3623 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy()); 3624 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3625} 3626 3627void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3628 SDLoc dl = getCurSDLoc(); 3629 AtomicOrdering Order = I.getOrdering(); 3630 SynchronizationScope Scope = I.getSynchScope(); 3631 3632 SDValue InChain = getRoot(); 3633 3634 const TargetLowering *TLI = TM.getTargetLowering(); 3635 EVT VT = TLI->getValueType(I.getType()); 3636 3637 if (I.getAlignment() < VT.getSizeInBits() / 8) 3638 report_fatal_error("Cannot generate unaligned atomic load"); 3639 3640 SDValue L = 3641 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3642 getValue(I.getPointerOperand()), 3643 I.getPointerOperand(), I.getAlignment(), 3644 TLI->getInsertFencesForAtomic() ? Monotonic : Order, 3645 Scope); 3646 3647 SDValue OutChain = L.getValue(1); 3648 3649 if (TLI->getInsertFencesForAtomic()) 3650 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3651 DAG, *TLI); 3652 3653 setValue(&I, L); 3654 DAG.setRoot(OutChain); 3655} 3656 3657void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3658 SDLoc dl = getCurSDLoc(); 3659 3660 AtomicOrdering Order = I.getOrdering(); 3661 SynchronizationScope Scope = I.getSynchScope(); 3662 3663 SDValue InChain = getRoot(); 3664 3665 const TargetLowering *TLI = TM.getTargetLowering(); 3666 EVT VT = TLI->getValueType(I.getValueOperand()->getType()); 3667 3668 if (I.getAlignment() < VT.getSizeInBits() / 8) 3669 report_fatal_error("Cannot generate unaligned atomic store"); 3670 3671 if (TLI->getInsertFencesForAtomic()) 3672 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3673 DAG, *TLI); 3674 3675 SDValue OutChain = 3676 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3677 InChain, 3678 getValue(I.getPointerOperand()), 3679 getValue(I.getValueOperand()), 3680 I.getPointerOperand(), I.getAlignment(), 3681 TLI->getInsertFencesForAtomic() ? Monotonic : Order, 3682 Scope); 3683 3684 if (TLI->getInsertFencesForAtomic()) 3685 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3686 DAG, *TLI); 3687 3688 DAG.setRoot(OutChain); 3689} 3690 3691/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3692/// node. 3693void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3694 unsigned Intrinsic) { 3695 bool HasChain = !I.doesNotAccessMemory(); 3696 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3697 3698 // Build the operand list. 3699 SmallVector<SDValue, 8> Ops; 3700 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3701 if (OnlyLoad) { 3702 // We don't need to serialize loads against other loads. 3703 Ops.push_back(DAG.getRoot()); 3704 } else { 3705 Ops.push_back(getRoot()); 3706 } 3707 } 3708 3709 // Info is set by getTgtMemInstrinsic 3710 TargetLowering::IntrinsicInfo Info; 3711 const TargetLowering *TLI = TM.getTargetLowering(); 3712 bool IsTgtIntrinsic = TLI->getTgtMemIntrinsic(Info, I, Intrinsic); 3713 3714 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3715 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3716 Info.opc == ISD::INTRINSIC_W_CHAIN) 3717 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI->getPointerTy())); 3718 3719 // Add all operands of the call to the operand list. 3720 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3721 SDValue Op = getValue(I.getArgOperand(i)); 3722 Ops.push_back(Op); 3723 } 3724 3725 SmallVector<EVT, 4> ValueVTs; 3726 ComputeValueVTs(*TLI, I.getType(), ValueVTs); 3727 3728 if (HasChain) 3729 ValueVTs.push_back(MVT::Other); 3730 3731 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3732 3733 // Create the node. 3734 SDValue Result; 3735 if (IsTgtIntrinsic) { 3736 // This is target intrinsic that touches memory 3737 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), 3738 VTs, &Ops[0], Ops.size(), 3739 Info.memVT, 3740 MachinePointerInfo(Info.ptrVal, Info.offset), 3741 Info.align, Info.vol, 3742 Info.readMem, Info.writeMem); 3743 } else if (!HasChain) { 3744 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), 3745 VTs, &Ops[0], Ops.size()); 3746 } else if (!I.getType()->isVoidTy()) { 3747 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), 3748 VTs, &Ops[0], Ops.size()); 3749 } else { 3750 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), 3751 VTs, &Ops[0], Ops.size()); 3752 } 3753 3754 if (HasChain) { 3755 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3756 if (OnlyLoad) 3757 PendingLoads.push_back(Chain); 3758 else 3759 DAG.setRoot(Chain); 3760 } 3761 3762 if (!I.getType()->isVoidTy()) { 3763 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3764 EVT VT = TLI->getValueType(PTy); 3765 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result); 3766 } 3767 3768 setValue(&I, Result); 3769 } 3770} 3771 3772/// GetSignificand - Get the significand and build it into a floating-point 3773/// number with exponent of 1: 3774/// 3775/// Op = (Op & 0x007fffff) | 0x3f800000; 3776/// 3777/// where Op is the hexadecimal representation of floating point value. 3778static SDValue 3779GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) { 3780 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3781 DAG.getConstant(0x007fffff, MVT::i32)); 3782 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3783 DAG.getConstant(0x3f800000, MVT::i32)); 3784 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3785} 3786 3787/// GetExponent - Get the exponent: 3788/// 3789/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3790/// 3791/// where Op is the hexadecimal representation of floating point value. 3792static SDValue 3793GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3794 SDLoc dl) { 3795 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3796 DAG.getConstant(0x7f800000, MVT::i32)); 3797 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3798 DAG.getConstant(23, TLI.getPointerTy())); 3799 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3800 DAG.getConstant(127, MVT::i32)); 3801 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3802} 3803 3804/// getF32Constant - Get 32-bit floating point constant. 3805static SDValue 3806getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3807 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), 3808 MVT::f32); 3809} 3810 3811/// expandExp - Lower an exp intrinsic. Handles the special sequences for 3812/// limited-precision mode. 3813static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG, 3814 const TargetLowering &TLI) { 3815 if (Op.getValueType() == MVT::f32 && 3816 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3817 3818 // Put the exponent in the right bit position for later addition to the 3819 // final result: 3820 // 3821 // #define LOG2OFe 1.4426950f 3822 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3823 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3824 getF32Constant(DAG, 0x3fb8aa3b)); 3825 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3826 3827 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3828 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3829 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3830 3831 // IntegerPartOfX <<= 23; 3832 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3833 DAG.getConstant(23, TLI.getPointerTy())); 3834 3835 SDValue TwoToFracPartOfX; 3836 if (LimitFloatPrecision <= 6) { 3837 // For floating-point precision of 6: 3838 // 3839 // TwoToFractionalPartOfX = 3840 // 0.997535578f + 3841 // (0.735607626f + 0.252464424f * x) * x; 3842 // 3843 // error 0.0144103317, which is 6 bits 3844 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3845 getF32Constant(DAG, 0x3e814304)); 3846 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3847 getF32Constant(DAG, 0x3f3c50c8)); 3848 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3849 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3850 getF32Constant(DAG, 0x3f7f5e7e)); 3851 } else if (LimitFloatPrecision <= 12) { 3852 // For floating-point precision of 12: 3853 // 3854 // TwoToFractionalPartOfX = 3855 // 0.999892986f + 3856 // (0.696457318f + 3857 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3858 // 3859 // 0.000107046256 error, which is 13 to 14 bits 3860 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3861 getF32Constant(DAG, 0x3da235e3)); 3862 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3863 getF32Constant(DAG, 0x3e65b8f3)); 3864 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3865 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3866 getF32Constant(DAG, 0x3f324b07)); 3867 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3868 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3869 getF32Constant(DAG, 0x3f7ff8fd)); 3870 } else { // LimitFloatPrecision <= 18 3871 // For floating-point precision of 18: 3872 // 3873 // TwoToFractionalPartOfX = 3874 // 0.999999982f + 3875 // (0.693148872f + 3876 // (0.240227044f + 3877 // (0.554906021e-1f + 3878 // (0.961591928e-2f + 3879 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3880 // 3881 // error 2.47208000*10^(-7), which is better than 18 bits 3882 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3883 getF32Constant(DAG, 0x3924b03e)); 3884 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3885 getF32Constant(DAG, 0x3ab24b87)); 3886 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3887 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3888 getF32Constant(DAG, 0x3c1d8c17)); 3889 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3890 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3891 getF32Constant(DAG, 0x3d634a1d)); 3892 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3893 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3894 getF32Constant(DAG, 0x3e75fe14)); 3895 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3896 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3897 getF32Constant(DAG, 0x3f317234)); 3898 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3899 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3900 getF32Constant(DAG, 0x3f800000)); 3901 } 3902 3903 // Add the exponent into the result in integer domain. 3904 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX); 3905 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 3906 DAG.getNode(ISD::ADD, dl, MVT::i32, 3907 t13, IntegerPartOfX)); 3908 } 3909 3910 // No special expansion. 3911 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op); 3912} 3913 3914/// expandLog - Lower a log intrinsic. Handles the special sequences for 3915/// limited-precision mode. 3916static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG, 3917 const TargetLowering &TLI) { 3918 if (Op.getValueType() == MVT::f32 && 3919 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3920 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3921 3922 // Scale the exponent by log(2) [0.69314718f]. 3923 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3924 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3925 getF32Constant(DAG, 0x3f317218)); 3926 3927 // Get the significand and build it into a floating-point number with 3928 // exponent of 1. 3929 SDValue X = GetSignificand(DAG, Op1, dl); 3930 3931 SDValue LogOfMantissa; 3932 if (LimitFloatPrecision <= 6) { 3933 // For floating-point precision of 6: 3934 // 3935 // LogofMantissa = 3936 // -1.1609546f + 3937 // (1.4034025f - 0.23903021f * x) * x; 3938 // 3939 // error 0.0034276066, which is better than 8 bits 3940 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3941 getF32Constant(DAG, 0xbe74c456)); 3942 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3943 getF32Constant(DAG, 0x3fb3a2b1)); 3944 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3945 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3946 getF32Constant(DAG, 0x3f949a29)); 3947 } else if (LimitFloatPrecision <= 12) { 3948 // For floating-point precision of 12: 3949 // 3950 // LogOfMantissa = 3951 // -1.7417939f + 3952 // (2.8212026f + 3953 // (-1.4699568f + 3954 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3955 // 3956 // error 0.000061011436, which is 14 bits 3957 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3958 getF32Constant(DAG, 0xbd67b6d6)); 3959 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3960 getF32Constant(DAG, 0x3ee4f4b8)); 3961 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3962 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3963 getF32Constant(DAG, 0x3fbc278b)); 3964 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3965 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3966 getF32Constant(DAG, 0x40348e95)); 3967 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3968 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3969 getF32Constant(DAG, 0x3fdef31a)); 3970 } else { // LimitFloatPrecision <= 18 3971 // For floating-point precision of 18: 3972 // 3973 // LogOfMantissa = 3974 // -2.1072184f + 3975 // (4.2372794f + 3976 // (-3.7029485f + 3977 // (2.2781945f + 3978 // (-0.87823314f + 3979 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3980 // 3981 // error 0.0000023660568, which is better than 18 bits 3982 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3983 getF32Constant(DAG, 0xbc91e5ac)); 3984 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3985 getF32Constant(DAG, 0x3e4350aa)); 3986 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3987 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3988 getF32Constant(DAG, 0x3f60d3e3)); 3989 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3990 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3991 getF32Constant(DAG, 0x4011cdf0)); 3992 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3993 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3994 getF32Constant(DAG, 0x406cfd1c)); 3995 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3996 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3997 getF32Constant(DAG, 0x408797cb)); 3998 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3999 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 4000 getF32Constant(DAG, 0x4006dcab)); 4001 } 4002 4003 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa); 4004 } 4005 4006 // No special expansion. 4007 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op); 4008} 4009 4010/// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for 4011/// limited-precision mode. 4012static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG, 4013 const TargetLowering &TLI) { 4014 if (Op.getValueType() == MVT::f32 && 4015 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4016 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 4017 4018 // Get the exponent. 4019 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 4020 4021 // Get the significand and build it into a floating-point number with 4022 // exponent of 1. 4023 SDValue X = GetSignificand(DAG, Op1, dl); 4024 4025 // Different possible minimax approximations of significand in 4026 // floating-point for various degrees of accuracy over [1,2]. 4027 SDValue Log2ofMantissa; 4028 if (LimitFloatPrecision <= 6) { 4029 // For floating-point precision of 6: 4030 // 4031 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 4032 // 4033 // error 0.0049451742, which is more than 7 bits 4034 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4035 getF32Constant(DAG, 0xbeb08fe0)); 4036 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4037 getF32Constant(DAG, 0x40019463)); 4038 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4039 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4040 getF32Constant(DAG, 0x3fd6633d)); 4041 } else if (LimitFloatPrecision <= 12) { 4042 // For floating-point precision of 12: 4043 // 4044 // Log2ofMantissa = 4045 // -2.51285454f + 4046 // (4.07009056f + 4047 // (-2.12067489f + 4048 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 4049 // 4050 // error 0.0000876136000, which is better than 13 bits 4051 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4052 getF32Constant(DAG, 0xbda7262e)); 4053 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4054 getF32Constant(DAG, 0x3f25280b)); 4055 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4056 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4057 getF32Constant(DAG, 0x4007b923)); 4058 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4059 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4060 getF32Constant(DAG, 0x40823e2f)); 4061 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4062 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 4063 getF32Constant(DAG, 0x4020d29c)); 4064 } else { // LimitFloatPrecision <= 18 4065 // For floating-point precision of 18: 4066 // 4067 // Log2ofMantissa = 4068 // -3.0400495f + 4069 // (6.1129976f + 4070 // (-5.3420409f + 4071 // (3.2865683f + 4072 // (-1.2669343f + 4073 // (0.27515199f - 4074 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 4075 // 4076 // error 0.0000018516, which is better than 18 bits 4077 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4078 getF32Constant(DAG, 0xbcd2769e)); 4079 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4080 getF32Constant(DAG, 0x3e8ce0b9)); 4081 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4082 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4083 getF32Constant(DAG, 0x3fa22ae7)); 4084 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4085 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4086 getF32Constant(DAG, 0x40525723)); 4087 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4088 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 4089 getF32Constant(DAG, 0x40aaf200)); 4090 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4091 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4092 getF32Constant(DAG, 0x40c39dad)); 4093 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4094 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 4095 getF32Constant(DAG, 0x4042902c)); 4096 } 4097 4098 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa); 4099 } 4100 4101 // No special expansion. 4102 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op); 4103} 4104 4105/// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for 4106/// limited-precision mode. 4107static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG, 4108 const TargetLowering &TLI) { 4109 if (Op.getValueType() == MVT::f32 && 4110 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4111 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 4112 4113 // Scale the exponent by log10(2) [0.30102999f]. 4114 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 4115 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 4116 getF32Constant(DAG, 0x3e9a209a)); 4117 4118 // Get the significand and build it into a floating-point number with 4119 // exponent of 1. 4120 SDValue X = GetSignificand(DAG, Op1, dl); 4121 4122 SDValue Log10ofMantissa; 4123 if (LimitFloatPrecision <= 6) { 4124 // For floating-point precision of 6: 4125 // 4126 // Log10ofMantissa = 4127 // -0.50419619f + 4128 // (0.60948995f - 0.10380950f * x) * x; 4129 // 4130 // error 0.0014886165, which is 6 bits 4131 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4132 getF32Constant(DAG, 0xbdd49a13)); 4133 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 4134 getF32Constant(DAG, 0x3f1c0789)); 4135 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4136 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4137 getF32Constant(DAG, 0x3f011300)); 4138 } else if (LimitFloatPrecision <= 12) { 4139 // For floating-point precision of 12: 4140 // 4141 // Log10ofMantissa = 4142 // -0.64831180f + 4143 // (0.91751397f + 4144 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 4145 // 4146 // error 0.00019228036, which is better than 12 bits 4147 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4148 getF32Constant(DAG, 0x3d431f31)); 4149 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4150 getF32Constant(DAG, 0x3ea21fb2)); 4151 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4152 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4153 getF32Constant(DAG, 0x3f6ae232)); 4154 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4155 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4156 getF32Constant(DAG, 0x3f25f7c3)); 4157 } else { // LimitFloatPrecision <= 18 4158 // For floating-point precision of 18: 4159 // 4160 // Log10ofMantissa = 4161 // -0.84299375f + 4162 // (1.5327582f + 4163 // (-1.0688956f + 4164 // (0.49102474f + 4165 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4166 // 4167 // error 0.0000037995730, which is better than 18 bits 4168 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4169 getF32Constant(DAG, 0x3c5d51ce)); 4170 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4171 getF32Constant(DAG, 0x3e00685a)); 4172 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4173 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4174 getF32Constant(DAG, 0x3efb6798)); 4175 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4176 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4177 getF32Constant(DAG, 0x3f88d192)); 4178 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4179 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4180 getF32Constant(DAG, 0x3fc4316c)); 4181 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4182 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4183 getF32Constant(DAG, 0x3f57ce70)); 4184 } 4185 4186 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa); 4187 } 4188 4189 // No special expansion. 4190 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op); 4191} 4192 4193/// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4194/// limited-precision mode. 4195static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG, 4196 const TargetLowering &TLI) { 4197 if (Op.getValueType() == MVT::f32 && 4198 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4199 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4200 4201 // FractionalPartOfX = x - (float)IntegerPartOfX; 4202 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4203 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4204 4205 // IntegerPartOfX <<= 23; 4206 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4207 DAG.getConstant(23, TLI.getPointerTy())); 4208 4209 SDValue TwoToFractionalPartOfX; 4210 if (LimitFloatPrecision <= 6) { 4211 // For floating-point precision of 6: 4212 // 4213 // TwoToFractionalPartOfX = 4214 // 0.997535578f + 4215 // (0.735607626f + 0.252464424f * x) * x; 4216 // 4217 // error 0.0144103317, which is 6 bits 4218 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4219 getF32Constant(DAG, 0x3e814304)); 4220 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4221 getF32Constant(DAG, 0x3f3c50c8)); 4222 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4223 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4224 getF32Constant(DAG, 0x3f7f5e7e)); 4225 } else if (LimitFloatPrecision <= 12) { 4226 // For floating-point precision of 12: 4227 // 4228 // TwoToFractionalPartOfX = 4229 // 0.999892986f + 4230 // (0.696457318f + 4231 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4232 // 4233 // error 0.000107046256, which is 13 to 14 bits 4234 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4235 getF32Constant(DAG, 0x3da235e3)); 4236 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4237 getF32Constant(DAG, 0x3e65b8f3)); 4238 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4239 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4240 getF32Constant(DAG, 0x3f324b07)); 4241 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4242 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4243 getF32Constant(DAG, 0x3f7ff8fd)); 4244 } else { // LimitFloatPrecision <= 18 4245 // For floating-point precision of 18: 4246 // 4247 // TwoToFractionalPartOfX = 4248 // 0.999999982f + 4249 // (0.693148872f + 4250 // (0.240227044f + 4251 // (0.554906021e-1f + 4252 // (0.961591928e-2f + 4253 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4254 // error 2.47208000*10^(-7), which is better than 18 bits 4255 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4256 getF32Constant(DAG, 0x3924b03e)); 4257 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4258 getF32Constant(DAG, 0x3ab24b87)); 4259 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4260 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4261 getF32Constant(DAG, 0x3c1d8c17)); 4262 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4263 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4264 getF32Constant(DAG, 0x3d634a1d)); 4265 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4266 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4267 getF32Constant(DAG, 0x3e75fe14)); 4268 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4269 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4270 getF32Constant(DAG, 0x3f317234)); 4271 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4272 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4273 getF32Constant(DAG, 0x3f800000)); 4274 } 4275 4276 // Add the exponent into the result in integer domain. 4277 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, 4278 TwoToFractionalPartOfX); 4279 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 4280 DAG.getNode(ISD::ADD, dl, MVT::i32, 4281 t13, IntegerPartOfX)); 4282 } 4283 4284 // No special expansion. 4285 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op); 4286} 4287 4288/// visitPow - Lower a pow intrinsic. Handles the special sequences for 4289/// limited-precision mode with x == 10.0f. 4290static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS, 4291 SelectionDAG &DAG, const TargetLowering &TLI) { 4292 bool IsExp10 = false; 4293 if (LHS.getValueType() == MVT::f32 && LHS.getValueType() == MVT::f32 && 4294 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4295 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) { 4296 APFloat Ten(10.0f); 4297 IsExp10 = LHSC->isExactlyValue(Ten); 4298 } 4299 } 4300 4301 if (IsExp10) { 4302 // Put the exponent in the right bit position for later addition to the 4303 // final result: 4304 // 4305 // #define LOG2OF10 3.3219281f 4306 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4307 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS, 4308 getF32Constant(DAG, 0x40549a78)); 4309 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4310 4311 // FractionalPartOfX = x - (float)IntegerPartOfX; 4312 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4313 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4314 4315 // IntegerPartOfX <<= 23; 4316 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4317 DAG.getConstant(23, TLI.getPointerTy())); 4318 4319 SDValue TwoToFractionalPartOfX; 4320 if (LimitFloatPrecision <= 6) { 4321 // For floating-point precision of 6: 4322 // 4323 // twoToFractionalPartOfX = 4324 // 0.997535578f + 4325 // (0.735607626f + 0.252464424f * x) * x; 4326 // 4327 // error 0.0144103317, which is 6 bits 4328 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4329 getF32Constant(DAG, 0x3e814304)); 4330 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4331 getF32Constant(DAG, 0x3f3c50c8)); 4332 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4333 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4334 getF32Constant(DAG, 0x3f7f5e7e)); 4335 } else if (LimitFloatPrecision <= 12) { 4336 // For floating-point precision of 12: 4337 // 4338 // TwoToFractionalPartOfX = 4339 // 0.999892986f + 4340 // (0.696457318f + 4341 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4342 // 4343 // error 0.000107046256, which is 13 to 14 bits 4344 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4345 getF32Constant(DAG, 0x3da235e3)); 4346 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4347 getF32Constant(DAG, 0x3e65b8f3)); 4348 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4349 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4350 getF32Constant(DAG, 0x3f324b07)); 4351 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4352 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4353 getF32Constant(DAG, 0x3f7ff8fd)); 4354 } else { // LimitFloatPrecision <= 18 4355 // For floating-point precision of 18: 4356 // 4357 // TwoToFractionalPartOfX = 4358 // 0.999999982f + 4359 // (0.693148872f + 4360 // (0.240227044f + 4361 // (0.554906021e-1f + 4362 // (0.961591928e-2f + 4363 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4364 // error 2.47208000*10^(-7), which is better than 18 bits 4365 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4366 getF32Constant(DAG, 0x3924b03e)); 4367 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4368 getF32Constant(DAG, 0x3ab24b87)); 4369 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4370 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4371 getF32Constant(DAG, 0x3c1d8c17)); 4372 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4373 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4374 getF32Constant(DAG, 0x3d634a1d)); 4375 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4376 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4377 getF32Constant(DAG, 0x3e75fe14)); 4378 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4379 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4380 getF32Constant(DAG, 0x3f317234)); 4381 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4382 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4383 getF32Constant(DAG, 0x3f800000)); 4384 } 4385 4386 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX); 4387 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 4388 DAG.getNode(ISD::ADD, dl, MVT::i32, 4389 t13, IntegerPartOfX)); 4390 } 4391 4392 // No special expansion. 4393 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS); 4394} 4395 4396 4397/// ExpandPowI - Expand a llvm.powi intrinsic. 4398static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS, 4399 SelectionDAG &DAG) { 4400 // If RHS is a constant, we can expand this out to a multiplication tree, 4401 // otherwise we end up lowering to a call to __powidf2 (for example). When 4402 // optimizing for size, we only want to do this if the expansion would produce 4403 // a small number of multiplies, otherwise we do the full expansion. 4404 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4405 // Get the exponent as a positive value. 4406 unsigned Val = RHSC->getSExtValue(); 4407 if ((int)Val < 0) Val = -Val; 4408 4409 // powi(x, 0) -> 1.0 4410 if (Val == 0) 4411 return DAG.getConstantFP(1.0, LHS.getValueType()); 4412 4413 const Function *F = DAG.getMachineFunction().getFunction(); 4414 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 4415 Attribute::OptimizeForSize) || 4416 // If optimizing for size, don't insert too many multiplies. This 4417 // inserts up to 5 multiplies. 4418 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4419 // We use the simple binary decomposition method to generate the multiply 4420 // sequence. There are more optimal ways to do this (for example, 4421 // powi(x,15) generates one more multiply than it should), but this has 4422 // the benefit of being both really simple and much better than a libcall. 4423 SDValue Res; // Logically starts equal to 1.0 4424 SDValue CurSquare = LHS; 4425 while (Val) { 4426 if (Val & 1) { 4427 if (Res.getNode()) 4428 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4429 else 4430 Res = CurSquare; // 1.0*CurSquare. 4431 } 4432 4433 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4434 CurSquare, CurSquare); 4435 Val >>= 1; 4436 } 4437 4438 // If the original was negative, invert the result, producing 1/(x*x*x). 4439 if (RHSC->getSExtValue() < 0) 4440 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4441 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4442 return Res; 4443 } 4444 } 4445 4446 // Otherwise, expand to a libcall. 4447 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4448} 4449 4450// getTruncatedArgReg - Find underlying register used for an truncated 4451// argument. 4452static unsigned getTruncatedArgReg(const SDValue &N) { 4453 if (N.getOpcode() != ISD::TRUNCATE) 4454 return 0; 4455 4456 const SDValue &Ext = N.getOperand(0); 4457 if (Ext.getOpcode() == ISD::AssertZext || 4458 Ext.getOpcode() == ISD::AssertSext) { 4459 const SDValue &CFR = Ext.getOperand(0); 4460 if (CFR.getOpcode() == ISD::CopyFromReg) 4461 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4462 if (CFR.getOpcode() == ISD::TRUNCATE) 4463 return getTruncatedArgReg(CFR); 4464 } 4465 return 0; 4466} 4467 4468/// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4469/// argument, create the corresponding DBG_VALUE machine instruction for it now. 4470/// At the end of instruction selection, they will be inserted to the entry BB. 4471bool 4472SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4473 int64_t Offset, 4474 const SDValue &N) { 4475 const Argument *Arg = dyn_cast<Argument>(V); 4476 if (!Arg) 4477 return false; 4478 4479 MachineFunction &MF = DAG.getMachineFunction(); 4480 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4481 4482 // Ignore inlined function arguments here. 4483 DIVariable DV(Variable); 4484 if (DV.isInlinedFnArgument(MF.getFunction())) 4485 return false; 4486 4487 Optional<MachineOperand> Op; 4488 // Some arguments' frame index is recorded during argument lowering. 4489 if (int FI = FuncInfo.getArgumentFrameIndex(Arg)) 4490 Op = MachineOperand::CreateFI(FI); 4491 4492 if (!Op && N.getNode()) { 4493 unsigned Reg; 4494 if (N.getOpcode() == ISD::CopyFromReg) 4495 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4496 else 4497 Reg = getTruncatedArgReg(N); 4498 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4499 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4500 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4501 if (PR) 4502 Reg = PR; 4503 } 4504 if (Reg) 4505 Op = MachineOperand::CreateReg(Reg, false); 4506 } 4507 4508 if (!Op) { 4509 // Check if ValueMap has reg number. 4510 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4511 if (VMI != FuncInfo.ValueMap.end()) 4512 Op = MachineOperand::CreateReg(VMI->second, false); 4513 } 4514 4515 if (!Op && N.getNode()) 4516 // Check if frame index is available. 4517 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4518 if (FrameIndexSDNode *FINode = 4519 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 4520 Op = MachineOperand::CreateFI(FINode->getIndex()); 4521 4522 if (!Op) 4523 return false; 4524 4525 // FIXME: This does not handle register-indirect values at offset 0. 4526 bool IsIndirect = Offset != 0; 4527 if (Op->isReg()) 4528 FuncInfo.ArgDbgValues.push_back(BuildMI(MF, getCurDebugLoc(), 4529 TII->get(TargetOpcode::DBG_VALUE), 4530 IsIndirect, 4531 Op->getReg(), Offset, Variable)); 4532 else 4533 FuncInfo.ArgDbgValues.push_back( 4534 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE)) 4535 .addOperand(*Op).addImm(Offset).addMetadata(Variable)); 4536 4537 return true; 4538} 4539 4540// VisualStudio defines setjmp as _setjmp 4541#if defined(_MSC_VER) && defined(setjmp) && \ 4542 !defined(setjmp_undefined_for_msvc) 4543# pragma push_macro("setjmp") 4544# undef setjmp 4545# define setjmp_undefined_for_msvc 4546#endif 4547 4548/// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4549/// we want to emit this as a call to a named external function, return the name 4550/// otherwise lower it and return null. 4551const char * 4552SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4553 const TargetLowering *TLI = TM.getTargetLowering(); 4554 SDLoc sdl = getCurSDLoc(); 4555 DebugLoc dl = getCurDebugLoc(); 4556 SDValue Res; 4557 4558 switch (Intrinsic) { 4559 default: 4560 // By default, turn this into a target intrinsic node. 4561 visitTargetIntrinsic(I, Intrinsic); 4562 return 0; 4563 case Intrinsic::vastart: visitVAStart(I); return 0; 4564 case Intrinsic::vaend: visitVAEnd(I); return 0; 4565 case Intrinsic::vacopy: visitVACopy(I); return 0; 4566 case Intrinsic::returnaddress: 4567 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI->getPointerTy(), 4568 getValue(I.getArgOperand(0)))); 4569 return 0; 4570 case Intrinsic::frameaddress: 4571 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI->getPointerTy(), 4572 getValue(I.getArgOperand(0)))); 4573 return 0; 4574 case Intrinsic::setjmp: 4575 return &"_setjmp"[!TLI->usesUnderscoreSetJmp()]; 4576 case Intrinsic::longjmp: 4577 return &"_longjmp"[!TLI->usesUnderscoreLongJmp()]; 4578 case Intrinsic::memcpy: { 4579 // Assert for address < 256 since we support only user defined address 4580 // spaces. 4581 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4582 < 256 && 4583 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4584 < 256 && 4585 "Unknown address space"); 4586 SDValue Op1 = getValue(I.getArgOperand(0)); 4587 SDValue Op2 = getValue(I.getArgOperand(1)); 4588 SDValue Op3 = getValue(I.getArgOperand(2)); 4589 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4590 if (!Align) 4591 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment. 4592 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4593 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false, 4594 MachinePointerInfo(I.getArgOperand(0)), 4595 MachinePointerInfo(I.getArgOperand(1)))); 4596 return 0; 4597 } 4598 case Intrinsic::memset: { 4599 // Assert for address < 256 since we support only user defined address 4600 // spaces. 4601 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4602 < 256 && 4603 "Unknown address space"); 4604 SDValue Op1 = getValue(I.getArgOperand(0)); 4605 SDValue Op2 = getValue(I.getArgOperand(1)); 4606 SDValue Op3 = getValue(I.getArgOperand(2)); 4607 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4608 if (!Align) 4609 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment. 4610 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4611 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, 4612 MachinePointerInfo(I.getArgOperand(0)))); 4613 return 0; 4614 } 4615 case Intrinsic::memmove: { 4616 // Assert for address < 256 since we support only user defined address 4617 // spaces. 4618 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4619 < 256 && 4620 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4621 < 256 && 4622 "Unknown address space"); 4623 SDValue Op1 = getValue(I.getArgOperand(0)); 4624 SDValue Op2 = getValue(I.getArgOperand(1)); 4625 SDValue Op3 = getValue(I.getArgOperand(2)); 4626 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4627 if (!Align) 4628 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment. 4629 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4630 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, 4631 MachinePointerInfo(I.getArgOperand(0)), 4632 MachinePointerInfo(I.getArgOperand(1)))); 4633 return 0; 4634 } 4635 case Intrinsic::dbg_declare: { 4636 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4637 MDNode *Variable = DI.getVariable(); 4638 const Value *Address = DI.getAddress(); 4639 DIVariable DIVar(Variable); 4640 assert((!DIVar || DIVar.isVariable()) && 4641 "Variable in DbgDeclareInst should be either null or a DIVariable."); 4642 if (!Address || !DIVar) { 4643 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4644 return 0; 4645 } 4646 4647 // Check if address has undef value. 4648 if (isa<UndefValue>(Address) || 4649 (Address->use_empty() && !isa<Argument>(Address))) { 4650 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4651 return 0; 4652 } 4653 4654 SDValue &N = NodeMap[Address]; 4655 if (!N.getNode() && isa<Argument>(Address)) 4656 // Check unused arguments map. 4657 N = UnusedArgNodeMap[Address]; 4658 SDDbgValue *SDV; 4659 if (N.getNode()) { 4660 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4661 Address = BCI->getOperand(0); 4662 // Parameters are handled specially. 4663 bool isParameter = 4664 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable || 4665 isa<Argument>(Address)); 4666 4667 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4668 4669 if (isParameter && !AI) { 4670 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4671 if (FINode) 4672 // Byval parameter. We have a frame index at this point. 4673 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4674 0, dl, SDNodeOrder); 4675 else { 4676 // Address is an argument, so try to emit its dbg value using 4677 // virtual register info from the FuncInfo.ValueMap. 4678 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4679 return 0; 4680 } 4681 } else if (AI) 4682 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4683 0, dl, SDNodeOrder); 4684 else { 4685 // Can't do anything with other non-AI cases yet. 4686 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4687 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t"); 4688 DEBUG(Address->dump()); 4689 return 0; 4690 } 4691 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4692 } else { 4693 // If Address is an argument then try to emit its dbg value using 4694 // virtual register info from the FuncInfo.ValueMap. 4695 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4696 // If variable is pinned by a alloca in dominating bb then 4697 // use StaticAllocaMap. 4698 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4699 if (AI->getParent() != DI.getParent()) { 4700 DenseMap<const AllocaInst*, int>::iterator SI = 4701 FuncInfo.StaticAllocaMap.find(AI); 4702 if (SI != FuncInfo.StaticAllocaMap.end()) { 4703 SDV = DAG.getDbgValue(Variable, SI->second, 4704 0, dl, SDNodeOrder); 4705 DAG.AddDbgValue(SDV, 0, false); 4706 return 0; 4707 } 4708 } 4709 } 4710 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4711 } 4712 } 4713 return 0; 4714 } 4715 case Intrinsic::dbg_value: { 4716 const DbgValueInst &DI = cast<DbgValueInst>(I); 4717 DIVariable DIVar(DI.getVariable()); 4718 assert((!DIVar || DIVar.isVariable()) && 4719 "Variable in DbgValueInst should be either null or a DIVariable."); 4720 if (!DIVar) 4721 return 0; 4722 4723 MDNode *Variable = DI.getVariable(); 4724 uint64_t Offset = DI.getOffset(); 4725 const Value *V = DI.getValue(); 4726 if (!V) 4727 return 0; 4728 4729 SDDbgValue *SDV; 4730 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4731 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4732 DAG.AddDbgValue(SDV, 0, false); 4733 } else { 4734 // Do not use getValue() in here; we don't want to generate code at 4735 // this point if it hasn't been done yet. 4736 SDValue N = NodeMap[V]; 4737 if (!N.getNode() && isa<Argument>(V)) 4738 // Check unused arguments map. 4739 N = UnusedArgNodeMap[V]; 4740 if (N.getNode()) { 4741 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4742 SDV = DAG.getDbgValue(Variable, N.getNode(), 4743 N.getResNo(), Offset, dl, SDNodeOrder); 4744 DAG.AddDbgValue(SDV, N.getNode(), false); 4745 } 4746 } else if (!V->use_empty() ) { 4747 // Do not call getValue(V) yet, as we don't want to generate code. 4748 // Remember it for later. 4749 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4750 DanglingDebugInfoMap[V] = DDI; 4751 } else { 4752 // We may expand this to cover more cases. One case where we have no 4753 // data available is an unreferenced parameter. 4754 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); 4755 } 4756 } 4757 4758 // Build a debug info table entry. 4759 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4760 V = BCI->getOperand(0); 4761 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4762 // Don't handle byval struct arguments or VLAs, for example. 4763 if (!AI) { 4764 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n"); 4765 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n"); 4766 return 0; 4767 } 4768 DenseMap<const AllocaInst*, int>::iterator SI = 4769 FuncInfo.StaticAllocaMap.find(AI); 4770 if (SI == FuncInfo.StaticAllocaMap.end()) 4771 return 0; // VLAs. 4772 int FI = SI->second; 4773 4774 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4775 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4776 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4777 return 0; 4778 } 4779 4780 case Intrinsic::eh_typeid_for: { 4781 // Find the type id for the given typeinfo. 4782 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4783 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4784 Res = DAG.getConstant(TypeID, MVT::i32); 4785 setValue(&I, Res); 4786 return 0; 4787 } 4788 4789 case Intrinsic::eh_return_i32: 4790 case Intrinsic::eh_return_i64: 4791 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4792 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl, 4793 MVT::Other, 4794 getControlRoot(), 4795 getValue(I.getArgOperand(0)), 4796 getValue(I.getArgOperand(1)))); 4797 return 0; 4798 case Intrinsic::eh_unwind_init: 4799 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4800 return 0; 4801 case Intrinsic::eh_dwarf_cfa: { 4802 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl, 4803 TLI->getPointerTy()); 4804 SDValue Offset = DAG.getNode(ISD::ADD, sdl, 4805 CfaArg.getValueType(), 4806 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl, 4807 CfaArg.getValueType()), 4808 CfaArg); 4809 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, 4810 TLI->getPointerTy(), 4811 DAG.getConstant(0, TLI->getPointerTy())); 4812 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(), 4813 FA, Offset)); 4814 return 0; 4815 } 4816 case Intrinsic::eh_sjlj_callsite: { 4817 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4818 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4819 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4820 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4821 4822 MMI.setCurrentCallSite(CI->getZExtValue()); 4823 return 0; 4824 } 4825 case Intrinsic::eh_sjlj_functioncontext: { 4826 // Get and store the index of the function context. 4827 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4828 AllocaInst *FnCtx = 4829 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4830 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4831 MFI->setFunctionContextIndex(FI); 4832 return 0; 4833 } 4834 case Intrinsic::eh_sjlj_setjmp: { 4835 SDValue Ops[2]; 4836 Ops[0] = getRoot(); 4837 Ops[1] = getValue(I.getArgOperand(0)); 4838 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl, 4839 DAG.getVTList(MVT::i32, MVT::Other), 4840 Ops, 2); 4841 setValue(&I, Op.getValue(0)); 4842 DAG.setRoot(Op.getValue(1)); 4843 return 0; 4844 } 4845 case Intrinsic::eh_sjlj_longjmp: { 4846 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other, 4847 getRoot(), getValue(I.getArgOperand(0)))); 4848 return 0; 4849 } 4850 4851 case Intrinsic::x86_mmx_pslli_w: 4852 case Intrinsic::x86_mmx_pslli_d: 4853 case Intrinsic::x86_mmx_pslli_q: 4854 case Intrinsic::x86_mmx_psrli_w: 4855 case Intrinsic::x86_mmx_psrli_d: 4856 case Intrinsic::x86_mmx_psrli_q: 4857 case Intrinsic::x86_mmx_psrai_w: 4858 case Intrinsic::x86_mmx_psrai_d: { 4859 SDValue ShAmt = getValue(I.getArgOperand(1)); 4860 if (isa<ConstantSDNode>(ShAmt)) { 4861 visitTargetIntrinsic(I, Intrinsic); 4862 return 0; 4863 } 4864 unsigned NewIntrinsic = 0; 4865 EVT ShAmtVT = MVT::v2i32; 4866 switch (Intrinsic) { 4867 case Intrinsic::x86_mmx_pslli_w: 4868 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4869 break; 4870 case Intrinsic::x86_mmx_pslli_d: 4871 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4872 break; 4873 case Intrinsic::x86_mmx_pslli_q: 4874 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4875 break; 4876 case Intrinsic::x86_mmx_psrli_w: 4877 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4878 break; 4879 case Intrinsic::x86_mmx_psrli_d: 4880 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4881 break; 4882 case Intrinsic::x86_mmx_psrli_q: 4883 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4884 break; 4885 case Intrinsic::x86_mmx_psrai_w: 4886 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4887 break; 4888 case Intrinsic::x86_mmx_psrai_d: 4889 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4890 break; 4891 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4892 } 4893 4894 // The vector shift intrinsics with scalars uses 32b shift amounts but 4895 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4896 // to be zero. 4897 // We must do this early because v2i32 is not a legal type. 4898 SDValue ShOps[2]; 4899 ShOps[0] = ShAmt; 4900 ShOps[1] = DAG.getConstant(0, MVT::i32); 4901 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, &ShOps[0], 2); 4902 EVT DestVT = TLI->getValueType(I.getType()); 4903 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt); 4904 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT, 4905 DAG.getConstant(NewIntrinsic, MVT::i32), 4906 getValue(I.getArgOperand(0)), ShAmt); 4907 setValue(&I, Res); 4908 return 0; 4909 } 4910 case Intrinsic::x86_avx_vinsertf128_pd_256: 4911 case Intrinsic::x86_avx_vinsertf128_ps_256: 4912 case Intrinsic::x86_avx_vinsertf128_si_256: 4913 case Intrinsic::x86_avx2_vinserti128: { 4914 EVT DestVT = TLI->getValueType(I.getType()); 4915 EVT ElVT = TLI->getValueType(I.getArgOperand(1)->getType()); 4916 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) * 4917 ElVT.getVectorNumElements(); 4918 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT, 4919 getValue(I.getArgOperand(0)), 4920 getValue(I.getArgOperand(1)), 4921 DAG.getConstant(Idx, TLI->getVectorIdxTy())); 4922 setValue(&I, Res); 4923 return 0; 4924 } 4925 case Intrinsic::x86_avx_vextractf128_pd_256: 4926 case Intrinsic::x86_avx_vextractf128_ps_256: 4927 case Intrinsic::x86_avx_vextractf128_si_256: 4928 case Intrinsic::x86_avx2_vextracti128: { 4929 EVT DestVT = TLI->getValueType(I.getType()); 4930 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) * 4931 DestVT.getVectorNumElements(); 4932 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT, 4933 getValue(I.getArgOperand(0)), 4934 DAG.getConstant(Idx, TLI->getVectorIdxTy())); 4935 setValue(&I, Res); 4936 return 0; 4937 } 4938 case Intrinsic::convertff: 4939 case Intrinsic::convertfsi: 4940 case Intrinsic::convertfui: 4941 case Intrinsic::convertsif: 4942 case Intrinsic::convertuif: 4943 case Intrinsic::convertss: 4944 case Intrinsic::convertsu: 4945 case Intrinsic::convertus: 4946 case Intrinsic::convertuu: { 4947 ISD::CvtCode Code = ISD::CVT_INVALID; 4948 switch (Intrinsic) { 4949 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4950 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4951 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4952 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4953 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4954 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4955 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4956 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4957 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4958 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4959 } 4960 EVT DestVT = TLI->getValueType(I.getType()); 4961 const Value *Op1 = I.getArgOperand(0); 4962 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1), 4963 DAG.getValueType(DestVT), 4964 DAG.getValueType(getValue(Op1).getValueType()), 4965 getValue(I.getArgOperand(1)), 4966 getValue(I.getArgOperand(2)), 4967 Code); 4968 setValue(&I, Res); 4969 return 0; 4970 } 4971 case Intrinsic::powi: 4972 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)), 4973 getValue(I.getArgOperand(1)), DAG)); 4974 return 0; 4975 case Intrinsic::log: 4976 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, *TLI)); 4977 return 0; 4978 case Intrinsic::log2: 4979 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI)); 4980 return 0; 4981 case Intrinsic::log10: 4982 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, *TLI)); 4983 return 0; 4984 case Intrinsic::exp: 4985 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, *TLI)); 4986 return 0; 4987 case Intrinsic::exp2: 4988 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI)); 4989 return 0; 4990 case Intrinsic::pow: 4991 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)), 4992 getValue(I.getArgOperand(1)), DAG, *TLI)); 4993 return 0; 4994 case Intrinsic::sqrt: 4995 case Intrinsic::fabs: 4996 case Intrinsic::sin: 4997 case Intrinsic::cos: 4998 case Intrinsic::floor: 4999 case Intrinsic::ceil: 5000 case Intrinsic::trunc: 5001 case Intrinsic::rint: 5002 case Intrinsic::nearbyint: 5003 case Intrinsic::round: { 5004 unsigned Opcode; 5005 switch (Intrinsic) { 5006 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 5007 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; 5008 case Intrinsic::fabs: Opcode = ISD::FABS; break; 5009 case Intrinsic::sin: Opcode = ISD::FSIN; break; 5010 case Intrinsic::cos: Opcode = ISD::FCOS; break; 5011 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; 5012 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; 5013 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; 5014 case Intrinsic::rint: Opcode = ISD::FRINT; break; 5015 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; 5016 case Intrinsic::round: Opcode = ISD::FROUND; break; 5017 } 5018 5019 setValue(&I, DAG.getNode(Opcode, sdl, 5020 getValue(I.getArgOperand(0)).getValueType(), 5021 getValue(I.getArgOperand(0)))); 5022 return 0; 5023 } 5024 case Intrinsic::copysign: 5025 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl, 5026 getValue(I.getArgOperand(0)).getValueType(), 5027 getValue(I.getArgOperand(0)), 5028 getValue(I.getArgOperand(1)))); 5029 return 0; 5030 case Intrinsic::fma: 5031 setValue(&I, DAG.getNode(ISD::FMA, sdl, 5032 getValue(I.getArgOperand(0)).getValueType(), 5033 getValue(I.getArgOperand(0)), 5034 getValue(I.getArgOperand(1)), 5035 getValue(I.getArgOperand(2)))); 5036 return 0; 5037 case Intrinsic::fmuladd: { 5038 EVT VT = TLI->getValueType(I.getType()); 5039 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict && 5040 TLI->isFMAFasterThanFMulAndFAdd(VT)) { 5041 setValue(&I, DAG.getNode(ISD::FMA, sdl, 5042 getValue(I.getArgOperand(0)).getValueType(), 5043 getValue(I.getArgOperand(0)), 5044 getValue(I.getArgOperand(1)), 5045 getValue(I.getArgOperand(2)))); 5046 } else { 5047 SDValue Mul = DAG.getNode(ISD::FMUL, sdl, 5048 getValue(I.getArgOperand(0)).getValueType(), 5049 getValue(I.getArgOperand(0)), 5050 getValue(I.getArgOperand(1))); 5051 SDValue Add = DAG.getNode(ISD::FADD, sdl, 5052 getValue(I.getArgOperand(0)).getValueType(), 5053 Mul, 5054 getValue(I.getArgOperand(2))); 5055 setValue(&I, Add); 5056 } 5057 return 0; 5058 } 5059 case Intrinsic::convert_to_fp16: 5060 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, sdl, 5061 MVT::i16, getValue(I.getArgOperand(0)))); 5062 return 0; 5063 case Intrinsic::convert_from_fp16: 5064 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, sdl, 5065 MVT::f32, getValue(I.getArgOperand(0)))); 5066 return 0; 5067 case Intrinsic::pcmarker: { 5068 SDValue Tmp = getValue(I.getArgOperand(0)); 5069 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp)); 5070 return 0; 5071 } 5072 case Intrinsic::readcyclecounter: { 5073 SDValue Op = getRoot(); 5074 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl, 5075 DAG.getVTList(MVT::i64, MVT::Other), 5076 &Op, 1); 5077 setValue(&I, Res); 5078 DAG.setRoot(Res.getValue(1)); 5079 return 0; 5080 } 5081 case Intrinsic::bswap: 5082 setValue(&I, DAG.getNode(ISD::BSWAP, sdl, 5083 getValue(I.getArgOperand(0)).getValueType(), 5084 getValue(I.getArgOperand(0)))); 5085 return 0; 5086 case Intrinsic::cttz: { 5087 SDValue Arg = getValue(I.getArgOperand(0)); 5088 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 5089 EVT Ty = Arg.getValueType(); 5090 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF, 5091 sdl, Ty, Arg)); 5092 return 0; 5093 } 5094 case Intrinsic::ctlz: { 5095 SDValue Arg = getValue(I.getArgOperand(0)); 5096 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1)); 5097 EVT Ty = Arg.getValueType(); 5098 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF, 5099 sdl, Ty, Arg)); 5100 return 0; 5101 } 5102 case Intrinsic::ctpop: { 5103 SDValue Arg = getValue(I.getArgOperand(0)); 5104 EVT Ty = Arg.getValueType(); 5105 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg)); 5106 return 0; 5107 } 5108 case Intrinsic::stacksave: { 5109 SDValue Op = getRoot(); 5110 Res = DAG.getNode(ISD::STACKSAVE, sdl, 5111 DAG.getVTList(TLI->getPointerTy(), MVT::Other), &Op, 1); 5112 setValue(&I, Res); 5113 DAG.setRoot(Res.getValue(1)); 5114 return 0; 5115 } 5116 case Intrinsic::stackrestore: { 5117 Res = getValue(I.getArgOperand(0)); 5118 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res)); 5119 return 0; 5120 } 5121 case Intrinsic::stackprotector: { 5122 // Emit code into the DAG to store the stack guard onto the stack. 5123 MachineFunction &MF = DAG.getMachineFunction(); 5124 MachineFrameInfo *MFI = MF.getFrameInfo(); 5125 EVT PtrTy = TLI->getPointerTy(); 5126 5127 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 5128 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 5129 5130 int FI = FuncInfo.StaticAllocaMap[Slot]; 5131 MFI->setStackProtectorIndex(FI); 5132 5133 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 5134 5135 // Store the stack protector onto the stack. 5136 Res = DAG.getStore(getRoot(), sdl, Src, FIN, 5137 MachinePointerInfo::getFixedStack(FI), 5138 true, false, 0); 5139 setValue(&I, Res); 5140 DAG.setRoot(Res); 5141 return 0; 5142 } 5143 case Intrinsic::objectsize: { 5144 // If we don't know by now, we're never going to know. 5145 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5146 5147 assert(CI && "Non-constant type in __builtin_object_size?"); 5148 5149 SDValue Arg = getValue(I.getCalledValue()); 5150 EVT Ty = Arg.getValueType(); 5151 5152 if (CI->isZero()) 5153 Res = DAG.getConstant(-1ULL, Ty); 5154 else 5155 Res = DAG.getConstant(0, Ty); 5156 5157 setValue(&I, Res); 5158 return 0; 5159 } 5160 case Intrinsic::annotation: 5161 case Intrinsic::ptr_annotation: 5162 // Drop the intrinsic, but forward the value 5163 setValue(&I, getValue(I.getOperand(0))); 5164 return 0; 5165 case Intrinsic::var_annotation: 5166 // Discard annotate attributes 5167 return 0; 5168 5169 case Intrinsic::init_trampoline: { 5170 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5171 5172 SDValue Ops[6]; 5173 Ops[0] = getRoot(); 5174 Ops[1] = getValue(I.getArgOperand(0)); 5175 Ops[2] = getValue(I.getArgOperand(1)); 5176 Ops[3] = getValue(I.getArgOperand(2)); 5177 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5178 Ops[5] = DAG.getSrcValue(F); 5179 5180 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops, 6); 5181 5182 DAG.setRoot(Res); 5183 return 0; 5184 } 5185 case Intrinsic::adjust_trampoline: { 5186 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl, 5187 TLI->getPointerTy(), 5188 getValue(I.getArgOperand(0)))); 5189 return 0; 5190 } 5191 case Intrinsic::gcroot: 5192 if (GFI) { 5193 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts(); 5194 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5195 5196 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5197 GFI->addStackRoot(FI->getIndex(), TypeMap); 5198 } 5199 return 0; 5200 case Intrinsic::gcread: 5201 case Intrinsic::gcwrite: 5202 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5203 case Intrinsic::flt_rounds: 5204 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32)); 5205 return 0; 5206 5207 case Intrinsic::expect: { 5208 // Just replace __builtin_expect(exp, c) with EXP. 5209 setValue(&I, getValue(I.getArgOperand(0))); 5210 return 0; 5211 } 5212 5213 case Intrinsic::debugtrap: 5214 case Intrinsic::trap: { 5215 StringRef TrapFuncName = TM.Options.getTrapFunctionName(); 5216 if (TrapFuncName.empty()) { 5217 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ? 5218 ISD::TRAP : ISD::DEBUGTRAP; 5219 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot())); 5220 return 0; 5221 } 5222 TargetLowering::ArgListTy Args; 5223 TargetLowering:: 5224 CallLoweringInfo CLI(getRoot(), I.getType(), 5225 false, false, false, false, 0, CallingConv::C, 5226 /*isTailCall=*/false, 5227 /*doesNotRet=*/false, /*isReturnValueUsed=*/true, 5228 DAG.getExternalSymbol(TrapFuncName.data(), 5229 TLI->getPointerTy()), 5230 Args, DAG, sdl); 5231 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI); 5232 DAG.setRoot(Result.second); 5233 return 0; 5234 } 5235 5236 case Intrinsic::uadd_with_overflow: 5237 case Intrinsic::sadd_with_overflow: 5238 case Intrinsic::usub_with_overflow: 5239 case Intrinsic::ssub_with_overflow: 5240 case Intrinsic::umul_with_overflow: 5241 case Intrinsic::smul_with_overflow: { 5242 ISD::NodeType Op; 5243 switch (Intrinsic) { 5244 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 5245 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break; 5246 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break; 5247 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break; 5248 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break; 5249 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; 5250 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; 5251 } 5252 SDValue Op1 = getValue(I.getArgOperand(0)); 5253 SDValue Op2 = getValue(I.getArgOperand(1)); 5254 5255 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 5256 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2)); 5257 return 0; 5258 } 5259 case Intrinsic::prefetch: { 5260 SDValue Ops[5]; 5261 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5262 Ops[0] = getRoot(); 5263 Ops[1] = getValue(I.getArgOperand(0)); 5264 Ops[2] = getValue(I.getArgOperand(1)); 5265 Ops[3] = getValue(I.getArgOperand(2)); 5266 Ops[4] = getValue(I.getArgOperand(3)); 5267 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl, 5268 DAG.getVTList(MVT::Other), 5269 &Ops[0], 5, 5270 EVT::getIntegerVT(*Context, 8), 5271 MachinePointerInfo(I.getArgOperand(0)), 5272 0, /* align */ 5273 false, /* volatile */ 5274 rw==0, /* read */ 5275 rw==1)); /* write */ 5276 return 0; 5277 } 5278 case Intrinsic::lifetime_start: 5279 case Intrinsic::lifetime_end: { 5280 bool IsStart = (Intrinsic == Intrinsic::lifetime_start); 5281 // Stack coloring is not enabled in O0, discard region information. 5282 if (TM.getOptLevel() == CodeGenOpt::None) 5283 return 0; 5284 5285 SmallVector<Value *, 4> Allocas; 5286 GetUnderlyingObjects(I.getArgOperand(1), Allocas, TD); 5287 5288 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(), 5289 E = Allocas.end(); Object != E; ++Object) { 5290 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object); 5291 5292 // Could not find an Alloca. 5293 if (!LifetimeObject) 5294 continue; 5295 5296 int FI = FuncInfo.StaticAllocaMap[LifetimeObject]; 5297 5298 SDValue Ops[2]; 5299 Ops[0] = getRoot(); 5300 Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true); 5301 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END); 5302 5303 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2); 5304 DAG.setRoot(Res); 5305 } 5306 return 0; 5307 } 5308 case Intrinsic::invariant_start: 5309 // Discard region information. 5310 setValue(&I, DAG.getUNDEF(TLI->getPointerTy())); 5311 return 0; 5312 case Intrinsic::invariant_end: 5313 // Discard region information. 5314 return 0; 5315 case Intrinsic::stackprotectorcheck: { 5316 // Do not actually emit anything for this basic block. Instead we initialize 5317 // the stack protector descriptor and export the guard variable so we can 5318 // access it in FinishBasicBlock. 5319 const BasicBlock *BB = I.getParent(); 5320 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I); 5321 ExportFromCurrentBlock(SPDescriptor.getGuard()); 5322 5323 // Flush our exports since we are going to process a terminator. 5324 (void)getControlRoot(); 5325 return 0; 5326 } 5327 case Intrinsic::donothing: 5328 // ignore 5329 return 0; 5330 case Intrinsic::experimental_stackmap: { 5331 visitStackmap(I); 5332 return 0; 5333 } 5334 case Intrinsic::experimental_patchpoint_void: 5335 case Intrinsic::experimental_patchpoint_i64: { 5336 visitPatchpoint(I); 5337 return 0; 5338 } 5339 } 5340} 5341 5342void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5343 bool isTailCall, 5344 MachineBasicBlock *LandingPad) { 5345 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5346 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5347 Type *RetTy = FTy->getReturnType(); 5348 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5349 MCSymbol *BeginLabel = 0; 5350 5351 TargetLowering::ArgListTy Args; 5352 TargetLowering::ArgListEntry Entry; 5353 Args.reserve(CS.arg_size()); 5354 5355 // Check whether the function can return without sret-demotion. 5356 SmallVector<ISD::OutputArg, 4> Outs; 5357 const TargetLowering *TLI = TM.getTargetLowering(); 5358 GetReturnInfo(RetTy, CS.getAttributes(), Outs, *TLI); 5359 5360 bool CanLowerReturn = TLI->CanLowerReturn(CS.getCallingConv(), 5361 DAG.getMachineFunction(), 5362 FTy->isVarArg(), Outs, 5363 FTy->getContext()); 5364 5365 SDValue DemoteStackSlot; 5366 int DemoteStackIdx = -100; 5367 5368 if (!CanLowerReturn) { 5369 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize( 5370 FTy->getReturnType()); 5371 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment( 5372 FTy->getReturnType()); 5373 MachineFunction &MF = DAG.getMachineFunction(); 5374 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5375 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5376 5377 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI->getPointerTy()); 5378 Entry.Node = DemoteStackSlot; 5379 Entry.Ty = StackSlotPtrType; 5380 Entry.isSExt = false; 5381 Entry.isZExt = false; 5382 Entry.isInReg = false; 5383 Entry.isSRet = true; 5384 Entry.isNest = false; 5385 Entry.isByVal = false; 5386 Entry.isReturned = false; 5387 Entry.Alignment = Align; 5388 Args.push_back(Entry); 5389 RetTy = Type::getVoidTy(FTy->getContext()); 5390 } 5391 5392 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5393 i != e; ++i) { 5394 const Value *V = *i; 5395 5396 // Skip empty types 5397 if (V->getType()->isEmptyTy()) 5398 continue; 5399 5400 SDValue ArgNode = getValue(V); 5401 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5402 5403 // Skip the first return-type Attribute to get to params. 5404 Entry.setAttributes(&CS, i - CS.arg_begin() + 1); 5405 Args.push_back(Entry); 5406 } 5407 5408 if (LandingPad) { 5409 // Insert a label before the invoke call to mark the try range. This can be 5410 // used to detect deletion of the invoke via the MachineModuleInfo. 5411 BeginLabel = MMI.getContext().CreateTempSymbol(); 5412 5413 // For SjLj, keep track of which landing pads go with which invokes 5414 // so as to maintain the ordering of pads in the LSDA. 5415 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5416 if (CallSiteIndex) { 5417 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5418 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5419 5420 // Now that the call site is handled, stop tracking it. 5421 MMI.setCurrentCallSite(0); 5422 } 5423 5424 // Both PendingLoads and PendingExports must be flushed here; 5425 // this call might not return. 5426 (void)getRoot(); 5427 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel)); 5428 } 5429 5430 // Check if target-independent constraints permit a tail call here. 5431 // Target-dependent constraints are checked within TLI->LowerCallTo. 5432 if (isTailCall && !isInTailCallPosition(CS, *TLI)) 5433 isTailCall = false; 5434 5435 TargetLowering:: 5436 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG, 5437 getCurSDLoc(), CS); 5438 std::pair<SDValue,SDValue> Result = TLI->LowerCallTo(CLI); 5439 assert((isTailCall || Result.second.getNode()) && 5440 "Non-null chain expected with non-tail call!"); 5441 assert((Result.second.getNode() || !Result.first.getNode()) && 5442 "Null value expected with tail call!"); 5443 if (Result.first.getNode()) { 5444 setValue(CS.getInstruction(), Result.first); 5445 } else if (!CanLowerReturn && Result.second.getNode()) { 5446 // The instruction result is the result of loading from the 5447 // hidden sret parameter. 5448 SmallVector<EVT, 1> PVTs; 5449 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5450 5451 ComputeValueVTs(*TLI, PtrRetTy, PVTs); 5452 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5453 EVT PtrVT = PVTs[0]; 5454 5455 SmallVector<EVT, 4> RetTys; 5456 SmallVector<uint64_t, 4> Offsets; 5457 RetTy = FTy->getReturnType(); 5458 ComputeValueVTs(*TLI, RetTy, RetTys, &Offsets); 5459 5460 unsigned NumValues = RetTys.size(); 5461 SmallVector<SDValue, 4> Values(NumValues); 5462 SmallVector<SDValue, 4> Chains(NumValues); 5463 5464 for (unsigned i = 0; i < NumValues; ++i) { 5465 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, 5466 DemoteStackSlot, 5467 DAG.getConstant(Offsets[i], PtrVT)); 5468 SDValue L = DAG.getLoad(RetTys[i], getCurSDLoc(), Result.second, Add, 5469 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5470 false, false, false, 1); 5471 Values[i] = L; 5472 Chains[i] = L.getValue(1); 5473 } 5474 5475 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), 5476 MVT::Other, &Chains[0], NumValues); 5477 PendingLoads.push_back(Chain); 5478 5479 setValue(CS.getInstruction(), 5480 DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), 5481 DAG.getVTList(&RetTys[0], RetTys.size()), 5482 &Values[0], Values.size())); 5483 } 5484 5485 if (!Result.second.getNode()) { 5486 // As a special case, a null chain means that a tail call has been emitted 5487 // and the DAG root is already updated. 5488 HasTailCall = true; 5489 5490 // Since there's no actual continuation from this block, nothing can be 5491 // relying on us setting vregs for them. 5492 PendingExports.clear(); 5493 } else { 5494 DAG.setRoot(Result.second); 5495 } 5496 5497 if (LandingPad) { 5498 // Insert a label at the end of the invoke call to mark the try range. This 5499 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5500 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5501 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel)); 5502 5503 // Inform MachineModuleInfo of range. 5504 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5505 } 5506} 5507 5508/// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5509/// value is equal or not-equal to zero. 5510static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5511 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5512 UI != E; ++UI) { 5513 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5514 if (IC->isEquality()) 5515 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5516 if (C->isNullValue()) 5517 continue; 5518 // Unknown instruction. 5519 return false; 5520 } 5521 return true; 5522} 5523 5524static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5525 Type *LoadTy, 5526 SelectionDAGBuilder &Builder) { 5527 5528 // Check to see if this load can be trivially constant folded, e.g. if the 5529 // input is from a string literal. 5530 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5531 // Cast pointer to the type we really want to load. 5532 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5533 PointerType::getUnqual(LoadTy)); 5534 5535 if (const Constant *LoadCst = 5536 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5537 Builder.TD)) 5538 return Builder.getValue(LoadCst); 5539 } 5540 5541 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5542 // still constant memory, the input chain can be the entry node. 5543 SDValue Root; 5544 bool ConstantMemory = false; 5545 5546 // Do not serialize (non-volatile) loads of constant memory with anything. 5547 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5548 Root = Builder.DAG.getEntryNode(); 5549 ConstantMemory = true; 5550 } else { 5551 // Do not serialize non-volatile loads against each other. 5552 Root = Builder.DAG.getRoot(); 5553 } 5554 5555 SDValue Ptr = Builder.getValue(PtrVal); 5556 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root, 5557 Ptr, MachinePointerInfo(PtrVal), 5558 false /*volatile*/, 5559 false /*nontemporal*/, 5560 false /*isinvariant*/, 1 /* align=1 */); 5561 5562 if (!ConstantMemory) 5563 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5564 return LoadVal; 5565} 5566 5567/// processIntegerCallValue - Record the value for an instruction that 5568/// produces an integer result, converting the type where necessary. 5569void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I, 5570 SDValue Value, 5571 bool IsSigned) { 5572 EVT VT = TM.getTargetLowering()->getValueType(I.getType(), true); 5573 if (IsSigned) 5574 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT); 5575 else 5576 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT); 5577 setValue(&I, Value); 5578} 5579 5580/// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5581/// If so, return true and lower it, otherwise return false and it will be 5582/// lowered like a normal call. 5583bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5584 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5585 if (I.getNumArgOperands() != 3) 5586 return false; 5587 5588 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5589 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5590 !I.getArgOperand(2)->getType()->isIntegerTy() || 5591 !I.getType()->isIntegerTy()) 5592 return false; 5593 5594 const Value *Size = I.getArgOperand(2); 5595 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size); 5596 if (CSize && CSize->getZExtValue() == 0) { 5597 EVT CallVT = TM.getTargetLowering()->getValueType(I.getType(), true); 5598 setValue(&I, DAG.getConstant(0, CallVT)); 5599 return true; 5600 } 5601 5602 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo(); 5603 std::pair<SDValue, SDValue> Res = 5604 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(), 5605 getValue(LHS), getValue(RHS), getValue(Size), 5606 MachinePointerInfo(LHS), 5607 MachinePointerInfo(RHS)); 5608 if (Res.first.getNode()) { 5609 processIntegerCallValue(I, Res.first, true); 5610 PendingLoads.push_back(Res.second); 5611 return true; 5612 } 5613 5614 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5615 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5616 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) { 5617 bool ActuallyDoIt = true; 5618 MVT LoadVT; 5619 Type *LoadTy; 5620 switch (CSize->getZExtValue()) { 5621 default: 5622 LoadVT = MVT::Other; 5623 LoadTy = 0; 5624 ActuallyDoIt = false; 5625 break; 5626 case 2: 5627 LoadVT = MVT::i16; 5628 LoadTy = Type::getInt16Ty(CSize->getContext()); 5629 break; 5630 case 4: 5631 LoadVT = MVT::i32; 5632 LoadTy = Type::getInt32Ty(CSize->getContext()); 5633 break; 5634 case 8: 5635 LoadVT = MVT::i64; 5636 LoadTy = Type::getInt64Ty(CSize->getContext()); 5637 break; 5638 /* 5639 case 16: 5640 LoadVT = MVT::v4i32; 5641 LoadTy = Type::getInt32Ty(CSize->getContext()); 5642 LoadTy = VectorType::get(LoadTy, 4); 5643 break; 5644 */ 5645 } 5646 5647 // This turns into unaligned loads. We only do this if the target natively 5648 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5649 // we'll only produce a small number of byte loads. 5650 5651 // Require that we can find a legal MVT, and only do this if the target 5652 // supports unaligned loads of that type. Expanding into byte loads would 5653 // bloat the code. 5654 const TargetLowering *TLI = TM.getTargetLowering(); 5655 if (ActuallyDoIt && CSize->getZExtValue() > 4) { 5656 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5657 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5658 if (!TLI->isTypeLegal(LoadVT) ||!TLI->allowsUnalignedMemoryAccesses(LoadVT)) 5659 ActuallyDoIt = false; 5660 } 5661 5662 if (ActuallyDoIt) { 5663 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5664 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5665 5666 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal, 5667 ISD::SETNE); 5668 processIntegerCallValue(I, Res, false); 5669 return true; 5670 } 5671 } 5672 5673 5674 return false; 5675} 5676 5677/// visitMemChrCall -- See if we can lower a memchr call into an optimized 5678/// form. If so, return true and lower it, otherwise return false and it 5679/// will be lowered like a normal call. 5680bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) { 5681 // Verify that the prototype makes sense. void *memchr(void *, int, size_t) 5682 if (I.getNumArgOperands() != 3) 5683 return false; 5684 5685 const Value *Src = I.getArgOperand(0); 5686 const Value *Char = I.getArgOperand(1); 5687 const Value *Length = I.getArgOperand(2); 5688 if (!Src->getType()->isPointerTy() || 5689 !Char->getType()->isIntegerTy() || 5690 !Length->getType()->isIntegerTy() || 5691 !I.getType()->isPointerTy()) 5692 return false; 5693 5694 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo(); 5695 std::pair<SDValue, SDValue> Res = 5696 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(), 5697 getValue(Src), getValue(Char), getValue(Length), 5698 MachinePointerInfo(Src)); 5699 if (Res.first.getNode()) { 5700 setValue(&I, Res.first); 5701 PendingLoads.push_back(Res.second); 5702 return true; 5703 } 5704 5705 return false; 5706} 5707 5708/// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an 5709/// optimized form. If so, return true and lower it, otherwise return false 5710/// and it will be lowered like a normal call. 5711bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) { 5712 // Verify that the prototype makes sense. char *strcpy(char *, char *) 5713 if (I.getNumArgOperands() != 2) 5714 return false; 5715 5716 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); 5717 if (!Arg0->getType()->isPointerTy() || 5718 !Arg1->getType()->isPointerTy() || 5719 !I.getType()->isPointerTy()) 5720 return false; 5721 5722 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo(); 5723 std::pair<SDValue, SDValue> Res = 5724 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(), 5725 getValue(Arg0), getValue(Arg1), 5726 MachinePointerInfo(Arg0), 5727 MachinePointerInfo(Arg1), isStpcpy); 5728 if (Res.first.getNode()) { 5729 setValue(&I, Res.first); 5730 DAG.setRoot(Res.second); 5731 return true; 5732 } 5733 5734 return false; 5735} 5736 5737/// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form. 5738/// If so, return true and lower it, otherwise return false and it will be 5739/// lowered like a normal call. 5740bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) { 5741 // Verify that the prototype makes sense. int strcmp(void*,void*) 5742 if (I.getNumArgOperands() != 2) 5743 return false; 5744 5745 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); 5746 if (!Arg0->getType()->isPointerTy() || 5747 !Arg1->getType()->isPointerTy() || 5748 !I.getType()->isIntegerTy()) 5749 return false; 5750 5751 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo(); 5752 std::pair<SDValue, SDValue> Res = 5753 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(), 5754 getValue(Arg0), getValue(Arg1), 5755 MachinePointerInfo(Arg0), 5756 MachinePointerInfo(Arg1)); 5757 if (Res.first.getNode()) { 5758 processIntegerCallValue(I, Res.first, true); 5759 PendingLoads.push_back(Res.second); 5760 return true; 5761 } 5762 5763 return false; 5764} 5765 5766/// visitStrLenCall -- See if we can lower a strlen call into an optimized 5767/// form. If so, return true and lower it, otherwise return false and it 5768/// will be lowered like a normal call. 5769bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) { 5770 // Verify that the prototype makes sense. size_t strlen(char *) 5771 if (I.getNumArgOperands() != 1) 5772 return false; 5773 5774 const Value *Arg0 = I.getArgOperand(0); 5775 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy()) 5776 return false; 5777 5778 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo(); 5779 std::pair<SDValue, SDValue> Res = 5780 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(), 5781 getValue(Arg0), MachinePointerInfo(Arg0)); 5782 if (Res.first.getNode()) { 5783 processIntegerCallValue(I, Res.first, false); 5784 PendingLoads.push_back(Res.second); 5785 return true; 5786 } 5787 5788 return false; 5789} 5790 5791/// visitStrNLenCall -- See if we can lower a strnlen call into an optimized 5792/// form. If so, return true and lower it, otherwise return false and it 5793/// will be lowered like a normal call. 5794bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) { 5795 // Verify that the prototype makes sense. size_t strnlen(char *, size_t) 5796 if (I.getNumArgOperands() != 2) 5797 return false; 5798 5799 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); 5800 if (!Arg0->getType()->isPointerTy() || 5801 !Arg1->getType()->isIntegerTy() || 5802 !I.getType()->isIntegerTy()) 5803 return false; 5804 5805 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo(); 5806 std::pair<SDValue, SDValue> Res = 5807 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(), 5808 getValue(Arg0), getValue(Arg1), 5809 MachinePointerInfo(Arg0)); 5810 if (Res.first.getNode()) { 5811 processIntegerCallValue(I, Res.first, false); 5812 PendingLoads.push_back(Res.second); 5813 return true; 5814 } 5815 5816 return false; 5817} 5818 5819/// visitUnaryFloatCall - If a call instruction is a unary floating-point 5820/// operation (as expected), translate it to an SDNode with the specified opcode 5821/// and return true. 5822bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I, 5823 unsigned Opcode) { 5824 // Sanity check that it really is a unary floating-point call. 5825 if (I.getNumArgOperands() != 1 || 5826 !I.getArgOperand(0)->getType()->isFloatingPointTy() || 5827 I.getType() != I.getArgOperand(0)->getType() || 5828 !I.onlyReadsMemory()) 5829 return false; 5830 5831 SDValue Tmp = getValue(I.getArgOperand(0)); 5832 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp)); 5833 return true; 5834} 5835 5836void SelectionDAGBuilder::visitCall(const CallInst &I) { 5837 // Handle inline assembly differently. 5838 if (isa<InlineAsm>(I.getCalledValue())) { 5839 visitInlineAsm(&I); 5840 return; 5841 } 5842 5843 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5844 ComputeUsesVAFloatArgument(I, &MMI); 5845 5846 const char *RenameFn = 0; 5847 if (Function *F = I.getCalledFunction()) { 5848 if (F->isDeclaration()) { 5849 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5850 if (unsigned IID = II->getIntrinsicID(F)) { 5851 RenameFn = visitIntrinsicCall(I, IID); 5852 if (!RenameFn) 5853 return; 5854 } 5855 } 5856 if (unsigned IID = F->getIntrinsicID()) { 5857 RenameFn = visitIntrinsicCall(I, IID); 5858 if (!RenameFn) 5859 return; 5860 } 5861 } 5862 5863 // Check for well-known libc/libm calls. If the function is internal, it 5864 // can't be a library call. 5865 LibFunc::Func Func; 5866 if (!F->hasLocalLinkage() && F->hasName() && 5867 LibInfo->getLibFunc(F->getName(), Func) && 5868 LibInfo->hasOptimizedCodeGen(Func)) { 5869 switch (Func) { 5870 default: break; 5871 case LibFunc::copysign: 5872 case LibFunc::copysignf: 5873 case LibFunc::copysignl: 5874 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5875 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5876 I.getType() == I.getArgOperand(0)->getType() && 5877 I.getType() == I.getArgOperand(1)->getType() && 5878 I.onlyReadsMemory()) { 5879 SDValue LHS = getValue(I.getArgOperand(0)); 5880 SDValue RHS = getValue(I.getArgOperand(1)); 5881 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(), 5882 LHS.getValueType(), LHS, RHS)); 5883 return; 5884 } 5885 break; 5886 case LibFunc::fabs: 5887 case LibFunc::fabsf: 5888 case LibFunc::fabsl: 5889 if (visitUnaryFloatCall(I, ISD::FABS)) 5890 return; 5891 break; 5892 case LibFunc::sin: 5893 case LibFunc::sinf: 5894 case LibFunc::sinl: 5895 if (visitUnaryFloatCall(I, ISD::FSIN)) 5896 return; 5897 break; 5898 case LibFunc::cos: 5899 case LibFunc::cosf: 5900 case LibFunc::cosl: 5901 if (visitUnaryFloatCall(I, ISD::FCOS)) 5902 return; 5903 break; 5904 case LibFunc::sqrt: 5905 case LibFunc::sqrtf: 5906 case LibFunc::sqrtl: 5907 case LibFunc::sqrt_finite: 5908 case LibFunc::sqrtf_finite: 5909 case LibFunc::sqrtl_finite: 5910 if (visitUnaryFloatCall(I, ISD::FSQRT)) 5911 return; 5912 break; 5913 case LibFunc::floor: 5914 case LibFunc::floorf: 5915 case LibFunc::floorl: 5916 if (visitUnaryFloatCall(I, ISD::FFLOOR)) 5917 return; 5918 break; 5919 case LibFunc::nearbyint: 5920 case LibFunc::nearbyintf: 5921 case LibFunc::nearbyintl: 5922 if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) 5923 return; 5924 break; 5925 case LibFunc::ceil: 5926 case LibFunc::ceilf: 5927 case LibFunc::ceill: 5928 if (visitUnaryFloatCall(I, ISD::FCEIL)) 5929 return; 5930 break; 5931 case LibFunc::rint: 5932 case LibFunc::rintf: 5933 case LibFunc::rintl: 5934 if (visitUnaryFloatCall(I, ISD::FRINT)) 5935 return; 5936 break; 5937 case LibFunc::round: 5938 case LibFunc::roundf: 5939 case LibFunc::roundl: 5940 if (visitUnaryFloatCall(I, ISD::FROUND)) 5941 return; 5942 break; 5943 case LibFunc::trunc: 5944 case LibFunc::truncf: 5945 case LibFunc::truncl: 5946 if (visitUnaryFloatCall(I, ISD::FTRUNC)) 5947 return; 5948 break; 5949 case LibFunc::log2: 5950 case LibFunc::log2f: 5951 case LibFunc::log2l: 5952 if (visitUnaryFloatCall(I, ISD::FLOG2)) 5953 return; 5954 break; 5955 case LibFunc::exp2: 5956 case LibFunc::exp2f: 5957 case LibFunc::exp2l: 5958 if (visitUnaryFloatCall(I, ISD::FEXP2)) 5959 return; 5960 break; 5961 case LibFunc::memcmp: 5962 if (visitMemCmpCall(I)) 5963 return; 5964 break; 5965 case LibFunc::memchr: 5966 if (visitMemChrCall(I)) 5967 return; 5968 break; 5969 case LibFunc::strcpy: 5970 if (visitStrCpyCall(I, false)) 5971 return; 5972 break; 5973 case LibFunc::stpcpy: 5974 if (visitStrCpyCall(I, true)) 5975 return; 5976 break; 5977 case LibFunc::strcmp: 5978 if (visitStrCmpCall(I)) 5979 return; 5980 break; 5981 case LibFunc::strlen: 5982 if (visitStrLenCall(I)) 5983 return; 5984 break; 5985 case LibFunc::strnlen: 5986 if (visitStrNLenCall(I)) 5987 return; 5988 break; 5989 } 5990 } 5991 } 5992 5993 SDValue Callee; 5994 if (!RenameFn) 5995 Callee = getValue(I.getCalledValue()); 5996 else 5997 Callee = DAG.getExternalSymbol(RenameFn, 5998 TM.getTargetLowering()->getPointerTy()); 5999 6000 // Check if we can potentially perform a tail call. More detailed checking is 6001 // be done within LowerCallTo, after more information about the call is known. 6002 LowerCallTo(&I, Callee, I.isTailCall()); 6003} 6004 6005namespace { 6006 6007/// AsmOperandInfo - This contains information for each constraint that we are 6008/// lowering. 6009class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 6010public: 6011 /// CallOperand - If this is the result output operand or a clobber 6012 /// this is null, otherwise it is the incoming operand to the CallInst. 6013 /// This gets modified as the asm is processed. 6014 SDValue CallOperand; 6015 6016 /// AssignedRegs - If this is a register or register class operand, this 6017 /// contains the set of register corresponding to the operand. 6018 RegsForValue AssignedRegs; 6019 6020 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 6021 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 6022 } 6023 6024 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 6025 /// corresponds to. If there is no Value* for this operand, it returns 6026 /// MVT::Other. 6027 EVT getCallOperandValEVT(LLVMContext &Context, 6028 const TargetLowering &TLI, 6029 const DataLayout *TD) const { 6030 if (CallOperandVal == 0) return MVT::Other; 6031 6032 if (isa<BasicBlock>(CallOperandVal)) 6033 return TLI.getPointerTy(); 6034 6035 llvm::Type *OpTy = CallOperandVal->getType(); 6036 6037 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 6038 // If this is an indirect operand, the operand is a pointer to the 6039 // accessed type. 6040 if (isIndirect) { 6041 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 6042 if (!PtrTy) 6043 report_fatal_error("Indirect operand for inline asm not a pointer!"); 6044 OpTy = PtrTy->getElementType(); 6045 } 6046 6047 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 6048 if (StructType *STy = dyn_cast<StructType>(OpTy)) 6049 if (STy->getNumElements() == 1) 6050 OpTy = STy->getElementType(0); 6051 6052 // If OpTy is not a single value, it may be a struct/union that we 6053 // can tile with integers. 6054 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 6055 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 6056 switch (BitSize) { 6057 default: break; 6058 case 1: 6059 case 8: 6060 case 16: 6061 case 32: 6062 case 64: 6063 case 128: 6064 OpTy = IntegerType::get(Context, BitSize); 6065 break; 6066 } 6067 } 6068 6069 return TLI.getValueType(OpTy, true); 6070 } 6071}; 6072 6073typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 6074 6075} // end anonymous namespace 6076 6077/// GetRegistersForValue - Assign registers (virtual or physical) for the 6078/// specified operand. We prefer to assign virtual registers, to allow the 6079/// register allocator to handle the assignment process. However, if the asm 6080/// uses features that we can't model on machineinstrs, we have SDISel do the 6081/// allocation. This produces generally horrible, but correct, code. 6082/// 6083/// OpInfo describes the operand. 6084/// 6085static void GetRegistersForValue(SelectionDAG &DAG, 6086 const TargetLowering &TLI, 6087 SDLoc DL, 6088 SDISelAsmOperandInfo &OpInfo) { 6089 LLVMContext &Context = *DAG.getContext(); 6090 6091 MachineFunction &MF = DAG.getMachineFunction(); 6092 SmallVector<unsigned, 4> Regs; 6093 6094 // If this is a constraint for a single physreg, or a constraint for a 6095 // register class, find it. 6096 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 6097 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 6098 OpInfo.ConstraintVT); 6099 6100 unsigned NumRegs = 1; 6101 if (OpInfo.ConstraintVT != MVT::Other) { 6102 // If this is a FP input in an integer register (or visa versa) insert a bit 6103 // cast of the input value. More generally, handle any case where the input 6104 // value disagrees with the register class we plan to stick this in. 6105 if (OpInfo.Type == InlineAsm::isInput && 6106 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 6107 // Try to convert to the first EVT that the reg class contains. If the 6108 // types are identical size, use a bitcast to convert (e.g. two differing 6109 // vector types). 6110 MVT RegVT = *PhysReg.second->vt_begin(); 6111 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 6112 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 6113 RegVT, OpInfo.CallOperand); 6114 OpInfo.ConstraintVT = RegVT; 6115 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 6116 // If the input is a FP value and we want it in FP registers, do a 6117 // bitcast to the corresponding integer type. This turns an f64 value 6118 // into i64, which can be passed with two i32 values on a 32-bit 6119 // machine. 6120 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); 6121 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 6122 RegVT, OpInfo.CallOperand); 6123 OpInfo.ConstraintVT = RegVT; 6124 } 6125 } 6126 6127 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 6128 } 6129 6130 MVT RegVT; 6131 EVT ValueVT = OpInfo.ConstraintVT; 6132 6133 // If this is a constraint for a specific physical register, like {r17}, 6134 // assign it now. 6135 if (unsigned AssignedReg = PhysReg.first) { 6136 const TargetRegisterClass *RC = PhysReg.second; 6137 if (OpInfo.ConstraintVT == MVT::Other) 6138 ValueVT = *RC->vt_begin(); 6139 6140 // Get the actual register value type. This is important, because the user 6141 // may have asked for (e.g.) the AX register in i32 type. We need to 6142 // remember that AX is actually i16 to get the right extension. 6143 RegVT = *RC->vt_begin(); 6144 6145 // This is a explicit reference to a physical register. 6146 Regs.push_back(AssignedReg); 6147 6148 // If this is an expanded reference, add the rest of the regs to Regs. 6149 if (NumRegs != 1) { 6150 TargetRegisterClass::iterator I = RC->begin(); 6151 for (; *I != AssignedReg; ++I) 6152 assert(I != RC->end() && "Didn't find reg!"); 6153 6154 // Already added the first reg. 6155 --NumRegs; ++I; 6156 for (; NumRegs; --NumRegs, ++I) { 6157 assert(I != RC->end() && "Ran out of registers to allocate!"); 6158 Regs.push_back(*I); 6159 } 6160 } 6161 6162 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 6163 return; 6164 } 6165 6166 // Otherwise, if this was a reference to an LLVM register class, create vregs 6167 // for this reference. 6168 if (const TargetRegisterClass *RC = PhysReg.second) { 6169 RegVT = *RC->vt_begin(); 6170 if (OpInfo.ConstraintVT == MVT::Other) 6171 ValueVT = RegVT; 6172 6173 // Create the appropriate number of virtual registers. 6174 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 6175 for (; NumRegs; --NumRegs) 6176 Regs.push_back(RegInfo.createVirtualRegister(RC)); 6177 6178 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 6179 return; 6180 } 6181 6182 // Otherwise, we couldn't allocate enough registers for this. 6183} 6184 6185/// visitInlineAsm - Handle a call to an InlineAsm object. 6186/// 6187void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 6188 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 6189 6190 /// ConstraintOperands - Information about all of the constraints. 6191 SDISelAsmOperandInfoVector ConstraintOperands; 6192 6193 const TargetLowering *TLI = TM.getTargetLowering(); 6194 TargetLowering::AsmOperandInfoVector 6195 TargetConstraints = TLI->ParseConstraints(CS); 6196 6197 bool hasMemory = false; 6198 6199 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 6200 unsigned ResNo = 0; // ResNo - The result number of the next output. 6201 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 6202 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 6203 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 6204 6205 MVT OpVT = MVT::Other; 6206 6207 // Compute the value type for each operand. 6208 switch (OpInfo.Type) { 6209 case InlineAsm::isOutput: 6210 // Indirect outputs just consume an argument. 6211 if (OpInfo.isIndirect) { 6212 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 6213 break; 6214 } 6215 6216 // The return value of the call is this value. As such, there is no 6217 // corresponding argument. 6218 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6219 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 6220 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo)); 6221 } else { 6222 assert(ResNo == 0 && "Asm only has one result!"); 6223 OpVT = TLI->getSimpleValueType(CS.getType()); 6224 } 6225 ++ResNo; 6226 break; 6227 case InlineAsm::isInput: 6228 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 6229 break; 6230 case InlineAsm::isClobber: 6231 // Nothing to do. 6232 break; 6233 } 6234 6235 // If this is an input or an indirect output, process the call argument. 6236 // BasicBlocks are labels, currently appearing only in asm's. 6237 if (OpInfo.CallOperandVal) { 6238 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 6239 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 6240 } else { 6241 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 6242 } 6243 6244 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), *TLI, TD). 6245 getSimpleVT(); 6246 } 6247 6248 OpInfo.ConstraintVT = OpVT; 6249 6250 // Indirect operand accesses access memory. 6251 if (OpInfo.isIndirect) 6252 hasMemory = true; 6253 else { 6254 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 6255 TargetLowering::ConstraintType 6256 CType = TLI->getConstraintType(OpInfo.Codes[j]); 6257 if (CType == TargetLowering::C_Memory) { 6258 hasMemory = true; 6259 break; 6260 } 6261 } 6262 } 6263 } 6264 6265 SDValue Chain, Flag; 6266 6267 // We won't need to flush pending loads if this asm doesn't touch 6268 // memory and is nonvolatile. 6269 if (hasMemory || IA->hasSideEffects()) 6270 Chain = getRoot(); 6271 else 6272 Chain = DAG.getRoot(); 6273 6274 // Second pass over the constraints: compute which constraint option to use 6275 // and assign registers to constraints that want a specific physreg. 6276 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6277 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6278 6279 // If this is an output operand with a matching input operand, look up the 6280 // matching input. If their types mismatch, e.g. one is an integer, the 6281 // other is floating point, or their sizes are different, flag it as an 6282 // error. 6283 if (OpInfo.hasMatchingInput()) { 6284 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 6285 6286 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 6287 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 6288 TLI->getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 6289 OpInfo.ConstraintVT); 6290 std::pair<unsigned, const TargetRegisterClass*> InputRC = 6291 TLI->getRegForInlineAsmConstraint(Input.ConstraintCode, 6292 Input.ConstraintVT); 6293 if ((OpInfo.ConstraintVT.isInteger() != 6294 Input.ConstraintVT.isInteger()) || 6295 (MatchRC.second != InputRC.second)) { 6296 report_fatal_error("Unsupported asm: input constraint" 6297 " with a matching output constraint of" 6298 " incompatible type!"); 6299 } 6300 Input.ConstraintVT = OpInfo.ConstraintVT; 6301 } 6302 } 6303 6304 // Compute the constraint code and ConstraintType to use. 6305 TLI->ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 6306 6307 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 6308 OpInfo.Type == InlineAsm::isClobber) 6309 continue; 6310 6311 // If this is a memory input, and if the operand is not indirect, do what we 6312 // need to to provide an address for the memory input. 6313 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 6314 !OpInfo.isIndirect) { 6315 assert((OpInfo.isMultipleAlternative || 6316 (OpInfo.Type == InlineAsm::isInput)) && 6317 "Can only indirectify direct input operands!"); 6318 6319 // Memory operands really want the address of the value. If we don't have 6320 // an indirect input, put it in the constpool if we can, otherwise spill 6321 // it to a stack slot. 6322 // TODO: This isn't quite right. We need to handle these according to 6323 // the addressing mode that the constraint wants. Also, this may take 6324 // an additional register for the computation and we don't want that 6325 // either. 6326 6327 // If the operand is a float, integer, or vector constant, spill to a 6328 // constant pool entry to get its address. 6329 const Value *OpVal = OpInfo.CallOperandVal; 6330 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 6331 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) { 6332 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 6333 TLI->getPointerTy()); 6334 } else { 6335 // Otherwise, create a stack slot and emit a store to it before the 6336 // asm. 6337 Type *Ty = OpVal->getType(); 6338 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty); 6339 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(Ty); 6340 MachineFunction &MF = DAG.getMachineFunction(); 6341 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 6342 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI->getPointerTy()); 6343 Chain = DAG.getStore(Chain, getCurSDLoc(), 6344 OpInfo.CallOperand, StackSlot, 6345 MachinePointerInfo::getFixedStack(SSFI), 6346 false, false, 0); 6347 OpInfo.CallOperand = StackSlot; 6348 } 6349 6350 // There is no longer a Value* corresponding to this operand. 6351 OpInfo.CallOperandVal = 0; 6352 6353 // It is now an indirect operand. 6354 OpInfo.isIndirect = true; 6355 } 6356 6357 // If this constraint is for a specific register, allocate it before 6358 // anything else. 6359 if (OpInfo.ConstraintType == TargetLowering::C_Register) 6360 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo); 6361 } 6362 6363 // Second pass - Loop over all of the operands, assigning virtual or physregs 6364 // to register class operands. 6365 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6366 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6367 6368 // C_Register operands have already been allocated, Other/Memory don't need 6369 // to be. 6370 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 6371 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo); 6372 } 6373 6374 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6375 std::vector<SDValue> AsmNodeOperands; 6376 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6377 AsmNodeOperands.push_back( 6378 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6379 TLI->getPointerTy())); 6380 6381 // If we have a !srcloc metadata node associated with it, we want to attach 6382 // this to the ultimately generated inline asm machineinstr. To do this, we 6383 // pass in the third operand as this (potentially null) inline asm MDNode. 6384 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6385 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6386 6387 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore 6388 // bits as operand 3. 6389 unsigned ExtraInfo = 0; 6390 if (IA->hasSideEffects()) 6391 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6392 if (IA->isAlignStack()) 6393 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6394 // Set the asm dialect. 6395 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect; 6396 6397 // Determine if this InlineAsm MayLoad or MayStore based on the constraints. 6398 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 6399 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i]; 6400 6401 // Compute the constraint code and ConstraintType to use. 6402 TLI->ComputeConstraintToUse(OpInfo, SDValue()); 6403 6404 // Ideally, we would only check against memory constraints. However, the 6405 // meaning of an other constraint can be target-specific and we can't easily 6406 // reason about it. Therefore, be conservative and set MayLoad/MayStore 6407 // for other constriants as well. 6408 if (OpInfo.ConstraintType == TargetLowering::C_Memory || 6409 OpInfo.ConstraintType == TargetLowering::C_Other) { 6410 if (OpInfo.Type == InlineAsm::isInput) 6411 ExtraInfo |= InlineAsm::Extra_MayLoad; 6412 else if (OpInfo.Type == InlineAsm::isOutput) 6413 ExtraInfo |= InlineAsm::Extra_MayStore; 6414 else if (OpInfo.Type == InlineAsm::isClobber) 6415 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore); 6416 } 6417 } 6418 6419 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6420 TLI->getPointerTy())); 6421 6422 // Loop over all of the inputs, copying the operand values into the 6423 // appropriate registers and processing the output regs. 6424 RegsForValue RetValRegs; 6425 6426 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6427 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6428 6429 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6430 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6431 6432 switch (OpInfo.Type) { 6433 case InlineAsm::isOutput: { 6434 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6435 OpInfo.ConstraintType != TargetLowering::C_Register) { 6436 // Memory output, or 'other' output (e.g. 'X' constraint). 6437 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6438 6439 // Add information to the INLINEASM node to know about this output. 6440 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6441 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6442 TLI->getPointerTy())); 6443 AsmNodeOperands.push_back(OpInfo.CallOperand); 6444 break; 6445 } 6446 6447 // Otherwise, this is a register or register class output. 6448 6449 // Copy the output from the appropriate register. Find a register that 6450 // we can use. 6451 if (OpInfo.AssignedRegs.Regs.empty()) { 6452 LLVMContext &Ctx = *DAG.getContext(); 6453 Ctx.emitError(CS.getInstruction(), 6454 "couldn't allocate output register for constraint '" + 6455 Twine(OpInfo.ConstraintCode) + "'"); 6456 return; 6457 } 6458 6459 // If this is an indirect operand, store through the pointer after the 6460 // asm. 6461 if (OpInfo.isIndirect) { 6462 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6463 OpInfo.CallOperandVal)); 6464 } else { 6465 // This is the result value of the call. 6466 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6467 // Concatenate this output onto the outputs list. 6468 RetValRegs.append(OpInfo.AssignedRegs); 6469 } 6470 6471 // Add information to the INLINEASM node to know that this register is 6472 // set. 6473 OpInfo.AssignedRegs 6474 .AddInlineAsmOperands(OpInfo.isEarlyClobber 6475 ? InlineAsm::Kind_RegDefEarlyClobber 6476 : InlineAsm::Kind_RegDef, 6477 false, 0, DAG, AsmNodeOperands); 6478 break; 6479 } 6480 case InlineAsm::isInput: { 6481 SDValue InOperandVal = OpInfo.CallOperand; 6482 6483 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6484 // If this is required to match an output register we have already set, 6485 // just use its register. 6486 unsigned OperandNo = OpInfo.getMatchedOperand(); 6487 6488 // Scan until we find the definition we already emitted of this operand. 6489 // When we find it, create a RegsForValue operand. 6490 unsigned CurOp = InlineAsm::Op_FirstOperand; 6491 for (; OperandNo; --OperandNo) { 6492 // Advance to the next operand. 6493 unsigned OpFlag = 6494 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6495 assert((InlineAsm::isRegDefKind(OpFlag) || 6496 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6497 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6498 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6499 } 6500 6501 unsigned OpFlag = 6502 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6503 if (InlineAsm::isRegDefKind(OpFlag) || 6504 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6505 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6506 if (OpInfo.isIndirect) { 6507 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6508 LLVMContext &Ctx = *DAG.getContext(); 6509 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6510 " don't know how to handle tied " 6511 "indirect register inputs"); 6512 return; 6513 } 6514 6515 RegsForValue MatchedRegs; 6516 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6517 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType(); 6518 MatchedRegs.RegVTs.push_back(RegVT); 6519 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6520 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6521 i != e; ++i) { 6522 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT)) 6523 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC)); 6524 else { 6525 LLVMContext &Ctx = *DAG.getContext(); 6526 Ctx.emitError(CS.getInstruction(), 6527 "inline asm error: This value" 6528 " type register class is not natively supported!"); 6529 return; 6530 } 6531 } 6532 // Use the produced MatchedRegs object to 6533 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(), 6534 Chain, &Flag, CS.getInstruction()); 6535 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6536 true, OpInfo.getMatchedOperand(), 6537 DAG, AsmNodeOperands); 6538 break; 6539 } 6540 6541 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6542 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6543 "Unexpected number of operands"); 6544 // Add information to the INLINEASM node to know about this input. 6545 // See InlineAsm.h isUseOperandTiedToDef. 6546 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6547 OpInfo.getMatchedOperand()); 6548 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6549 TLI->getPointerTy())); 6550 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6551 break; 6552 } 6553 6554 // Treat indirect 'X' constraint as memory. 6555 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6556 OpInfo.isIndirect) 6557 OpInfo.ConstraintType = TargetLowering::C_Memory; 6558 6559 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6560 std::vector<SDValue> Ops; 6561 TLI->LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6562 Ops, DAG); 6563 if (Ops.empty()) { 6564 LLVMContext &Ctx = *DAG.getContext(); 6565 Ctx.emitError(CS.getInstruction(), 6566 "invalid operand for inline asm constraint '" + 6567 Twine(OpInfo.ConstraintCode) + "'"); 6568 return; 6569 } 6570 6571 // Add information to the INLINEASM node to know about this input. 6572 unsigned ResOpType = 6573 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6574 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6575 TLI->getPointerTy())); 6576 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6577 break; 6578 } 6579 6580 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6581 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6582 assert(InOperandVal.getValueType() == TLI->getPointerTy() && 6583 "Memory operands expect pointer values"); 6584 6585 // Add information to the INLINEASM node to know about this input. 6586 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6587 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6588 TLI->getPointerTy())); 6589 AsmNodeOperands.push_back(InOperandVal); 6590 break; 6591 } 6592 6593 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6594 OpInfo.ConstraintType == TargetLowering::C_Register) && 6595 "Unknown constraint type!"); 6596 6597 // TODO: Support this. 6598 if (OpInfo.isIndirect) { 6599 LLVMContext &Ctx = *DAG.getContext(); 6600 Ctx.emitError(CS.getInstruction(), 6601 "Don't know how to handle indirect register inputs yet " 6602 "for constraint '" + 6603 Twine(OpInfo.ConstraintCode) + "'"); 6604 return; 6605 } 6606 6607 // Copy the input into the appropriate registers. 6608 if (OpInfo.AssignedRegs.Regs.empty()) { 6609 LLVMContext &Ctx = *DAG.getContext(); 6610 Ctx.emitError(CS.getInstruction(), 6611 "couldn't allocate input reg for constraint '" + 6612 Twine(OpInfo.ConstraintCode) + "'"); 6613 return; 6614 } 6615 6616 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(), 6617 Chain, &Flag, CS.getInstruction()); 6618 6619 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6620 DAG, AsmNodeOperands); 6621 break; 6622 } 6623 case InlineAsm::isClobber: { 6624 // Add the clobbered value to the operand list, so that the register 6625 // allocator is aware that the physreg got clobbered. 6626 if (!OpInfo.AssignedRegs.Regs.empty()) 6627 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6628 false, 0, DAG, 6629 AsmNodeOperands); 6630 break; 6631 } 6632 } 6633 } 6634 6635 // Finish up input operands. Set the input chain and add the flag last. 6636 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6637 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6638 6639 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(), 6640 DAG.getVTList(MVT::Other, MVT::Glue), 6641 &AsmNodeOperands[0], AsmNodeOperands.size()); 6642 Flag = Chain.getValue(1); 6643 6644 // If this asm returns a register value, copy the result from that register 6645 // and set it as the value of the call. 6646 if (!RetValRegs.Regs.empty()) { 6647 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), 6648 Chain, &Flag, CS.getInstruction()); 6649 6650 // FIXME: Why don't we do this for inline asms with MRVs? 6651 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6652 EVT ResultType = TLI->getValueType(CS.getType()); 6653 6654 // If any of the results of the inline asm is a vector, it may have the 6655 // wrong width/num elts. This can happen for register classes that can 6656 // contain multiple different value types. The preg or vreg allocated may 6657 // not have the same VT as was expected. Convert it to the right type 6658 // with bit_convert. 6659 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6660 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(), 6661 ResultType, Val); 6662 6663 } else if (ResultType != Val.getValueType() && 6664 ResultType.isInteger() && Val.getValueType().isInteger()) { 6665 // If a result value was tied to an input value, the computed result may 6666 // have a wider width than the expected result. Extract the relevant 6667 // portion. 6668 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val); 6669 } 6670 6671 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6672 } 6673 6674 setValue(CS.getInstruction(), Val); 6675 // Don't need to use this as a chain in this case. 6676 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6677 return; 6678 } 6679 6680 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6681 6682 // Process indirect outputs, first output all of the flagged copies out of 6683 // physregs. 6684 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6685 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6686 const Value *Ptr = IndirectStoresToEmit[i].second; 6687 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), 6688 Chain, &Flag, IA); 6689 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6690 } 6691 6692 // Emit the non-flagged stores from the physregs. 6693 SmallVector<SDValue, 8> OutChains; 6694 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6695 SDValue Val = DAG.getStore(Chain, getCurSDLoc(), 6696 StoresToEmit[i].first, 6697 getValue(StoresToEmit[i].second), 6698 MachinePointerInfo(StoresToEmit[i].second), 6699 false, false, 0); 6700 OutChains.push_back(Val); 6701 } 6702 6703 if (!OutChains.empty()) 6704 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, 6705 &OutChains[0], OutChains.size()); 6706 6707 DAG.setRoot(Chain); 6708} 6709 6710void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6711 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(), 6712 MVT::Other, getRoot(), 6713 getValue(I.getArgOperand(0)), 6714 DAG.getSrcValue(I.getArgOperand(0)))); 6715} 6716 6717void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6718 const TargetLowering *TLI = TM.getTargetLowering(); 6719 const DataLayout &TD = *TLI->getDataLayout(); 6720 SDValue V = DAG.getVAArg(TLI->getValueType(I.getType()), getCurSDLoc(), 6721 getRoot(), getValue(I.getOperand(0)), 6722 DAG.getSrcValue(I.getOperand(0)), 6723 TD.getABITypeAlignment(I.getType())); 6724 setValue(&I, V); 6725 DAG.setRoot(V.getValue(1)); 6726} 6727 6728void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6729 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(), 6730 MVT::Other, getRoot(), 6731 getValue(I.getArgOperand(0)), 6732 DAG.getSrcValue(I.getArgOperand(0)))); 6733} 6734 6735void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6736 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(), 6737 MVT::Other, getRoot(), 6738 getValue(I.getArgOperand(0)), 6739 getValue(I.getArgOperand(1)), 6740 DAG.getSrcValue(I.getArgOperand(0)), 6741 DAG.getSrcValue(I.getArgOperand(1)))); 6742} 6743 6744/// \brief Lower an argument list according to the target calling convention. 6745/// 6746/// \return A tuple of <return-value, token-chain> 6747/// 6748/// This is a helper for lowering intrinsics that follow a target calling 6749/// convention or require stack pointer adjustment. Only a subset of the 6750/// intrinsic's operands need to participate in the calling convention. 6751std::pair<SDValue, SDValue> 6752SelectionDAGBuilder::LowerCallOperands(const CallInst &CI, unsigned ArgIdx, 6753 unsigned NumArgs, SDValue Callee, 6754 bool useVoidTy) { 6755 TargetLowering::ArgListTy Args; 6756 Args.reserve(NumArgs); 6757 6758 // Populate the argument list. 6759 // Attributes for args start at offset 1, after the return attribute. 6760 ImmutableCallSite CS(&CI); 6761 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1; 6762 ArgI != ArgE; ++ArgI) { 6763 const Value *V = CI.getOperand(ArgI); 6764 6765 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic."); 6766 6767 TargetLowering::ArgListEntry Entry; 6768 Entry.Node = getValue(V); 6769 Entry.Ty = V->getType(); 6770 Entry.setAttributes(&CS, AttrI); 6771 Args.push_back(Entry); 6772 } 6773 6774 Type *retTy = useVoidTy ? Type::getVoidTy(*DAG.getContext()) : CI.getType(); 6775 TargetLowering::CallLoweringInfo CLI(getRoot(), retTy, /*retSExt*/ false, 6776 /*retZExt*/ false, /*isVarArg*/ false, /*isInReg*/ false, NumArgs, 6777 CI.getCallingConv(), /*isTailCall*/ false, /*doesNotReturn*/ false, 6778 /*isReturnValueUsed*/ CI.use_empty(), Callee, Args, DAG, getCurSDLoc()); 6779 6780 const TargetLowering *TLI = TM.getTargetLowering(); 6781 return TLI->LowerCallTo(CLI); 6782} 6783 6784/// \brief Lower llvm.experimental.stackmap directly to its target opcode. 6785void SelectionDAGBuilder::visitStackmap(const CallInst &CI) { 6786 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>, 6787 // [live variables...]) 6788 6789 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value."); 6790 6791 SDValue Callee = getValue(CI.getCalledValue()); 6792 6793 // Lower into a call sequence with no args and no return value. 6794 std::pair<SDValue, SDValue> Result = LowerCallOperands(CI, 0, 0, Callee); 6795 // Set the root to the target-lowered call chain. 6796 SDValue Chain = Result.second; 6797 DAG.setRoot(Chain); 6798 6799 /// Get a call instruction from the call sequence chain. 6800 /// Tail calls are not allowed. 6801 SDNode *CallEnd = Chain.getNode(); 6802 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END && 6803 "Expected a callseq node."); 6804 SDNode *Call = CallEnd->getOperand(0).getNode(); 6805 bool hasGlue = Call->getGluedNode(); 6806 6807 // Replace the target specific call node with the stackmap intrinsic. 6808 SmallVector<SDValue, 8> Ops; 6809 6810 // Add the <id> and <numShadowBytes> constants. 6811 for (unsigned i = 0; i < 2; ++i) { 6812 SDValue tmp = getValue(CI.getOperand(i)); 6813 Ops.push_back(DAG.getTargetConstant( 6814 cast<ConstantSDNode>(tmp)->getZExtValue(), MVT::i32)); 6815 } 6816 // Push live variables for the stack map. 6817 for (unsigned i = 2, e = CI.getNumArgOperands(); i != e; ++i) 6818 Ops.push_back(getValue(CI.getArgOperand(i))); 6819 6820 // Push the chain (this is originally the first operand of the call, but 6821 // becomes now the last or second to last operand). 6822 Ops.push_back(*(Call->op_begin())); 6823 6824 // Push the glue flag (last operand). 6825 if (hasGlue) 6826 Ops.push_back(*(Call->op_end()-1)); 6827 6828 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 6829 6830 // Replace the target specific call node with a STACKMAP node. 6831 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::STACKMAP, getCurSDLoc(), 6832 NodeTys, Ops); 6833 6834 // StackMap generates no value, so nothing goes in the NodeMap. 6835 6836 // Fixup the consumers of the intrinsic. The chain and glue may be used in the 6837 // call sequence. 6838 DAG.ReplaceAllUsesWith(Call, MN); 6839 6840 DAG.DeleteNode(Call); 6841} 6842 6843/// \brief Lower llvm.experimental.patchpoint directly to its target opcode. 6844void SelectionDAGBuilder::visitPatchpoint(const CallInst &CI) { 6845 // void|i64 @llvm.experimental.patchpoint.void|i64(i32 <id>, 6846 // i32 <numBytes>, 6847 // i8* <target>, 6848 // i32 <numArgs>, 6849 // [Args...], 6850 // [live variables...]) 6851 6852 CallingConv::ID CC = CI.getCallingConv(); 6853 bool isAnyRegCC = CC == CallingConv::AnyReg; 6854 bool hasDef = !CI.getType()->isVoidTy(); 6855 SDValue Callee = getValue(CI.getOperand(2)); // <target> 6856 6857 // Get the real number of arguments participating in the call <numArgs> 6858 unsigned NumArgs = 6859 cast<ConstantSDNode>(getValue(CI.getArgOperand(3)))->getZExtValue(); 6860 6861 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs> 6862 assert(CI.getNumArgOperands() >= NumArgs + 4 && 6863 "Not enough arguments provided to the patchpoint intrinsic"); 6864 6865 // For AnyRegCC the arguments are lowered later on manually. 6866 unsigned NumCallArgs = isAnyRegCC ? 0 : NumArgs; 6867 std::pair<SDValue, SDValue> Result = 6868 LowerCallOperands(CI, 4, NumCallArgs, Callee, isAnyRegCC); 6869 6870 // Set the root to the target-lowered call chain. 6871 SDValue Chain = Result.second; 6872 DAG.setRoot(Chain); 6873 6874 SDNode *CallEnd = Chain.getNode(); 6875 if (hasDef && (CallEnd->getOpcode() == ISD::CopyFromReg)) 6876 CallEnd = CallEnd->getOperand(0).getNode(); 6877 6878 /// Get a call instruction from the call sequence chain. 6879 /// Tail calls are not allowed. 6880 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END && 6881 "Expected a callseq node."); 6882 SDNode *Call = CallEnd->getOperand(0).getNode(); 6883 bool hasGlue = Call->getGluedNode(); 6884 6885 // Replace the target specific call node with the patchable intrinsic. 6886 SmallVector<SDValue, 8> Ops; 6887 6888 // Add the <id> and <numNopBytes> constants. 6889 for (unsigned i = 0; i < 2; ++i) { 6890 SDValue tmp = getValue(CI.getOperand(i)); 6891 Ops.push_back(DAG.getTargetConstant( 6892 cast<ConstantSDNode>(tmp)->getZExtValue(), MVT::i32)); 6893 } 6894 // Assume that the Callee is a constant address. 6895 Ops.push_back( 6896 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(), 6897 /*isTarget=*/true)); 6898 6899 // Adjust <numArgs> to account for any arguments that have been passed on the 6900 // stack instead. 6901 // Call Node: Chain, Target, {Args}, RegMask, [Glue] 6902 unsigned NumCallRegArgs = Call->getNumOperands() - (hasGlue ? 4 : 3); 6903 NumCallRegArgs = isAnyRegCC ? NumArgs : NumCallRegArgs; 6904 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32)); 6905 6906 // Add the calling convention 6907 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32)); 6908 6909 // Add the arguments we omitted previously. The register allocator should 6910 // place these in any free register. 6911 if (isAnyRegCC) 6912 for (unsigned i = 4, e = NumArgs + 4; i != e; ++i) 6913 Ops.push_back(getValue(CI.getArgOperand(i))); 6914 6915 // Push the arguments from the call instruction. 6916 SDNode::op_iterator e = hasGlue ? Call->op_end()-2 : Call->op_end()-1; 6917 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i) 6918 Ops.push_back(*i); 6919 6920 // Push live variables for the stack map. 6921 for (unsigned i = NumArgs + 4, e = CI.getNumArgOperands(); i != e; ++i) { 6922 SDValue OpVal = getValue(CI.getArgOperand(i)); 6923 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) { 6924 Ops.push_back( 6925 DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64)); 6926 Ops.push_back( 6927 DAG.getTargetConstant(C->getSExtValue(), MVT::i64)); 6928 } else 6929 Ops.push_back(OpVal); 6930 } 6931 6932 // Push the register mask info. 6933 if (hasGlue) 6934 Ops.push_back(*(Call->op_end()-2)); 6935 else 6936 Ops.push_back(*(Call->op_end()-1)); 6937 6938 // Push the chain (this is originally the first operand of the call, but 6939 // becomes now the last or second to last operand). 6940 Ops.push_back(*(Call->op_begin())); 6941 6942 // Push the glue flag (last operand). 6943 if (hasGlue) 6944 Ops.push_back(*(Call->op_end()-1)); 6945 6946 SDVTList NodeTys; 6947 if (isAnyRegCC && hasDef) { 6948 // Create the return types based on the intrinsic definition 6949 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6950 SmallVector<EVT, 3> ValueVTs; 6951 ComputeValueVTs(TLI, CI.getType(), ValueVTs); 6952 assert(ValueVTs.size() == 1 && "Expected only one return value type."); 6953 6954 // There is always a chain and a glue type at the end 6955 ValueVTs.push_back(MVT::Other); 6956 ValueVTs.push_back(MVT::Glue); 6957 NodeTys = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 6958 } else 6959 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 6960 6961 // Replace the target specific call node with a PATCHPOINT node. 6962 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT, 6963 getCurSDLoc(), NodeTys, Ops); 6964 6965 // Update the NodeMap. 6966 if (hasDef) { 6967 if (isAnyRegCC) 6968 setValue(&CI, SDValue(MN, 0)); 6969 else 6970 setValue(&CI, Result.first); 6971 } 6972 6973 // Fixup the consumers of the intrinsic. The chain and glue may be used in the 6974 // call sequence. Furthermore the location of the chain and glue can change 6975 // when the AnyReg calling convention is used and the intrinsic returns a 6976 // value. 6977 if (isAnyRegCC && hasDef) { 6978 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)}; 6979 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)}; 6980 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 6981 } else 6982 DAG.ReplaceAllUsesWith(Call, MN); 6983 DAG.DeleteNode(Call); 6984} 6985 6986/// TargetLowering::LowerCallTo - This is the default LowerCallTo 6987/// implementation, which just calls LowerCall. 6988/// FIXME: When all targets are 6989/// migrated to using LowerCall, this hook should be integrated into SDISel. 6990std::pair<SDValue, SDValue> 6991TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { 6992 // Handle the incoming return values from the call. 6993 CLI.Ins.clear(); 6994 SmallVector<EVT, 4> RetTys; 6995 ComputeValueVTs(*this, CLI.RetTy, RetTys); 6996 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6997 EVT VT = RetTys[I]; 6998 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 6999 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 7000 for (unsigned i = 0; i != NumRegs; ++i) { 7001 ISD::InputArg MyFlags; 7002 MyFlags.VT = RegisterVT; 7003 MyFlags.ArgVT = VT; 7004 MyFlags.Used = CLI.IsReturnValueUsed; 7005 if (CLI.RetSExt) 7006 MyFlags.Flags.setSExt(); 7007 if (CLI.RetZExt) 7008 MyFlags.Flags.setZExt(); 7009 if (CLI.IsInReg) 7010 MyFlags.Flags.setInReg(); 7011 CLI.Ins.push_back(MyFlags); 7012 } 7013 } 7014 7015 // Handle all of the outgoing arguments. 7016 CLI.Outs.clear(); 7017 CLI.OutVals.clear(); 7018 ArgListTy &Args = CLI.Args; 7019 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 7020 SmallVector<EVT, 4> ValueVTs; 7021 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 7022 for (unsigned Value = 0, NumValues = ValueVTs.size(); 7023 Value != NumValues; ++Value) { 7024 EVT VT = ValueVTs[Value]; 7025 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext()); 7026 SDValue Op = SDValue(Args[i].Node.getNode(), 7027 Args[i].Node.getResNo() + Value); 7028 ISD::ArgFlagsTy Flags; 7029 unsigned OriginalAlignment = 7030 getDataLayout()->getABITypeAlignment(ArgTy); 7031 7032 if (Args[i].isZExt) 7033 Flags.setZExt(); 7034 if (Args[i].isSExt) 7035 Flags.setSExt(); 7036 if (Args[i].isInReg) 7037 Flags.setInReg(); 7038 if (Args[i].isSRet) 7039 Flags.setSRet(); 7040 if (Args[i].isByVal) { 7041 Flags.setByVal(); 7042 PointerType *Ty = cast<PointerType>(Args[i].Ty); 7043 Type *ElementTy = Ty->getElementType(); 7044 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy)); 7045 // For ByVal, alignment should come from FE. BE will guess if this 7046 // info is not there but there are cases it cannot get right. 7047 unsigned FrameAlign; 7048 if (Args[i].Alignment) 7049 FrameAlign = Args[i].Alignment; 7050 else 7051 FrameAlign = getByValTypeAlignment(ElementTy); 7052 Flags.setByValAlign(FrameAlign); 7053 } 7054 if (Args[i].isNest) 7055 Flags.setNest(); 7056 Flags.setOrigAlign(OriginalAlignment); 7057 7058 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT); 7059 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT); 7060 SmallVector<SDValue, 4> Parts(NumParts); 7061 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 7062 7063 if (Args[i].isSExt) 7064 ExtendKind = ISD::SIGN_EXTEND; 7065 else if (Args[i].isZExt) 7066 ExtendKind = ISD::ZERO_EXTEND; 7067 7068 // Conservatively only handle 'returned' on non-vectors for now 7069 if (Args[i].isReturned && !Op.getValueType().isVector()) { 7070 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues && 7071 "unexpected use of 'returned'"); 7072 // Before passing 'returned' to the target lowering code, ensure that 7073 // either the register MVT and the actual EVT are the same size or that 7074 // the return value and argument are extended in the same way; in these 7075 // cases it's safe to pass the argument register value unchanged as the 7076 // return register value (although it's at the target's option whether 7077 // to do so) 7078 // TODO: allow code generation to take advantage of partially preserved 7079 // registers rather than clobbering the entire register when the 7080 // parameter extension method is not compatible with the return 7081 // extension method 7082 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) || 7083 (ExtendKind != ISD::ANY_EXTEND && 7084 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt)) 7085 Flags.setReturned(); 7086 } 7087 7088 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, 7089 PartVT, CLI.CS ? CLI.CS->getInstruction() : 0, ExtendKind); 7090 7091 for (unsigned j = 0; j != NumParts; ++j) { 7092 // if it isn't first piece, alignment must be 1 7093 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT, 7094 i < CLI.NumFixedArgs, 7095 i, j*Parts[j].getValueType().getStoreSize()); 7096 if (NumParts > 1 && j == 0) 7097 MyFlags.Flags.setSplit(); 7098 else if (j != 0) 7099 MyFlags.Flags.setOrigAlign(1); 7100 7101 CLI.Outs.push_back(MyFlags); 7102 CLI.OutVals.push_back(Parts[j]); 7103 } 7104 } 7105 } 7106 7107 SmallVector<SDValue, 4> InVals; 7108 CLI.Chain = LowerCall(CLI, InVals); 7109 7110 // Verify that the target's LowerCall behaved as expected. 7111 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other && 7112 "LowerCall didn't return a valid chain!"); 7113 assert((!CLI.IsTailCall || InVals.empty()) && 7114 "LowerCall emitted a return value for a tail call!"); 7115 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) && 7116 "LowerCall didn't emit the correct number of values!"); 7117 7118 // For a tail call, the return value is merely live-out and there aren't 7119 // any nodes in the DAG representing it. Return a special value to 7120 // indicate that a tail call has been emitted and no more Instructions 7121 // should be processed in the current block. 7122 if (CLI.IsTailCall) { 7123 CLI.DAG.setRoot(CLI.Chain); 7124 return std::make_pair(SDValue(), SDValue()); 7125 } 7126 7127 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) { 7128 assert(InVals[i].getNode() && 7129 "LowerCall emitted a null value!"); 7130 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() && 7131 "LowerCall emitted a value with the wrong type!"); 7132 }); 7133 7134 // Collect the legal value parts into potentially illegal values 7135 // that correspond to the original function's return values. 7136 ISD::NodeType AssertOp = ISD::DELETED_NODE; 7137 if (CLI.RetSExt) 7138 AssertOp = ISD::AssertSext; 7139 else if (CLI.RetZExt) 7140 AssertOp = ISD::AssertZext; 7141 SmallVector<SDValue, 4> ReturnValues; 7142 unsigned CurReg = 0; 7143 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 7144 EVT VT = RetTys[I]; 7145 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT); 7146 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); 7147 7148 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg], 7149 NumRegs, RegisterVT, VT, NULL, 7150 AssertOp)); 7151 CurReg += NumRegs; 7152 } 7153 7154 // For a function returning void, there is no return value. We can't create 7155 // such a node, so we just return a null return value in that case. In 7156 // that case, nothing will actually look at the value. 7157 if (ReturnValues.empty()) 7158 return std::make_pair(SDValue(), CLI.Chain); 7159 7160 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, 7161 CLI.DAG.getVTList(&RetTys[0], RetTys.size()), 7162 &ReturnValues[0], ReturnValues.size()); 7163 return std::make_pair(Res, CLI.Chain); 7164} 7165 7166void TargetLowering::LowerOperationWrapper(SDNode *N, 7167 SmallVectorImpl<SDValue> &Results, 7168 SelectionDAG &DAG) const { 7169 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 7170 if (Res.getNode()) 7171 Results.push_back(Res); 7172} 7173 7174SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 7175 llvm_unreachable("LowerOperation not implemented for this target!"); 7176} 7177 7178void 7179SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 7180 SDValue Op = getNonRegisterValue(V); 7181 assert((Op.getOpcode() != ISD::CopyFromReg || 7182 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 7183 "Copy from a reg to the same reg!"); 7184 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 7185 7186 const TargetLowering *TLI = TM.getTargetLowering(); 7187 RegsForValue RFV(V->getContext(), *TLI, Reg, V->getType()); 7188 SDValue Chain = DAG.getEntryNode(); 7189 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, 0, V); 7190 PendingExports.push_back(Chain); 7191} 7192 7193#include "llvm/CodeGen/SelectionDAGISel.h" 7194 7195/// isOnlyUsedInEntryBlock - If the specified argument is only used in the 7196/// entry block, return true. This includes arguments used by switches, since 7197/// the switch may expand into multiple basic blocks. 7198static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) { 7199 // With FastISel active, we may be splitting blocks, so force creation 7200 // of virtual registers for all non-dead arguments. 7201 if (FastISel) 7202 return A->use_empty(); 7203 7204 const BasicBlock *Entry = A->getParent()->begin(); 7205 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 7206 UI != E; ++UI) { 7207 const User *U = *UI; 7208 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 7209 return false; // Use not in entry block. 7210 } 7211 return true; 7212} 7213 7214void SelectionDAGISel::LowerArguments(const Function &F) { 7215 SelectionDAG &DAG = SDB->DAG; 7216 SDLoc dl = SDB->getCurSDLoc(); 7217 const TargetLowering *TLI = getTargetLowering(); 7218 const DataLayout *TD = TLI->getDataLayout(); 7219 SmallVector<ISD::InputArg, 16> Ins; 7220 7221 if (!FuncInfo->CanLowerReturn) { 7222 // Put in an sret pointer parameter before all the other parameters. 7223 SmallVector<EVT, 1> ValueVTs; 7224 ComputeValueVTs(*getTargetLowering(), 7225 PointerType::getUnqual(F.getReturnType()), ValueVTs); 7226 7227 // NOTE: Assuming that a pointer will never break down to more than one VT 7228 // or one register. 7229 ISD::ArgFlagsTy Flags; 7230 Flags.setSRet(); 7231 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]); 7232 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0); 7233 Ins.push_back(RetArg); 7234 } 7235 7236 // Set up the incoming argument description vector. 7237 unsigned Idx = 1; 7238 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 7239 I != E; ++I, ++Idx) { 7240 SmallVector<EVT, 4> ValueVTs; 7241 ComputeValueVTs(*TLI, I->getType(), ValueVTs); 7242 bool isArgValueUsed = !I->use_empty(); 7243 unsigned PartBase = 0; 7244 for (unsigned Value = 0, NumValues = ValueVTs.size(); 7245 Value != NumValues; ++Value) { 7246 EVT VT = ValueVTs[Value]; 7247 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 7248 ISD::ArgFlagsTy Flags; 7249 unsigned OriginalAlignment = 7250 TD->getABITypeAlignment(ArgTy); 7251 7252 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt)) 7253 Flags.setZExt(); 7254 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt)) 7255 Flags.setSExt(); 7256 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg)) 7257 Flags.setInReg(); 7258 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet)) 7259 Flags.setSRet(); 7260 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal)) { 7261 Flags.setByVal(); 7262 PointerType *Ty = cast<PointerType>(I->getType()); 7263 Type *ElementTy = Ty->getElementType(); 7264 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 7265 // For ByVal, alignment should be passed from FE. BE will guess if 7266 // this info is not there but there are cases it cannot get right. 7267 unsigned FrameAlign; 7268 if (F.getParamAlignment(Idx)) 7269 FrameAlign = F.getParamAlignment(Idx); 7270 else 7271 FrameAlign = TLI->getByValTypeAlignment(ElementTy); 7272 Flags.setByValAlign(FrameAlign); 7273 } 7274 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest)) 7275 Flags.setNest(); 7276 Flags.setOrigAlign(OriginalAlignment); 7277 7278 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT); 7279 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT); 7280 for (unsigned i = 0; i != NumRegs; ++i) { 7281 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed, 7282 Idx-1, PartBase+i*RegisterVT.getStoreSize()); 7283 if (NumRegs > 1 && i == 0) 7284 MyFlags.Flags.setSplit(); 7285 // if it isn't first piece, alignment must be 1 7286 else if (i > 0) 7287 MyFlags.Flags.setOrigAlign(1); 7288 Ins.push_back(MyFlags); 7289 } 7290 PartBase += VT.getStoreSize(); 7291 } 7292 } 7293 7294 // Call the target to set up the argument values. 7295 SmallVector<SDValue, 8> InVals; 7296 SDValue NewRoot = TLI->LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 7297 F.isVarArg(), Ins, 7298 dl, DAG, InVals); 7299 7300 // Verify that the target's LowerFormalArguments behaved as expected. 7301 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 7302 "LowerFormalArguments didn't return a valid chain!"); 7303 assert(InVals.size() == Ins.size() && 7304 "LowerFormalArguments didn't emit the correct number of values!"); 7305 DEBUG({ 7306 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 7307 assert(InVals[i].getNode() && 7308 "LowerFormalArguments emitted a null value!"); 7309 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 7310 "LowerFormalArguments emitted a value with the wrong type!"); 7311 } 7312 }); 7313 7314 // Update the DAG with the new chain value resulting from argument lowering. 7315 DAG.setRoot(NewRoot); 7316 7317 // Set up the argument values. 7318 unsigned i = 0; 7319 Idx = 1; 7320 if (!FuncInfo->CanLowerReturn) { 7321 // Create a virtual register for the sret pointer, and put in a copy 7322 // from the sret argument into it. 7323 SmallVector<EVT, 1> ValueVTs; 7324 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 7325 MVT VT = ValueVTs[0].getSimpleVT(); 7326 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT); 7327 ISD::NodeType AssertOp = ISD::DELETED_NODE; 7328 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 7329 RegVT, VT, NULL, AssertOp); 7330 7331 MachineFunction& MF = SDB->DAG.getMachineFunction(); 7332 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 7333 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT)); 7334 FuncInfo->DemoteRegister = SRetReg; 7335 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), 7336 SRetReg, ArgValue); 7337 DAG.setRoot(NewRoot); 7338 7339 // i indexes lowered arguments. Bump it past the hidden sret argument. 7340 // Idx indexes LLVM arguments. Don't touch it. 7341 ++i; 7342 } 7343 7344 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 7345 ++I, ++Idx) { 7346 SmallVector<SDValue, 4> ArgValues; 7347 SmallVector<EVT, 4> ValueVTs; 7348 ComputeValueVTs(*TLI, I->getType(), ValueVTs); 7349 unsigned NumValues = ValueVTs.size(); 7350 7351 // If this argument is unused then remember its value. It is used to generate 7352 // debugging information. 7353 if (I->use_empty() && NumValues) { 7354 SDB->setUnusedArgValue(I, InVals[i]); 7355 7356 // Also remember any frame index for use in FastISel. 7357 if (FrameIndexSDNode *FI = 7358 dyn_cast<FrameIndexSDNode>(InVals[i].getNode())) 7359 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 7360 } 7361 7362 for (unsigned Val = 0; Val != NumValues; ++Val) { 7363 EVT VT = ValueVTs[Val]; 7364 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT); 7365 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT); 7366 7367 if (!I->use_empty()) { 7368 ISD::NodeType AssertOp = ISD::DELETED_NODE; 7369 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt)) 7370 AssertOp = ISD::AssertSext; 7371 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt)) 7372 AssertOp = ISD::AssertZext; 7373 7374 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 7375 NumParts, PartVT, VT, 7376 NULL, AssertOp)); 7377 } 7378 7379 i += NumParts; 7380 } 7381 7382 // We don't need to do anything else for unused arguments. 7383 if (ArgValues.empty()) 7384 continue; 7385 7386 // Note down frame index. 7387 if (FrameIndexSDNode *FI = 7388 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 7389 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 7390 7391 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 7392 SDB->getCurSDLoc()); 7393 7394 SDB->setValue(I, Res); 7395 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 7396 if (LoadSDNode *LNode = 7397 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 7398 if (FrameIndexSDNode *FI = 7399 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 7400 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 7401 } 7402 7403 // If this argument is live outside of the entry block, insert a copy from 7404 // wherever we got it to the vreg that other BB's will reference it as. 7405 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 7406 // If we can, though, try to skip creating an unnecessary vreg. 7407 // FIXME: This isn't very clean... it would be nice to make this more 7408 // general. It's also subtly incompatible with the hacks FastISel 7409 // uses with vregs. 7410 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 7411 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 7412 FuncInfo->ValueMap[I] = Reg; 7413 continue; 7414 } 7415 } 7416 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) { 7417 FuncInfo->InitializeRegForValue(I); 7418 SDB->CopyToExportRegsIfNeeded(I); 7419 } 7420 } 7421 7422 assert(i == InVals.size() && "Argument register count mismatch!"); 7423 7424 // Finally, if the target has anything special to do, allow it to do so. 7425 // FIXME: this should insert code into the DAG! 7426 EmitFunctionEntryCode(); 7427} 7428 7429/// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 7430/// ensure constants are generated when needed. Remember the virtual registers 7431/// that need to be added to the Machine PHI nodes as input. We cannot just 7432/// directly add them, because expansion might result in multiple MBB's for one 7433/// BB. As such, the start of the BB might correspond to a different MBB than 7434/// the end. 7435/// 7436void 7437SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 7438 const TerminatorInst *TI = LLVMBB->getTerminator(); 7439 7440 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 7441 7442 // Check successor nodes' PHI nodes that expect a constant to be available 7443 // from this block. 7444 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 7445 const BasicBlock *SuccBB = TI->getSuccessor(succ); 7446 if (!isa<PHINode>(SuccBB->begin())) continue; 7447 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 7448 7449 // If this terminator has multiple identical successors (common for 7450 // switches), only handle each succ once. 7451 if (!SuccsHandled.insert(SuccMBB)) continue; 7452 7453 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 7454 7455 // At this point we know that there is a 1-1 correspondence between LLVM PHI 7456 // nodes and Machine PHI nodes, but the incoming operands have not been 7457 // emitted yet. 7458 for (BasicBlock::const_iterator I = SuccBB->begin(); 7459 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 7460 // Ignore dead phi's. 7461 if (PN->use_empty()) continue; 7462 7463 // Skip empty types 7464 if (PN->getType()->isEmptyTy()) 7465 continue; 7466 7467 unsigned Reg; 7468 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 7469 7470 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 7471 unsigned &RegOut = ConstantsOut[C]; 7472 if (RegOut == 0) { 7473 RegOut = FuncInfo.CreateRegs(C->getType()); 7474 CopyValueToVirtualRegister(C, RegOut); 7475 } 7476 Reg = RegOut; 7477 } else { 7478 DenseMap<const Value *, unsigned>::iterator I = 7479 FuncInfo.ValueMap.find(PHIOp); 7480 if (I != FuncInfo.ValueMap.end()) 7481 Reg = I->second; 7482 else { 7483 assert(isa<AllocaInst>(PHIOp) && 7484 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 7485 "Didn't codegen value into a register!??"); 7486 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 7487 CopyValueToVirtualRegister(PHIOp, Reg); 7488 } 7489 } 7490 7491 // Remember that this register needs to added to the machine PHI node as 7492 // the input for this MBB. 7493 SmallVector<EVT, 4> ValueVTs; 7494 const TargetLowering *TLI = TM.getTargetLowering(); 7495 ComputeValueVTs(*TLI, PN->getType(), ValueVTs); 7496 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 7497 EVT VT = ValueVTs[vti]; 7498 unsigned NumRegisters = TLI->getNumRegisters(*DAG.getContext(), VT); 7499 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 7500 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 7501 Reg += NumRegisters; 7502 } 7503 } 7504 } 7505 7506 ConstantsOut.clear(); 7507} 7508 7509/// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB 7510/// is 0. 7511MachineBasicBlock * 7512SelectionDAGBuilder::StackProtectorDescriptor:: 7513AddSuccessorMBB(const BasicBlock *BB, 7514 MachineBasicBlock *ParentMBB, 7515 MachineBasicBlock *SuccMBB) { 7516 // If SuccBB has not been created yet, create it. 7517 if (!SuccMBB) { 7518 MachineFunction *MF = ParentMBB->getParent(); 7519 MachineFunction::iterator BBI = ParentMBB; 7520 SuccMBB = MF->CreateMachineBasicBlock(BB); 7521 MF->insert(++BBI, SuccMBB); 7522 } 7523 // Add it as a successor of ParentMBB. 7524 ParentMBB->addSuccessor(SuccMBB); 7525 return SuccMBB; 7526} 7527