1//===-- TailDuplication.cpp - Duplicate blocks into predecessors' tails ---===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This pass duplicates basic blocks ending in unconditional branches into
11// the tails of their predecessors.
12//
13//===----------------------------------------------------------------------===//
14
15#include "llvm/CodeGen/Passes.h"
16#include "llvm/ADT/DenseSet.h"
17#include "llvm/ADT/SetVector.h"
18#include "llvm/ADT/SmallSet.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
21#include "llvm/CodeGen/MachineFunctionPass.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineModuleInfo.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/MachineSSAUpdater.h"
26#include "llvm/CodeGen/RegisterScavenging.h"
27#include "llvm/IR/Function.h"
28#include "llvm/Support/CommandLine.h"
29#include "llvm/Support/Debug.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Support/raw_ostream.h"
32#include "llvm/Target/TargetInstrInfo.h"
33#include "llvm/Target/TargetRegisterInfo.h"
34using namespace llvm;
35
36#define DEBUG_TYPE "tailduplication"
37
38STATISTIC(NumTails     , "Number of tails duplicated");
39STATISTIC(NumTailDups  , "Number of tail duplicated blocks");
40STATISTIC(NumInstrDups , "Additional instructions due to tail duplication");
41STATISTIC(NumDeadBlocks, "Number of dead blocks removed");
42STATISTIC(NumAddedPHIs , "Number of phis added");
43
44// Heuristic for tail duplication.
45static cl::opt<unsigned>
46TailDuplicateSize("tail-dup-size",
47                  cl::desc("Maximum instructions to consider tail duplicating"),
48                  cl::init(2), cl::Hidden);
49
50static cl::opt<bool>
51TailDupVerify("tail-dup-verify",
52              cl::desc("Verify sanity of PHI instructions during taildup"),
53              cl::init(false), cl::Hidden);
54
55static cl::opt<unsigned>
56TailDupLimit("tail-dup-limit", cl::init(~0U), cl::Hidden);
57
58typedef std::vector<std::pair<MachineBasicBlock*,unsigned> > AvailableValsTy;
59
60namespace {
61  /// TailDuplicatePass - Perform tail duplication.
62  class TailDuplicatePass : public MachineFunctionPass {
63    const TargetInstrInfo *TII;
64    const TargetRegisterInfo *TRI;
65    const MachineBranchProbabilityInfo *MBPI;
66    MachineModuleInfo *MMI;
67    MachineRegisterInfo *MRI;
68    std::unique_ptr<RegScavenger> RS;
69    bool PreRegAlloc;
70
71    // SSAUpdateVRs - A list of virtual registers for which to update SSA form.
72    SmallVector<unsigned, 16> SSAUpdateVRs;
73
74    // SSAUpdateVals - For each virtual register in SSAUpdateVals keep a list of
75    // source virtual registers.
76    DenseMap<unsigned, AvailableValsTy> SSAUpdateVals;
77
78  public:
79    static char ID;
80    explicit TailDuplicatePass() :
81      MachineFunctionPass(ID), PreRegAlloc(false) {}
82
83    bool runOnMachineFunction(MachineFunction &MF) override;
84
85    void getAnalysisUsage(AnalysisUsage &AU) const override;
86
87  private:
88    void AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
89                           MachineBasicBlock *BB);
90    void ProcessPHI(MachineInstr *MI, MachineBasicBlock *TailBB,
91                    MachineBasicBlock *PredBB,
92                    DenseMap<unsigned, unsigned> &LocalVRMap,
93                    SmallVectorImpl<std::pair<unsigned,unsigned> > &Copies,
94                    const DenseSet<unsigned> &UsedByPhi,
95                    bool Remove);
96    void DuplicateInstruction(MachineInstr *MI,
97                              MachineBasicBlock *TailBB,
98                              MachineBasicBlock *PredBB,
99                              MachineFunction &MF,
100                              DenseMap<unsigned, unsigned> &LocalVRMap,
101                              const DenseSet<unsigned> &UsedByPhi);
102    void UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead,
103                              SmallVectorImpl<MachineBasicBlock *> &TDBBs,
104                              SmallSetVector<MachineBasicBlock*, 8> &Succs);
105    bool TailDuplicateBlocks(MachineFunction &MF);
106    bool shouldTailDuplicate(const MachineFunction &MF,
107                             bool IsSimple, MachineBasicBlock &TailBB);
108    bool isSimpleBB(MachineBasicBlock *TailBB);
109    bool canCompletelyDuplicateBB(MachineBasicBlock &BB);
110    bool duplicateSimpleBB(MachineBasicBlock *TailBB,
111                           SmallVectorImpl<MachineBasicBlock *> &TDBBs,
112                           const DenseSet<unsigned> &RegsUsedByPhi,
113                           SmallVectorImpl<MachineInstr *> &Copies);
114    bool TailDuplicate(MachineBasicBlock *TailBB,
115                       bool IsSimple,
116                       MachineFunction &MF,
117                       SmallVectorImpl<MachineBasicBlock *> &TDBBs,
118                       SmallVectorImpl<MachineInstr *> &Copies);
119    bool TailDuplicateAndUpdate(MachineBasicBlock *MBB,
120                                bool IsSimple,
121                                MachineFunction &MF);
122
123    void RemoveDeadBlock(MachineBasicBlock *MBB);
124  };
125
126  char TailDuplicatePass::ID = 0;
127}
128
129char &llvm::TailDuplicateID = TailDuplicatePass::ID;
130
131INITIALIZE_PASS(TailDuplicatePass, "tailduplication", "Tail Duplication",
132                false, false)
133
134bool TailDuplicatePass::runOnMachineFunction(MachineFunction &MF) {
135  if (skipOptnoneFunction(*MF.getFunction()))
136    return false;
137
138  TII = MF.getTarget().getInstrInfo();
139  TRI = MF.getTarget().getRegisterInfo();
140  MRI = &MF.getRegInfo();
141  MMI = getAnalysisIfAvailable<MachineModuleInfo>();
142  MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
143
144  PreRegAlloc = MRI->isSSA();
145  RS.reset();
146  if (MRI->tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF))
147    RS.reset(new RegScavenger());
148
149  bool MadeChange = false;
150  while (TailDuplicateBlocks(MF))
151    MadeChange = true;
152
153  return MadeChange;
154}
155
156void TailDuplicatePass::getAnalysisUsage(AnalysisUsage &AU) const {
157  AU.addRequired<MachineBranchProbabilityInfo>();
158  MachineFunctionPass::getAnalysisUsage(AU);
159}
160
161static void VerifyPHIs(MachineFunction &MF, bool CheckExtra) {
162  for (MachineFunction::iterator I = ++MF.begin(), E = MF.end(); I != E; ++I) {
163    MachineBasicBlock *MBB = I;
164    SmallSetVector<MachineBasicBlock*, 8> Preds(MBB->pred_begin(),
165                                                MBB->pred_end());
166    MachineBasicBlock::iterator MI = MBB->begin();
167    while (MI != MBB->end()) {
168      if (!MI->isPHI())
169        break;
170      for (SmallSetVector<MachineBasicBlock *, 8>::iterator PI = Preds.begin(),
171             PE = Preds.end(); PI != PE; ++PI) {
172        MachineBasicBlock *PredBB = *PI;
173        bool Found = false;
174        for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
175          MachineBasicBlock *PHIBB = MI->getOperand(i+1).getMBB();
176          if (PHIBB == PredBB) {
177            Found = true;
178            break;
179          }
180        }
181        if (!Found) {
182          dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
183          dbgs() << "  missing input from predecessor BB#"
184                 << PredBB->getNumber() << '\n';
185          llvm_unreachable(nullptr);
186        }
187      }
188
189      for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
190        MachineBasicBlock *PHIBB = MI->getOperand(i+1).getMBB();
191        if (CheckExtra && !Preds.count(PHIBB)) {
192          dbgs() << "Warning: malformed PHI in BB#" << MBB->getNumber()
193                 << ": " << *MI;
194          dbgs() << "  extra input from predecessor BB#"
195                 << PHIBB->getNumber() << '\n';
196          llvm_unreachable(nullptr);
197        }
198        if (PHIBB->getNumber() < 0) {
199          dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
200          dbgs() << "  non-existing BB#" << PHIBB->getNumber() << '\n';
201          llvm_unreachable(nullptr);
202        }
203      }
204      ++MI;
205    }
206  }
207}
208
209/// TailDuplicateAndUpdate - Tail duplicate the block and cleanup.
210bool
211TailDuplicatePass::TailDuplicateAndUpdate(MachineBasicBlock *MBB,
212                                          bool IsSimple,
213                                          MachineFunction &MF) {
214  // Save the successors list.
215  SmallSetVector<MachineBasicBlock*, 8> Succs(MBB->succ_begin(),
216                                              MBB->succ_end());
217
218  SmallVector<MachineBasicBlock*, 8> TDBBs;
219  SmallVector<MachineInstr*, 16> Copies;
220  if (!TailDuplicate(MBB, IsSimple, MF, TDBBs, Copies))
221    return false;
222
223  ++NumTails;
224
225  SmallVector<MachineInstr*, 8> NewPHIs;
226  MachineSSAUpdater SSAUpdate(MF, &NewPHIs);
227
228  // TailBB's immediate successors are now successors of those predecessors
229  // which duplicated TailBB. Add the predecessors as sources to the PHI
230  // instructions.
231  bool isDead = MBB->pred_empty() && !MBB->hasAddressTaken();
232  if (PreRegAlloc)
233    UpdateSuccessorsPHIs(MBB, isDead, TDBBs, Succs);
234
235  // If it is dead, remove it.
236  if (isDead) {
237    NumInstrDups -= MBB->size();
238    RemoveDeadBlock(MBB);
239    ++NumDeadBlocks;
240  }
241
242  // Update SSA form.
243  if (!SSAUpdateVRs.empty()) {
244    for (unsigned i = 0, e = SSAUpdateVRs.size(); i != e; ++i) {
245      unsigned VReg = SSAUpdateVRs[i];
246      SSAUpdate.Initialize(VReg);
247
248      // If the original definition is still around, add it as an available
249      // value.
250      MachineInstr *DefMI = MRI->getVRegDef(VReg);
251      MachineBasicBlock *DefBB = nullptr;
252      if (DefMI) {
253        DefBB = DefMI->getParent();
254        SSAUpdate.AddAvailableValue(DefBB, VReg);
255      }
256
257      // Add the new vregs as available values.
258      DenseMap<unsigned, AvailableValsTy>::iterator LI =
259        SSAUpdateVals.find(VReg);
260      for (unsigned j = 0, ee = LI->second.size(); j != ee; ++j) {
261        MachineBasicBlock *SrcBB = LI->second[j].first;
262        unsigned SrcReg = LI->second[j].second;
263        SSAUpdate.AddAvailableValue(SrcBB, SrcReg);
264      }
265
266      // Rewrite uses that are outside of the original def's block.
267      MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
268      while (UI != MRI->use_end()) {
269        MachineOperand &UseMO = *UI;
270        MachineInstr *UseMI = UseMO.getParent();
271        ++UI;
272        if (UseMI->isDebugValue()) {
273          // SSAUpdate can replace the use with an undef. That creates
274          // a debug instruction that is a kill.
275          // FIXME: Should it SSAUpdate job to delete debug instructions
276          // instead of replacing the use with undef?
277          UseMI->eraseFromParent();
278          continue;
279        }
280        if (UseMI->getParent() == DefBB && !UseMI->isPHI())
281          continue;
282        SSAUpdate.RewriteUse(UseMO);
283      }
284    }
285
286    SSAUpdateVRs.clear();
287    SSAUpdateVals.clear();
288  }
289
290  // Eliminate some of the copies inserted by tail duplication to maintain
291  // SSA form.
292  for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
293    MachineInstr *Copy = Copies[i];
294    if (!Copy->isCopy())
295      continue;
296    unsigned Dst = Copy->getOperand(0).getReg();
297    unsigned Src = Copy->getOperand(1).getReg();
298    if (MRI->hasOneNonDBGUse(Src) &&
299        MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
300      // Copy is the only use. Do trivial copy propagation here.
301      MRI->replaceRegWith(Dst, Src);
302      Copy->eraseFromParent();
303    }
304  }
305
306  if (NewPHIs.size())
307    NumAddedPHIs += NewPHIs.size();
308
309  return true;
310}
311
312/// TailDuplicateBlocks - Look for small blocks that are unconditionally
313/// branched to and do not fall through. Tail-duplicate their instructions
314/// into their predecessors to eliminate (dynamic) branches.
315bool TailDuplicatePass::TailDuplicateBlocks(MachineFunction &MF) {
316  bool MadeChange = false;
317
318  if (PreRegAlloc && TailDupVerify) {
319    DEBUG(dbgs() << "\n*** Before tail-duplicating\n");
320    VerifyPHIs(MF, true);
321  }
322
323  for (MachineFunction::iterator I = ++MF.begin(), E = MF.end(); I != E; ) {
324    MachineBasicBlock *MBB = I++;
325
326    if (NumTails == TailDupLimit)
327      break;
328
329    bool IsSimple = isSimpleBB(MBB);
330
331    if (!shouldTailDuplicate(MF, IsSimple, *MBB))
332      continue;
333
334    MadeChange |= TailDuplicateAndUpdate(MBB, IsSimple, MF);
335  }
336
337  if (PreRegAlloc && TailDupVerify)
338    VerifyPHIs(MF, false);
339
340  return MadeChange;
341}
342
343static bool isDefLiveOut(unsigned Reg, MachineBasicBlock *BB,
344                         const MachineRegisterInfo *MRI) {
345  for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
346    if (UseMI.isDebugValue())
347      continue;
348    if (UseMI.getParent() != BB)
349      return true;
350  }
351  return false;
352}
353
354static unsigned getPHISrcRegOpIdx(MachineInstr *MI, MachineBasicBlock *SrcBB) {
355  for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2)
356    if (MI->getOperand(i+1).getMBB() == SrcBB)
357      return i;
358  return 0;
359}
360
361
362// Remember which registers are used by phis in this block. This is
363// used to determine which registers are liveout while modifying the
364// block (which is why we need to copy the information).
365static void getRegsUsedByPHIs(const MachineBasicBlock &BB,
366                              DenseSet<unsigned> *UsedByPhi) {
367  for (const auto &MI : BB) {
368    if (!MI.isPHI())
369      break;
370    for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
371      unsigned SrcReg = MI.getOperand(i).getReg();
372      UsedByPhi->insert(SrcReg);
373    }
374  }
375}
376
377/// AddSSAUpdateEntry - Add a definition and source virtual registers pair for
378/// SSA update.
379void TailDuplicatePass::AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
380                                          MachineBasicBlock *BB) {
381  DenseMap<unsigned, AvailableValsTy>::iterator LI= SSAUpdateVals.find(OrigReg);
382  if (LI != SSAUpdateVals.end())
383    LI->second.push_back(std::make_pair(BB, NewReg));
384  else {
385    AvailableValsTy Vals;
386    Vals.push_back(std::make_pair(BB, NewReg));
387    SSAUpdateVals.insert(std::make_pair(OrigReg, Vals));
388    SSAUpdateVRs.push_back(OrigReg);
389  }
390}
391
392/// ProcessPHI - Process PHI node in TailBB by turning it into a copy in PredBB.
393/// Remember the source register that's contributed by PredBB and update SSA
394/// update map.
395void TailDuplicatePass::ProcessPHI(
396    MachineInstr *MI, MachineBasicBlock *TailBB, MachineBasicBlock *PredBB,
397    DenseMap<unsigned, unsigned> &LocalVRMap,
398    SmallVectorImpl<std::pair<unsigned, unsigned> > &Copies,
399    const DenseSet<unsigned> &RegsUsedByPhi, bool Remove) {
400  unsigned DefReg = MI->getOperand(0).getReg();
401  unsigned SrcOpIdx = getPHISrcRegOpIdx(MI, PredBB);
402  assert(SrcOpIdx && "Unable to find matching PHI source?");
403  unsigned SrcReg = MI->getOperand(SrcOpIdx).getReg();
404  const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
405  LocalVRMap.insert(std::make_pair(DefReg, SrcReg));
406
407  // Insert a copy from source to the end of the block. The def register is the
408  // available value liveout of the block.
409  unsigned NewDef = MRI->createVirtualRegister(RC);
410  Copies.push_back(std::make_pair(NewDef, SrcReg));
411  if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg))
412    AddSSAUpdateEntry(DefReg, NewDef, PredBB);
413
414  if (!Remove)
415    return;
416
417  // Remove PredBB from the PHI node.
418  MI->RemoveOperand(SrcOpIdx+1);
419  MI->RemoveOperand(SrcOpIdx);
420  if (MI->getNumOperands() == 1)
421    MI->eraseFromParent();
422}
423
424/// DuplicateInstruction - Duplicate a TailBB instruction to PredBB and update
425/// the source operands due to earlier PHI translation.
426void TailDuplicatePass::DuplicateInstruction(MachineInstr *MI,
427                                     MachineBasicBlock *TailBB,
428                                     MachineBasicBlock *PredBB,
429                                     MachineFunction &MF,
430                                     DenseMap<unsigned, unsigned> &LocalVRMap,
431                                     const DenseSet<unsigned> &UsedByPhi) {
432  MachineInstr *NewMI = TII->duplicate(MI, MF);
433  for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
434    MachineOperand &MO = NewMI->getOperand(i);
435    if (!MO.isReg())
436      continue;
437    unsigned Reg = MO.getReg();
438    if (!TargetRegisterInfo::isVirtualRegister(Reg))
439      continue;
440    if (MO.isDef()) {
441      const TargetRegisterClass *RC = MRI->getRegClass(Reg);
442      unsigned NewReg = MRI->createVirtualRegister(RC);
443      MO.setReg(NewReg);
444      LocalVRMap.insert(std::make_pair(Reg, NewReg));
445      if (isDefLiveOut(Reg, TailBB, MRI) || UsedByPhi.count(Reg))
446        AddSSAUpdateEntry(Reg, NewReg, PredBB);
447    } else {
448      DenseMap<unsigned, unsigned>::iterator VI = LocalVRMap.find(Reg);
449      if (VI != LocalVRMap.end()) {
450        MO.setReg(VI->second);
451        MRI->constrainRegClass(VI->second, MRI->getRegClass(Reg));
452      }
453    }
454  }
455  PredBB->insert(PredBB->instr_end(), NewMI);
456}
457
458/// UpdateSuccessorsPHIs - After FromBB is tail duplicated into its predecessor
459/// blocks, the successors have gained new predecessors. Update the PHI
460/// instructions in them accordingly.
461void
462TailDuplicatePass::UpdateSuccessorsPHIs(MachineBasicBlock *FromBB, bool isDead,
463                                  SmallVectorImpl<MachineBasicBlock *> &TDBBs,
464                                  SmallSetVector<MachineBasicBlock*,8> &Succs) {
465  for (SmallSetVector<MachineBasicBlock*, 8>::iterator SI = Succs.begin(),
466         SE = Succs.end(); SI != SE; ++SI) {
467    MachineBasicBlock *SuccBB = *SI;
468    for (MachineBasicBlock::iterator II = SuccBB->begin(), EE = SuccBB->end();
469         II != EE; ++II) {
470      if (!II->isPHI())
471        break;
472      MachineInstrBuilder MIB(*FromBB->getParent(), II);
473      unsigned Idx = 0;
474      for (unsigned i = 1, e = II->getNumOperands(); i != e; i += 2) {
475        MachineOperand &MO = II->getOperand(i+1);
476        if (MO.getMBB() == FromBB) {
477          Idx = i;
478          break;
479        }
480      }
481
482      assert(Idx != 0);
483      MachineOperand &MO0 = II->getOperand(Idx);
484      unsigned Reg = MO0.getReg();
485      if (isDead) {
486        // Folded into the previous BB.
487        // There could be duplicate phi source entries. FIXME: Should sdisel
488        // or earlier pass fixed this?
489        for (unsigned i = II->getNumOperands()-2; i != Idx; i -= 2) {
490          MachineOperand &MO = II->getOperand(i+1);
491          if (MO.getMBB() == FromBB) {
492            II->RemoveOperand(i+1);
493            II->RemoveOperand(i);
494          }
495        }
496      } else
497        Idx = 0;
498
499      // If Idx is set, the operands at Idx and Idx+1 must be removed.
500      // We reuse the location to avoid expensive RemoveOperand calls.
501
502      DenseMap<unsigned,AvailableValsTy>::iterator LI=SSAUpdateVals.find(Reg);
503      if (LI != SSAUpdateVals.end()) {
504        // This register is defined in the tail block.
505        for (unsigned j = 0, ee = LI->second.size(); j != ee; ++j) {
506          MachineBasicBlock *SrcBB = LI->second[j].first;
507          // If we didn't duplicate a bb into a particular predecessor, we
508          // might still have added an entry to SSAUpdateVals to correcly
509          // recompute SSA. If that case, avoid adding a dummy extra argument
510          // this PHI.
511          if (!SrcBB->isSuccessor(SuccBB))
512            continue;
513
514          unsigned SrcReg = LI->second[j].second;
515          if (Idx != 0) {
516            II->getOperand(Idx).setReg(SrcReg);
517            II->getOperand(Idx+1).setMBB(SrcBB);
518            Idx = 0;
519          } else {
520            MIB.addReg(SrcReg).addMBB(SrcBB);
521          }
522        }
523      } else {
524        // Live in tail block, must also be live in predecessors.
525        for (unsigned j = 0, ee = TDBBs.size(); j != ee; ++j) {
526          MachineBasicBlock *SrcBB = TDBBs[j];
527          if (Idx != 0) {
528            II->getOperand(Idx).setReg(Reg);
529            II->getOperand(Idx+1).setMBB(SrcBB);
530            Idx = 0;
531          } else {
532            MIB.addReg(Reg).addMBB(SrcBB);
533          }
534        }
535      }
536      if (Idx != 0) {
537        II->RemoveOperand(Idx+1);
538        II->RemoveOperand(Idx);
539      }
540    }
541  }
542}
543
544/// shouldTailDuplicate - Determine if it is profitable to duplicate this block.
545bool
546TailDuplicatePass::shouldTailDuplicate(const MachineFunction &MF,
547                                       bool IsSimple,
548                                       MachineBasicBlock &TailBB) {
549  // Only duplicate blocks that end with unconditional branches.
550  if (TailBB.canFallThrough())
551    return false;
552
553  // Don't try to tail-duplicate single-block loops.
554  if (TailBB.isSuccessor(&TailBB))
555    return false;
556
557  // Set the limit on the cost to duplicate. When optimizing for size,
558  // duplicate only one, because one branch instruction can be eliminated to
559  // compensate for the duplication.
560  unsigned MaxDuplicateCount;
561  if (TailDuplicateSize.getNumOccurrences() == 0 &&
562      MF.getFunction()->getAttributes().
563        hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize))
564    MaxDuplicateCount = 1;
565  else
566    MaxDuplicateCount = TailDuplicateSize;
567
568  // If the target has hardware branch prediction that can handle indirect
569  // branches, duplicating them can often make them predictable when there
570  // are common paths through the code.  The limit needs to be high enough
571  // to allow undoing the effects of tail merging and other optimizations
572  // that rearrange the predecessors of the indirect branch.
573
574  bool HasIndirectbr = false;
575  if (!TailBB.empty())
576    HasIndirectbr = TailBB.back().isIndirectBranch();
577
578  if (HasIndirectbr && PreRegAlloc)
579    MaxDuplicateCount = 20;
580
581  // Check the instructions in the block to determine whether tail-duplication
582  // is invalid or unlikely to be profitable.
583  unsigned InstrCount = 0;
584  for (MachineBasicBlock::iterator I = TailBB.begin(); I != TailBB.end(); ++I) {
585    // Non-duplicable things shouldn't be tail-duplicated.
586    if (I->isNotDuplicable())
587      return false;
588
589    // Do not duplicate 'return' instructions if this is a pre-regalloc run.
590    // A return may expand into a lot more instructions (e.g. reload of callee
591    // saved registers) after PEI.
592    if (PreRegAlloc && I->isReturn())
593      return false;
594
595    // Avoid duplicating calls before register allocation. Calls presents a
596    // barrier to register allocation so duplicating them may end up increasing
597    // spills.
598    if (PreRegAlloc && I->isCall())
599      return false;
600
601    if (!I->isPHI() && !I->isDebugValue())
602      InstrCount += 1;
603
604    if (InstrCount > MaxDuplicateCount)
605      return false;
606  }
607
608  if (HasIndirectbr && PreRegAlloc)
609    return true;
610
611  if (IsSimple)
612    return true;
613
614  if (!PreRegAlloc)
615    return true;
616
617  return canCompletelyDuplicateBB(TailBB);
618}
619
620/// isSimpleBB - True if this BB has only one unconditional jump.
621bool
622TailDuplicatePass::isSimpleBB(MachineBasicBlock *TailBB) {
623  if (TailBB->succ_size() != 1)
624    return false;
625  if (TailBB->pred_empty())
626    return false;
627  MachineBasicBlock::iterator I = TailBB->begin();
628  MachineBasicBlock::iterator E = TailBB->end();
629  while (I != E && I->isDebugValue())
630    ++I;
631  if (I == E)
632    return true;
633  return I->isUnconditionalBranch();
634}
635
636static bool
637bothUsedInPHI(const MachineBasicBlock &A,
638              SmallPtrSet<MachineBasicBlock*, 8> SuccsB) {
639  for (MachineBasicBlock::const_succ_iterator SI = A.succ_begin(),
640         SE = A.succ_end(); SI != SE; ++SI) {
641    MachineBasicBlock *BB = *SI;
642    if (SuccsB.count(BB) && !BB->empty() && BB->begin()->isPHI())
643      return true;
644  }
645
646  return false;
647}
648
649bool
650TailDuplicatePass::canCompletelyDuplicateBB(MachineBasicBlock &BB) {
651  for (MachineBasicBlock::pred_iterator PI = BB.pred_begin(),
652       PE = BB.pred_end(); PI != PE; ++PI) {
653    MachineBasicBlock *PredBB = *PI;
654
655    if (PredBB->succ_size() > 1)
656      return false;
657
658    MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
659    SmallVector<MachineOperand, 4> PredCond;
660    if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
661      return false;
662
663    if (!PredCond.empty())
664      return false;
665  }
666  return true;
667}
668
669bool
670TailDuplicatePass::duplicateSimpleBB(MachineBasicBlock *TailBB,
671                                    SmallVectorImpl<MachineBasicBlock *> &TDBBs,
672                                    const DenseSet<unsigned> &UsedByPhi,
673                                    SmallVectorImpl<MachineInstr *> &Copies) {
674  SmallPtrSet<MachineBasicBlock*, 8> Succs(TailBB->succ_begin(),
675                                           TailBB->succ_end());
676  SmallVector<MachineBasicBlock*, 8> Preds(TailBB->pred_begin(),
677                                           TailBB->pred_end());
678  bool Changed = false;
679  for (SmallSetVector<MachineBasicBlock *, 8>::iterator PI = Preds.begin(),
680       PE = Preds.end(); PI != PE; ++PI) {
681    MachineBasicBlock *PredBB = *PI;
682
683    if (PredBB->getLandingPadSuccessor())
684      continue;
685
686    if (bothUsedInPHI(*PredBB, Succs))
687      continue;
688
689    MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
690    SmallVector<MachineOperand, 4> PredCond;
691    if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
692      continue;
693
694    Changed = true;
695    DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB
696                 << "From simple Succ: " << *TailBB);
697
698    MachineBasicBlock *NewTarget = *TailBB->succ_begin();
699    MachineBasicBlock *NextBB = std::next(MachineFunction::iterator(PredBB));
700
701    // Make PredFBB explicit.
702    if (PredCond.empty())
703      PredFBB = PredTBB;
704
705    // Make fall through explicit.
706    if (!PredTBB)
707      PredTBB = NextBB;
708    if (!PredFBB)
709      PredFBB = NextBB;
710
711    // Redirect
712    if (PredFBB == TailBB)
713      PredFBB = NewTarget;
714    if (PredTBB == TailBB)
715      PredTBB = NewTarget;
716
717    // Make the branch unconditional if possible
718    if (PredTBB == PredFBB) {
719      PredCond.clear();
720      PredFBB = nullptr;
721    }
722
723    // Avoid adding fall through branches.
724    if (PredFBB == NextBB)
725      PredFBB = nullptr;
726    if (PredTBB == NextBB && PredFBB == nullptr)
727      PredTBB = nullptr;
728
729    TII->RemoveBranch(*PredBB);
730
731    if (PredTBB)
732      TII->InsertBranch(*PredBB, PredTBB, PredFBB, PredCond, DebugLoc());
733
734    uint32_t Weight = MBPI->getEdgeWeight(PredBB, TailBB);
735    PredBB->removeSuccessor(TailBB);
736    unsigned NumSuccessors = PredBB->succ_size();
737    assert(NumSuccessors <= 1);
738    if (NumSuccessors == 0 || *PredBB->succ_begin() != NewTarget)
739      PredBB->addSuccessor(NewTarget, Weight);
740
741    TDBBs.push_back(PredBB);
742  }
743  return Changed;
744}
745
746/// TailDuplicate - If it is profitable, duplicate TailBB's contents in each
747/// of its predecessors.
748bool
749TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB,
750                                 bool IsSimple,
751                                 MachineFunction &MF,
752                                 SmallVectorImpl<MachineBasicBlock *> &TDBBs,
753                                 SmallVectorImpl<MachineInstr *> &Copies) {
754  DEBUG(dbgs() << "\n*** Tail-duplicating BB#" << TailBB->getNumber() << '\n');
755
756  DenseSet<unsigned> UsedByPhi;
757  getRegsUsedByPHIs(*TailBB, &UsedByPhi);
758
759  if (IsSimple)
760    return duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
761
762  // Iterate through all the unique predecessors and tail-duplicate this
763  // block into them, if possible. Copying the list ahead of time also
764  // avoids trouble with the predecessor list reallocating.
765  bool Changed = false;
766  SmallSetVector<MachineBasicBlock*, 8> Preds(TailBB->pred_begin(),
767                                              TailBB->pred_end());
768  for (SmallSetVector<MachineBasicBlock *, 8>::iterator PI = Preds.begin(),
769       PE = Preds.end(); PI != PE; ++PI) {
770    MachineBasicBlock *PredBB = *PI;
771
772    assert(TailBB != PredBB &&
773           "Single-block loop should have been rejected earlier!");
774    // EH edges are ignored by AnalyzeBranch.
775    if (PredBB->succ_size() > 1)
776      continue;
777
778    MachineBasicBlock *PredTBB, *PredFBB;
779    SmallVector<MachineOperand, 4> PredCond;
780    if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
781      continue;
782    if (!PredCond.empty())
783      continue;
784    // Don't duplicate into a fall-through predecessor (at least for now).
785    if (PredBB->isLayoutSuccessor(TailBB) && PredBB->canFallThrough())
786      continue;
787
788    DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB
789                 << "From Succ: " << *TailBB);
790
791    TDBBs.push_back(PredBB);
792
793    // Remove PredBB's unconditional branch.
794    TII->RemoveBranch(*PredBB);
795
796    if (RS && !TailBB->livein_empty()) {
797      // Update PredBB livein.
798      RS->enterBasicBlock(PredBB);
799      if (!PredBB->empty())
800        RS->forward(std::prev(PredBB->end()));
801      BitVector RegsLiveAtExit(TRI->getNumRegs());
802      RS->getRegsUsed(RegsLiveAtExit, false);
803      for (MachineBasicBlock::livein_iterator I = TailBB->livein_begin(),
804             E = TailBB->livein_end(); I != E; ++I) {
805        if (!RegsLiveAtExit[*I])
806          // If a register is previously livein to the tail but it's not live
807          // at the end of predecessor BB, then it should be added to its
808          // livein list.
809          PredBB->addLiveIn(*I);
810      }
811    }
812
813    // Clone the contents of TailBB into PredBB.
814    DenseMap<unsigned, unsigned> LocalVRMap;
815    SmallVector<std::pair<unsigned,unsigned>, 4> CopyInfos;
816    // Use instr_iterator here to properly handle bundles, e.g.
817    // ARM Thumb2 IT block.
818    MachineBasicBlock::instr_iterator I = TailBB->instr_begin();
819    while (I != TailBB->instr_end()) {
820      MachineInstr *MI = &*I;
821      ++I;
822      if (MI->isPHI()) {
823        // Replace the uses of the def of the PHI with the register coming
824        // from PredBB.
825        ProcessPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi, true);
826      } else {
827        // Replace def of virtual registers with new registers, and update
828        // uses with PHI source register or the new registers.
829        DuplicateInstruction(MI, TailBB, PredBB, MF, LocalVRMap, UsedByPhi);
830      }
831    }
832    MachineBasicBlock::iterator Loc = PredBB->getFirstTerminator();
833    for (unsigned i = 0, e = CopyInfos.size(); i != e; ++i) {
834      Copies.push_back(BuildMI(*PredBB, Loc, DebugLoc(),
835                               TII->get(TargetOpcode::COPY),
836                               CopyInfos[i].first).addReg(CopyInfos[i].second));
837    }
838
839    // Simplify
840    TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true);
841
842    NumInstrDups += TailBB->size() - 1; // subtract one for removed branch
843
844    // Update the CFG.
845    PredBB->removeSuccessor(PredBB->succ_begin());
846    assert(PredBB->succ_empty() &&
847           "TailDuplicate called on block with multiple successors!");
848    for (MachineBasicBlock::succ_iterator I = TailBB->succ_begin(),
849           E = TailBB->succ_end(); I != E; ++I)
850      PredBB->addSuccessor(*I, MBPI->getEdgeWeight(TailBB, I));
851
852    Changed = true;
853    ++NumTailDups;
854  }
855
856  // If TailBB was duplicated into all its predecessors except for the prior
857  // block, which falls through unconditionally, move the contents of this
858  // block into the prior block.
859  MachineBasicBlock *PrevBB = std::prev(MachineFunction::iterator(TailBB));
860  MachineBasicBlock *PriorTBB = nullptr, *PriorFBB = nullptr;
861  SmallVector<MachineOperand, 4> PriorCond;
862  // This has to check PrevBB->succ_size() because EH edges are ignored by
863  // AnalyzeBranch.
864  if (PrevBB->succ_size() == 1 &&
865      !TII->AnalyzeBranch(*PrevBB, PriorTBB, PriorFBB, PriorCond, true) &&
866      PriorCond.empty() && !PriorTBB && TailBB->pred_size() == 1 &&
867      !TailBB->hasAddressTaken()) {
868    DEBUG(dbgs() << "\nMerging into block: " << *PrevBB
869          << "From MBB: " << *TailBB);
870    if (PreRegAlloc) {
871      DenseMap<unsigned, unsigned> LocalVRMap;
872      SmallVector<std::pair<unsigned,unsigned>, 4> CopyInfos;
873      MachineBasicBlock::iterator I = TailBB->begin();
874      // Process PHI instructions first.
875      while (I != TailBB->end() && I->isPHI()) {
876        // Replace the uses of the def of the PHI with the register coming
877        // from PredBB.
878        MachineInstr *MI = &*I++;
879        ProcessPHI(MI, TailBB, PrevBB, LocalVRMap, CopyInfos, UsedByPhi, true);
880        if (MI->getParent())
881          MI->eraseFromParent();
882      }
883
884      // Now copy the non-PHI instructions.
885      while (I != TailBB->end()) {
886        // Replace def of virtual registers with new registers, and update
887        // uses with PHI source register or the new registers.
888        MachineInstr *MI = &*I++;
889        assert(!MI->isBundle() && "Not expecting bundles before regalloc!");
890        DuplicateInstruction(MI, TailBB, PrevBB, MF, LocalVRMap, UsedByPhi);
891        MI->eraseFromParent();
892      }
893      MachineBasicBlock::iterator Loc = PrevBB->getFirstTerminator();
894      for (unsigned i = 0, e = CopyInfos.size(); i != e; ++i) {
895        Copies.push_back(BuildMI(*PrevBB, Loc, DebugLoc(),
896                                 TII->get(TargetOpcode::COPY),
897                                 CopyInfos[i].first)
898                           .addReg(CopyInfos[i].second));
899      }
900    } else {
901      // No PHIs to worry about, just splice the instructions over.
902      PrevBB->splice(PrevBB->end(), TailBB, TailBB->begin(), TailBB->end());
903    }
904    PrevBB->removeSuccessor(PrevBB->succ_begin());
905    assert(PrevBB->succ_empty());
906    PrevBB->transferSuccessors(TailBB);
907    TDBBs.push_back(PrevBB);
908    Changed = true;
909  }
910
911  // If this is after register allocation, there are no phis to fix.
912  if (!PreRegAlloc)
913    return Changed;
914
915  // If we made no changes so far, we are safe.
916  if (!Changed)
917    return Changed;
918
919
920  // Handle the nasty case in that we duplicated a block that is part of a loop
921  // into some but not all of its predecessors. For example:
922  //    1 -> 2 <-> 3                 |
923  //          \                      |
924  //           \---> rest            |
925  // if we duplicate 2 into 1 but not into 3, we end up with
926  // 12 -> 3 <-> 2 -> rest           |
927  //   \             /               |
928  //    \----->-----/                |
929  // If there was a "var = phi(1, 3)" in 2, it has to be ultimately replaced
930  // with a phi in 3 (which now dominates 2).
931  // What we do here is introduce a copy in 3 of the register defined by the
932  // phi, just like when we are duplicating 2 into 3, but we don't copy any
933  // real instructions or remove the 3 -> 2 edge from the phi in 2.
934  for (SmallSetVector<MachineBasicBlock *, 8>::iterator PI = Preds.begin(),
935       PE = Preds.end(); PI != PE; ++PI) {
936    MachineBasicBlock *PredBB = *PI;
937    if (std::find(TDBBs.begin(), TDBBs.end(), PredBB) != TDBBs.end())
938      continue;
939
940    // EH edges
941    if (PredBB->succ_size() != 1)
942      continue;
943
944    DenseMap<unsigned, unsigned> LocalVRMap;
945    SmallVector<std::pair<unsigned,unsigned>, 4> CopyInfos;
946    MachineBasicBlock::iterator I = TailBB->begin();
947    // Process PHI instructions first.
948    while (I != TailBB->end() && I->isPHI()) {
949      // Replace the uses of the def of the PHI with the register coming
950      // from PredBB.
951      MachineInstr *MI = &*I++;
952      ProcessPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi, false);
953    }
954    MachineBasicBlock::iterator Loc = PredBB->getFirstTerminator();
955    for (unsigned i = 0, e = CopyInfos.size(); i != e; ++i) {
956      Copies.push_back(BuildMI(*PredBB, Loc, DebugLoc(),
957                               TII->get(TargetOpcode::COPY),
958                               CopyInfos[i].first).addReg(CopyInfos[i].second));
959    }
960  }
961
962  return Changed;
963}
964
965/// RemoveDeadBlock - Remove the specified dead machine basic block from the
966/// function, updating the CFG.
967void TailDuplicatePass::RemoveDeadBlock(MachineBasicBlock *MBB) {
968  assert(MBB->pred_empty() && "MBB must be dead!");
969  DEBUG(dbgs() << "\nRemoving MBB: " << *MBB);
970
971  // Remove all successors.
972  while (!MBB->succ_empty())
973    MBB->removeSuccessor(MBB->succ_end()-1);
974
975  // Remove the block.
976  MBB->eraseFromParent();
977}
978