1//===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "llvm/MC/MCSubtargetInfo.h"
11#include "llvm/ADT/StringRef.h"
12#include "llvm/ADT/Triple.h"
13#include "llvm/MC/MCInstrItineraries.h"
14#include "llvm/MC/SubtargetFeature.h"
15#include "llvm/Support/raw_ostream.h"
16#include <algorithm>
17
18using namespace llvm;
19
20MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors.
21
22/// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
23/// with feature string). Recompute feature bits and scheduling model.
24void
25MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
26  SubtargetFeatures Features(FS);
27  FeatureBits = Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
28  InitCPUSchedModel(CPU);
29}
30
31void
32MCSubtargetInfo::InitCPUSchedModel(StringRef CPU) {
33  if (!CPU.empty())
34    CPUSchedModel = getSchedModelForCPU(CPU);
35  else
36    CPUSchedModel = &MCSchedModel::DefaultSchedModel;
37}
38
39void
40MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
41                                     ArrayRef<SubtargetFeatureKV> PF,
42                                     ArrayRef<SubtargetFeatureKV> PD,
43                                     const SubtargetInfoKV *ProcSched,
44                                     const MCWriteProcResEntry *WPR,
45                                     const MCWriteLatencyEntry *WL,
46                                     const MCReadAdvanceEntry *RA,
47                                     const InstrStage *IS,
48                                     const unsigned *OC,
49                                     const unsigned *FP) {
50  TargetTriple = TT;
51  ProcFeatures = PF;
52  ProcDesc = PD;
53  ProcSchedModels = ProcSched;
54  WriteProcResTable = WPR;
55  WriteLatencyTable = WL;
56  ReadAdvanceTable = RA;
57
58  Stages = IS;
59  OperandCycles = OC;
60  ForwardingPaths = FP;
61
62  InitMCProcessorInfo(CPU, FS);
63}
64
65/// ToggleFeature - Toggle a feature and returns the re-computed feature
66/// bits. This version does not change the implied bits.
67uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
68  FeatureBits ^= FB;
69  return FeatureBits;
70}
71
72/// ToggleFeature - Toggle a feature and returns the re-computed feature
73/// bits. This version will also change all implied bits.
74uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
75  SubtargetFeatures Features;
76  FeatureBits = Features.ToggleFeature(FeatureBits, FS, ProcFeatures);
77  return FeatureBits;
78}
79
80
81const MCSchedModel *
82MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
83  assert(ProcSchedModels && "Processor machine model not available!");
84
85  unsigned NumProcs = ProcDesc.size();
86#ifndef NDEBUG
87  for (size_t i = 1; i < NumProcs; i++) {
88    assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 &&
89           "Processor machine model table is not sorted");
90  }
91#endif
92
93  // Find entry
94  const SubtargetInfoKV *Found =
95    std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, CPU);
96  if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) {
97    errs() << "'" << CPU
98           << "' is not a recognized processor for this target"
99           << " (ignoring processor)\n";
100    return &MCSchedModel::DefaultSchedModel;
101  }
102  assert(Found->Value && "Missing processor SchedModel value");
103  return (const MCSchedModel *)Found->Value;
104}
105
106InstrItineraryData
107MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
108  const MCSchedModel *SchedModel = getSchedModelForCPU(CPU);
109  return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
110}
111
112/// Initialize an InstrItineraryData instance.
113void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
114  InstrItins =
115    InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths);
116}
117