1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// AArch64 Subtarget features.
21//
22
23def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
24                                       "Enable ARMv8 FP">;
25
26def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27  "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
28
29def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
30  "Enable cryptographic instructions">;
31
32def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33  "Enable ARMv8 CRC-32 checksum instructions">;
34
35/// Cyclone has register move instructions which are "free".
36def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
37                                        "Has zero-cycle register moves">;
38
39/// Cyclone has instructions which zero registers for "free".
40def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
41                                        "Has zero-cycle zeroing instructions">;
42
43//===----------------------------------------------------------------------===//
44// Register File Description
45//===----------------------------------------------------------------------===//
46
47include "AArch64RegisterInfo.td"
48include "AArch64CallingConvention.td"
49
50//===----------------------------------------------------------------------===//
51// Instruction Descriptions
52//===----------------------------------------------------------------------===//
53
54include "AArch64Schedule.td"
55include "AArch64InstrInfo.td"
56
57def AArch64InstrInfo : InstrInfo;
58
59//===----------------------------------------------------------------------===//
60// AArch64 Processors supported.
61//
62include "AArch64SchedA53.td"
63include "AArch64SchedA57.td"
64include "AArch64SchedCyclone.td"
65
66def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
67                                   "Cortex-A53 ARM processors",
68                                   [FeatureFPARMv8,
69                                   FeatureNEON,
70                                   FeatureCrypto,
71                                   FeatureCRC]>;
72
73def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
74                                   "Cortex-A57 ARM processors",
75                                   [FeatureFPARMv8,
76                                   FeatureNEON,
77                                   FeatureCrypto,
78                                   FeatureCRC]>;
79
80def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
81                                   "Cyclone",
82                                   [FeatureFPARMv8,
83                                   FeatureNEON,
84                                   FeatureCrypto,
85                                   FeatureCRC,
86                                   FeatureZCRegMove, FeatureZCZeroing]>;
87
88def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
89                                              FeatureNEON,
90                                              FeatureCRC]>;
91
92def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
93def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
94def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
95
96//===----------------------------------------------------------------------===//
97// Assembly parser
98//===----------------------------------------------------------------------===//
99
100def GenericAsmParserVariant : AsmParserVariant {
101  int Variant = 0;
102  string Name = "generic";
103}
104
105def AppleAsmParserVariant : AsmParserVariant {
106  int Variant = 1;
107  string Name = "apple-neon";
108}
109
110//===----------------------------------------------------------------------===//
111// Assembly printer
112//===----------------------------------------------------------------------===//
113// AArch64 Uses the MC printer for asm output, so make sure the TableGen
114// AsmWriter bits get associated with the correct class.
115def GenericAsmWriter : AsmWriter {
116  string AsmWriterClassName  = "InstPrinter";
117  int Variant = 0;
118  bit isMCAsmWriter = 1;
119}
120
121def AppleAsmWriter : AsmWriter {
122  let AsmWriterClassName = "AppleInstPrinter";
123  int Variant = 1;
124  int isMCAsmWriter = 1;
125}
126
127//===----------------------------------------------------------------------===//
128// Target Declaration
129//===----------------------------------------------------------------------===//
130
131def AArch64 : Target {
132  let InstructionSet = AArch64InstrInfo;
133  let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
134  let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
135}
136