AArch64DeadRegisterDefinitionsPass.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// When allowed by the instruction, replace a dead definition of a GPR with
10// the zero register. This makes the code a bit friendlier towards the
11// hardware's register renamer.
12//===----------------------------------------------------------------------===//
13
14#include "AArch64.h"
15#include "AArch64RegisterInfo.h"
16#include "llvm/ADT/Statistic.h"
17#include "llvm/CodeGen/MachineFunctionPass.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/CodeGen/MachineInstr.h"
20#include "llvm/Support/Debug.h"
21#include "llvm/Support/raw_ostream.h"
22using namespace llvm;
23
24#define DEBUG_TYPE "aarch64-dead-defs"
25
26STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
27
28namespace {
29class AArch64DeadRegisterDefinitions : public MachineFunctionPass {
30private:
31  const TargetRegisterInfo *TRI;
32  bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI);
33  bool processMachineBasicBlock(MachineBasicBlock &MBB);
34  bool usesFrameIndex(const MachineInstr &MI);
35public:
36  static char ID; // Pass identification, replacement for typeid.
37  explicit AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {}
38
39  virtual bool runOnMachineFunction(MachineFunction &F) override;
40
41  const char *getPassName() const override { return "Dead register definitions"; }
42
43  virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
44    AU.setPreservesCFG();
45    MachineFunctionPass::getAnalysisUsage(AU);
46  }
47};
48char AArch64DeadRegisterDefinitions::ID = 0;
49} // end anonymous namespace
50
51bool AArch64DeadRegisterDefinitions::implicitlyDefinesOverlappingReg(
52    unsigned Reg, const MachineInstr &MI) {
53  for (const MachineOperand &MO : MI.implicit_operands())
54    if (MO.isReg() && MO.isDef())
55      if (TRI->regsOverlap(Reg, MO.getReg()))
56        return true;
57  return false;
58}
59
60bool AArch64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr &MI) {
61  for (const MachineOperand &Op : MI.uses())
62    if (Op.isFI())
63      return true;
64  return false;
65}
66
67bool AArch64DeadRegisterDefinitions::processMachineBasicBlock(
68    MachineBasicBlock &MBB) {
69  bool Changed = false;
70  for (MachineInstr &MI : MBB) {
71    if (usesFrameIndex(MI)) {
72      // We need to skip this instruction because while it appears to have a
73      // dead def it uses a frame index which might expand into a multi
74      // instruction sequence during EPI.
75      DEBUG(dbgs() << "    Ignoring, operand is frame index\n");
76      continue;
77    }
78    for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) {
79      MachineOperand &MO = MI.getOperand(i);
80      if (MO.isReg() && MO.isDead() && MO.isDef()) {
81        assert(!MO.isImplicit() && "Unexpected implicit def!");
82        DEBUG(dbgs() << "  Dead def operand #" << i << " in:\n    ";
83              MI.print(dbgs()));
84        // Be careful not to change the register if it's a tied operand.
85        if (MI.isRegTiedToUseOperand(i)) {
86          DEBUG(dbgs() << "    Ignoring, def is tied operand.\n");
87          continue;
88        }
89        // Don't change the register if there's an implicit def of a subreg or
90        // supperreg.
91        if (implicitlyDefinesOverlappingReg(MO.getReg(), MI)) {
92          DEBUG(dbgs() << "    Ignoring, implicitly defines overlap reg.\n");
93          continue;
94        }
95        // Make sure the instruction take a register class that contains
96        // the zero register and replace it if so.
97        unsigned NewReg;
98        switch (MI.getDesc().OpInfo[i].RegClass) {
99        default:
100          DEBUG(dbgs() << "    Ignoring, register is not a GPR.\n");
101          continue;
102        case AArch64::GPR32RegClassID:
103          NewReg = AArch64::WZR;
104          break;
105        case AArch64::GPR64RegClassID:
106          NewReg = AArch64::XZR;
107          break;
108        }
109        DEBUG(dbgs() << "    Replacing with zero register. New:\n      ");
110        MO.setReg(NewReg);
111        DEBUG(MI.print(dbgs()));
112        ++NumDeadDefsReplaced;
113      }
114    }
115  }
116  return Changed;
117}
118
119// Scan the function for instructions that have a dead definition of a
120// register. Replace that register with the zero register when possible.
121bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
122  TRI = MF.getTarget().getRegisterInfo();
123  bool Changed = false;
124  DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
125
126  for (auto &MBB : MF)
127    if (processMachineBasicBlock(MBB))
128      Changed = true;
129  return Changed;
130}
131
132FunctionPass *llvm::createAArch64DeadRegisterDefinitions() {
133  return new AArch64DeadRegisterDefinitions();
134}
135