AArch64ISelLowering.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
15c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)//===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===// 25c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)// 35c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)// The LLVM Compiler Infrastructure 45c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)// 55c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)// License. See LICENSE.TXT for details. 75c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)// 85c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)//===----------------------------------------------------------------------===// 95c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)// 105c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)// This file implements the AArch64TargetLowering class. 115c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)// 125c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)//===----------------------------------------------------------------------===// 135c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 145c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "AArch64ISelLowering.h" 155c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "AArch64PerfectShuffle.h" 165c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "AArch64Subtarget.h" 175c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "AArch64MachineFunctionInfo.h" 185c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "AArch64TargetMachine.h" 195c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "AArch64TargetObjectFile.h" 205c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "MCTargetDesc/AArch64AddressingModes.h" 215c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "llvm/ADT/Statistic.h" 225c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "llvm/CodeGen/CallingConvLower.h" 235c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "llvm/CodeGen/MachineFrameInfo.h" 245c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "llvm/CodeGen/MachineInstrBuilder.h" 255c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "llvm/CodeGen/MachineRegisterInfo.h" 265c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "llvm/IR/Function.h" 275c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "llvm/IR/Intrinsics.h" 285c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "llvm/IR/Type.h" 295c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "llvm/Support/CommandLine.h" 305c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "llvm/Support/Debug.h" 315c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "llvm/Support/ErrorHandling.h" 325267f701546148b83dfbe1d151cb184385bb5c22Torne (Richard Coles)#include "llvm/Support/raw_ostream.h" 335c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "llvm/Target/TargetOptions.h" 34f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles)using namespace llvm; 3593ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) 3693ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles)#define DEBUG_TYPE "aarch64-lower" 375c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 3851b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles)STATISTIC(NumTailCalls, "Number of tail calls"); 395c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)STATISTIC(NumShiftInserts, "Number of vector shift inserts"); 40f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) 4193ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles)enum AlignMode { 4293ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) StrictAlign, 4393ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) NoStrictAlign 4493ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles)}; 4593ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) 4693ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles)static cl::opt<AlignMode> 4793ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles)Align(cl::desc("Load/store alignment support"), 4893ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) cl::Hidden, cl::init(NoStrictAlign), 4993ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) cl::values( 5093ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) clEnumValN(StrictAlign, "aarch64-strict-align", 5193ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) "Disallow all unaligned memory accesses"), 5293ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) clEnumValN(NoStrictAlign, "aarch64-no-strict-align", 5393ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) "Allow unaligned memory accesses"), 5493ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) clEnumValEnd)); 5593ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) 5693ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles)// Place holder until extr generation is tested fully. 5793ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles)static cl::opt<bool> 5893ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles)EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden, 5993ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) cl::desc("Allow AArch64 (or (shift)(shift))->extract"), 6093ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) cl::init(true)); 6193ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) 6293ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles)static cl::opt<bool> 635c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden, 645c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) cl::desc("Allow AArch64 SLI/SRI formation"), 655c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) cl::init(false)); 665c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 675c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)//===----------------------------------------------------------------------===// 685c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)// AArch64 Lowering public interface. 695c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)//===----------------------------------------------------------------------===// 705c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { 715c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) if (TM.getSubtarget<AArch64Subtarget>().isTargetDarwin()) 725c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) return new AArch64_MachoTargetObjectFile(); 735c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 745c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) return new AArch64_ELFTargetObjectFile(); 755c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)} 765c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 775c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM) 7893ac45cfc74041c8ae536ce58a9534d46db2024eTorne (Richard Coles) : TargetLowering(TM, createTLOF(TM)) { 795c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) Subtarget = &TM.getSubtarget<AArch64Subtarget>(); 805c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 815c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so 825c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) // we have to make something up. Arbitrarily, choose ZeroOrOne. 835c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) setBooleanContents(ZeroOrOneBooleanContent); 845c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) // When comparing vectors the result sets the different elements in the 855c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) // vector to all-one or all-zero. 865c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 875c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 885c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) // Set up the register classes. 895c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass); 905c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass); 915c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 925c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) if (Subtarget->hasFPARMv8()) { 935c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); 945c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); 955c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); 965c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); 975c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) } 985c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 9951b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) if (Subtarget->hasNEON()) { 100 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass); 101 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass); 102 // Someone set us up the NEON. 103 addDRTypeForNEON(MVT::v2f32); 104 addDRTypeForNEON(MVT::v8i8); 105 addDRTypeForNEON(MVT::v4i16); 106 addDRTypeForNEON(MVT::v2i32); 107 addDRTypeForNEON(MVT::v1i64); 108 addDRTypeForNEON(MVT::v1f64); 109 110 addQRTypeForNEON(MVT::v4f32); 111 addQRTypeForNEON(MVT::v2f64); 112 addQRTypeForNEON(MVT::v16i8); 113 addQRTypeForNEON(MVT::v8i16); 114 addQRTypeForNEON(MVT::v4i32); 115 addQRTypeForNEON(MVT::v2i64); 116 } 117 118 // Compute derived properties from the register classes 119 computeRegisterProperties(); 120 121 // Provide all sorts of operation actions 122 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 123 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 124 setOperationAction(ISD::SETCC, MVT::i32, Custom); 125 setOperationAction(ISD::SETCC, MVT::i64, Custom); 126 setOperationAction(ISD::SETCC, MVT::f32, Custom); 127 setOperationAction(ISD::SETCC, MVT::f64, Custom); 128 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 129 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 130 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 131 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 132 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 133 setOperationAction(ISD::SELECT, MVT::i32, Custom); 134 setOperationAction(ISD::SELECT, MVT::i64, Custom); 135 setOperationAction(ISD::SELECT, MVT::f32, Custom); 136 setOperationAction(ISD::SELECT, MVT::f64, Custom); 137 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 138 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 139 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 140 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 141 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 142 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 143 144 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 145 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 146 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 147 148 setOperationAction(ISD::FREM, MVT::f32, Expand); 149 setOperationAction(ISD::FREM, MVT::f64, Expand); 150 setOperationAction(ISD::FREM, MVT::f80, Expand); 151 152 // Custom lowering hooks are needed for XOR 153 // to fold it into CSINC/CSINV. 154 setOperationAction(ISD::XOR, MVT::i32, Custom); 155 setOperationAction(ISD::XOR, MVT::i64, Custom); 156 157 // Virtually no operation on f128 is legal, but LLVM can't expand them when 158 // there's a valid register class, so we need custom operations in most cases. 159 setOperationAction(ISD::FABS, MVT::f128, Expand); 160 setOperationAction(ISD::FADD, MVT::f128, Custom); 161 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); 162 setOperationAction(ISD::FCOS, MVT::f128, Expand); 163 setOperationAction(ISD::FDIV, MVT::f128, Custom); 164 setOperationAction(ISD::FMA, MVT::f128, Expand); 165 setOperationAction(ISD::FMUL, MVT::f128, Custom); 166 setOperationAction(ISD::FNEG, MVT::f128, Expand); 167 setOperationAction(ISD::FPOW, MVT::f128, Expand); 168 setOperationAction(ISD::FREM, MVT::f128, Expand); 169 setOperationAction(ISD::FRINT, MVT::f128, Expand); 170 setOperationAction(ISD::FSIN, MVT::f128, Expand); 171 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); 172 setOperationAction(ISD::FSQRT, MVT::f128, Expand); 173 setOperationAction(ISD::FSUB, MVT::f128, Custom); 174 setOperationAction(ISD::FTRUNC, MVT::f128, Expand); 175 setOperationAction(ISD::SETCC, MVT::f128, Custom); 176 setOperationAction(ISD::BR_CC, MVT::f128, Custom); 177 setOperationAction(ISD::SELECT, MVT::f128, Custom); 178 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); 179 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); 180 181 // Lowering for many of the conversions is actually specified by the non-f128 182 // type. The LowerXXX function will be trivial when f128 isn't involved. 183 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 184 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 185 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom); 186 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 187 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); 188 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom); 189 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 190 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 191 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); 192 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 193 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); 194 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom); 195 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); 196 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); 197 198 // Variable arguments. 199 setOperationAction(ISD::VASTART, MVT::Other, Custom); 200 setOperationAction(ISD::VAARG, MVT::Other, Custom); 201 setOperationAction(ISD::VACOPY, MVT::Other, Custom); 202 setOperationAction(ISD::VAEND, MVT::Other, Expand); 203 204 // Variable-sized objects. 205 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 206 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 208 209 // Exception handling. 210 // FIXME: These are guesses. Has this been defined yet? 211 setExceptionPointerRegister(AArch64::X0); 212 setExceptionSelectorRegister(AArch64::X1); 213 214 // Constant pool entries 215 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 216 217 // BlockAddress 218 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 219 220 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences. 221 setOperationAction(ISD::ADDC, MVT::i32, Custom); 222 setOperationAction(ISD::ADDE, MVT::i32, Custom); 223 setOperationAction(ISD::SUBC, MVT::i32, Custom); 224 setOperationAction(ISD::SUBE, MVT::i32, Custom); 225 setOperationAction(ISD::ADDC, MVT::i64, Custom); 226 setOperationAction(ISD::ADDE, MVT::i64, Custom); 227 setOperationAction(ISD::SUBC, MVT::i64, Custom); 228 setOperationAction(ISD::SUBE, MVT::i64, Custom); 229 230 // AArch64 lacks both left-rotate and popcount instructions. 231 setOperationAction(ISD::ROTL, MVT::i32, Expand); 232 setOperationAction(ISD::ROTL, MVT::i64, Expand); 233 234 // AArch64 doesn't have {U|S}MUL_LOHI. 235 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 236 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 237 238 239 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero 240 // counterparts, which AArch64 supports directly. 241 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 242 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 243 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 244 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 245 246 setOperationAction(ISD::CTPOP, MVT::i32, Custom); 247 setOperationAction(ISD::CTPOP, MVT::i64, Custom); 248 249 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 250 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 251 setOperationAction(ISD::SREM, MVT::i32, Expand); 252 setOperationAction(ISD::SREM, MVT::i64, Expand); 253 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 254 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 255 setOperationAction(ISD::UREM, MVT::i32, Expand); 256 setOperationAction(ISD::UREM, MVT::i64, Expand); 257 258 // Custom lower Add/Sub/Mul with overflow. 259 setOperationAction(ISD::SADDO, MVT::i32, Custom); 260 setOperationAction(ISD::SADDO, MVT::i64, Custom); 261 setOperationAction(ISD::UADDO, MVT::i32, Custom); 262 setOperationAction(ISD::UADDO, MVT::i64, Custom); 263 setOperationAction(ISD::SSUBO, MVT::i32, Custom); 264 setOperationAction(ISD::SSUBO, MVT::i64, Custom); 265 setOperationAction(ISD::USUBO, MVT::i32, Custom); 266 setOperationAction(ISD::USUBO, MVT::i64, Custom); 267 setOperationAction(ISD::SMULO, MVT::i32, Custom); 268 setOperationAction(ISD::SMULO, MVT::i64, Custom); 269 setOperationAction(ISD::UMULO, MVT::i32, Custom); 270 setOperationAction(ISD::UMULO, MVT::i64, Custom); 271 272 setOperationAction(ISD::FSIN, MVT::f32, Expand); 273 setOperationAction(ISD::FSIN, MVT::f64, Expand); 274 setOperationAction(ISD::FCOS, MVT::f32, Expand); 275 setOperationAction(ISD::FCOS, MVT::f64, Expand); 276 setOperationAction(ISD::FPOW, MVT::f32, Expand); 277 setOperationAction(ISD::FPOW, MVT::f64, Expand); 278 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 279 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 280 281 // AArch64 has implementations of a lot of rounding-like FP operations. 282 static MVT RoundingTypes[] = { MVT::f32, MVT::f64}; 283 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) { 284 MVT Ty = RoundingTypes[I]; 285 setOperationAction(ISD::FFLOOR, Ty, Legal); 286 setOperationAction(ISD::FNEARBYINT, Ty, Legal); 287 setOperationAction(ISD::FCEIL, Ty, Legal); 288 setOperationAction(ISD::FRINT, Ty, Legal); 289 setOperationAction(ISD::FTRUNC, Ty, Legal); 290 setOperationAction(ISD::FROUND, Ty, Legal); 291 } 292 293 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); 294 295 if (Subtarget->isTargetMachO()) { 296 // For iOS, we don't want to the normal expansion of a libcall to 297 // sincos. We want to issue a libcall to __sincos_stret to avoid memory 298 // traffic. 299 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); 300 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); 301 } else { 302 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 303 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 304 } 305 306 // AArch64 does not have floating-point extending loads, i1 sign-extending 307 // load, floating-point truncating stores, or v2i32->v2i16 truncating store. 308 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 309 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 310 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand); 311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand); 312 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 313 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 314 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 315 setTruncStoreAction(MVT::f128, MVT::f80, Expand); 316 setTruncStoreAction(MVT::f128, MVT::f64, Expand); 317 setTruncStoreAction(MVT::f128, MVT::f32, Expand); 318 setTruncStoreAction(MVT::f128, MVT::f16, Expand); 319 // Indexed loads and stores are supported. 320 for (unsigned im = (unsigned)ISD::PRE_INC; 321 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 322 setIndexedLoadAction(im, MVT::i8, Legal); 323 setIndexedLoadAction(im, MVT::i16, Legal); 324 setIndexedLoadAction(im, MVT::i32, Legal); 325 setIndexedLoadAction(im, MVT::i64, Legal); 326 setIndexedLoadAction(im, MVT::f64, Legal); 327 setIndexedLoadAction(im, MVT::f32, Legal); 328 setIndexedStoreAction(im, MVT::i8, Legal); 329 setIndexedStoreAction(im, MVT::i16, Legal); 330 setIndexedStoreAction(im, MVT::i32, Legal); 331 setIndexedStoreAction(im, MVT::i64, Legal); 332 setIndexedStoreAction(im, MVT::f64, Legal); 333 setIndexedStoreAction(im, MVT::f32, Legal); 334 } 335 336 // Trap. 337 setOperationAction(ISD::TRAP, MVT::Other, Legal); 338 339 // We combine OR nodes for bitfield operations. 340 setTargetDAGCombine(ISD::OR); 341 342 // Vector add and sub nodes may conceal a high-half opportunity. 343 // Also, try to fold ADD into CSINC/CSINV.. 344 setTargetDAGCombine(ISD::ADD); 345 setTargetDAGCombine(ISD::SUB); 346 347 setTargetDAGCombine(ISD::XOR); 348 setTargetDAGCombine(ISD::SINT_TO_FP); 349 setTargetDAGCombine(ISD::UINT_TO_FP); 350 351 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 352 353 setTargetDAGCombine(ISD::ANY_EXTEND); 354 setTargetDAGCombine(ISD::ZERO_EXTEND); 355 setTargetDAGCombine(ISD::SIGN_EXTEND); 356 setTargetDAGCombine(ISD::BITCAST); 357 setTargetDAGCombine(ISD::CONCAT_VECTORS); 358 setTargetDAGCombine(ISD::STORE); 359 360 setTargetDAGCombine(ISD::MUL); 361 362 setTargetDAGCombine(ISD::SELECT); 363 setTargetDAGCombine(ISD::VSELECT); 364 365 setTargetDAGCombine(ISD::INTRINSIC_VOID); 366 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); 367 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 368 369 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8; 370 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4; 371 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4; 372 373 setStackPointerRegisterToSaveRestore(AArch64::SP); 374 375 setSchedulingPreference(Sched::Hybrid); 376 377 // Enable TBZ/TBNZ 378 MaskAndBranchFoldingIsLegal = true; 379 380 setMinFunctionAlignment(2); 381 382 RequireStrictAlign = (Align == StrictAlign); 383 384 setHasExtractBitsInsn(true); 385 386 if (Subtarget->hasNEON()) { 387 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to 388 // silliness like this: 389 setOperationAction(ISD::FABS, MVT::v1f64, Expand); 390 setOperationAction(ISD::FADD, MVT::v1f64, Expand); 391 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand); 392 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand); 393 setOperationAction(ISD::FCOS, MVT::v1f64, Expand); 394 setOperationAction(ISD::FDIV, MVT::v1f64, Expand); 395 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand); 396 setOperationAction(ISD::FMA, MVT::v1f64, Expand); 397 setOperationAction(ISD::FMUL, MVT::v1f64, Expand); 398 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand); 399 setOperationAction(ISD::FNEG, MVT::v1f64, Expand); 400 setOperationAction(ISD::FPOW, MVT::v1f64, Expand); 401 setOperationAction(ISD::FREM, MVT::v1f64, Expand); 402 setOperationAction(ISD::FROUND, MVT::v1f64, Expand); 403 setOperationAction(ISD::FRINT, MVT::v1f64, Expand); 404 setOperationAction(ISD::FSIN, MVT::v1f64, Expand); 405 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand); 406 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand); 407 setOperationAction(ISD::FSUB, MVT::v1f64, Expand); 408 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand); 409 setOperationAction(ISD::SETCC, MVT::v1f64, Expand); 410 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand); 411 setOperationAction(ISD::SELECT, MVT::v1f64, Expand); 412 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand); 413 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand); 414 415 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand); 416 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand); 417 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); 418 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand); 419 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand); 420 421 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 422 423 // AArch64 doesn't have a direct vector ->f32 conversion instructions for 424 // elements smaller than i32, so promote the input to i32 first. 425 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote); 426 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote); 427 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote); 428 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote); 429 // Similarly, there is no direct i32 -> f64 vector conversion instruction. 430 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); 431 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom); 432 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom); 433 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom); 434 435 // AArch64 doesn't have MUL.2d: 436 setOperationAction(ISD::MUL, MVT::v2i64, Expand); 437 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal); 438 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand); 439 // Likewise, narrowing and extending vector loads/stores aren't handled 440 // directly. 441 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 442 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 443 444 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, 445 Expand); 446 447 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand); 448 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 449 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand); 450 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 451 452 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 453 454 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 455 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 456 setTruncStoreAction((MVT::SimpleValueType)VT, 457 (MVT::SimpleValueType)InnerVT, Expand); 458 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 459 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 460 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 461 } 462 463 // AArch64 has implementations of a lot of rounding-like FP operations. 464 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 }; 465 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) { 466 MVT Ty = RoundingVecTypes[I]; 467 setOperationAction(ISD::FFLOOR, Ty, Legal); 468 setOperationAction(ISD::FNEARBYINT, Ty, Legal); 469 setOperationAction(ISD::FCEIL, Ty, Legal); 470 setOperationAction(ISD::FRINT, Ty, Legal); 471 setOperationAction(ISD::FTRUNC, Ty, Legal); 472 setOperationAction(ISD::FROUND, Ty, Legal); 473 } 474 } 475} 476 477void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) { 478 if (VT == MVT::v2f32) { 479 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 480 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32); 481 482 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 483 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32); 484 } else if (VT == MVT::v2f64 || VT == MVT::v4f32) { 485 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 486 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64); 487 488 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 489 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64); 490 } 491 492 // Mark vector float intrinsics as expand. 493 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) { 494 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand); 495 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand); 496 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand); 497 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand); 498 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand); 499 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand); 500 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand); 501 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand); 502 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand); 503 } 504 505 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); 506 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom); 507 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); 508 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); 509 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom); 510 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); 511 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); 512 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); 513 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom); 514 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom); 515 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom); 516 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); 517 518 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand); 519 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); 520 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand); 521 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand); 522 523 // CNT supports only B element sizes. 524 if (VT != MVT::v8i8 && VT != MVT::v16i8) 525 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand); 526 527 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand); 528 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand); 529 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand); 530 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); 531 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand); 532 533 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom); 534 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom); 535 536 if (Subtarget->isLittleEndian()) { 537 for (unsigned im = (unsigned)ISD::PRE_INC; 538 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 539 setIndexedLoadAction(im, VT.getSimpleVT(), Legal); 540 setIndexedStoreAction(im, VT.getSimpleVT(), Legal); 541 } 542 } 543} 544 545void AArch64TargetLowering::addDRTypeForNEON(MVT VT) { 546 addRegisterClass(VT, &AArch64::FPR64RegClass); 547 addTypeForNEON(VT, MVT::v2i32); 548} 549 550void AArch64TargetLowering::addQRTypeForNEON(MVT VT) { 551 addRegisterClass(VT, &AArch64::FPR128RegClass); 552 addTypeForNEON(VT, MVT::v4i32); 553} 554 555EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 556 if (!VT.isVector()) 557 return MVT::i32; 558 return VT.changeVectorElementTypeToInteger(); 559} 560 561/// computeKnownBitsForTargetNode - Determine which of the bits specified in 562/// Mask are known to be either zero or one and return them in the 563/// KnownZero/KnownOne bitsets. 564void AArch64TargetLowering::computeKnownBitsForTargetNode( 565 const SDValue Op, APInt &KnownZero, APInt &KnownOne, 566 const SelectionDAG &DAG, unsigned Depth) const { 567 switch (Op.getOpcode()) { 568 default: 569 break; 570 case AArch64ISD::CSEL: { 571 APInt KnownZero2, KnownOne2; 572 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1); 573 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1); 574 KnownZero &= KnownZero2; 575 KnownOne &= KnownOne2; 576 break; 577 } 578 case ISD::INTRINSIC_W_CHAIN: { 579 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1)); 580 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue()); 581 switch (IntID) { 582 default: return; 583 case Intrinsic::aarch64_ldaxr: 584 case Intrinsic::aarch64_ldxr: { 585 unsigned BitWidth = KnownOne.getBitWidth(); 586 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT(); 587 unsigned MemBits = VT.getScalarType().getSizeInBits(); 588 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits); 589 return; 590 } 591 } 592 break; 593 } 594 case ISD::INTRINSIC_WO_CHAIN: 595 case ISD::INTRINSIC_VOID: { 596 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 597 switch (IntNo) { 598 default: 599 break; 600 case Intrinsic::aarch64_neon_umaxv: 601 case Intrinsic::aarch64_neon_uminv: { 602 // Figure out the datatype of the vector operand. The UMINV instruction 603 // will zero extend the result, so we can mark as known zero all the 604 // bits larger than the element datatype. 32-bit or larget doesn't need 605 // this as those are legal types and will be handled by isel directly. 606 MVT VT = Op.getOperand(1).getValueType().getSimpleVT(); 607 unsigned BitWidth = KnownZero.getBitWidth(); 608 if (VT == MVT::v8i8 || VT == MVT::v16i8) { 609 assert(BitWidth >= 8 && "Unexpected width!"); 610 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8); 611 KnownZero |= Mask; 612 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) { 613 assert(BitWidth >= 16 && "Unexpected width!"); 614 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16); 615 KnownZero |= Mask; 616 } 617 break; 618 } break; 619 } 620 } 621 } 622} 623 624MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const { 625 return MVT::i64; 626} 627 628unsigned AArch64TargetLowering::getMaximalGlobalOffset() const { 629 // FIXME: On AArch64, this depends on the type. 630 // Basically, the addressable offsets are o to 4095 * Ty.getSizeInBytes(). 631 // and the offset has to be a multiple of the related size in bytes. 632 return 4095; 633} 634 635FastISel * 636AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, 637 const TargetLibraryInfo *libInfo) const { 638 return AArch64::createFastISel(funcInfo, libInfo); 639} 640 641const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const { 642 switch (Opcode) { 643 default: 644 return nullptr; 645 case AArch64ISD::CALL: return "AArch64ISD::CALL"; 646 case AArch64ISD::ADRP: return "AArch64ISD::ADRP"; 647 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow"; 648 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot"; 649 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG"; 650 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND"; 651 case AArch64ISD::CSEL: return "AArch64ISD::CSEL"; 652 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL"; 653 case AArch64ISD::CSINV: return "AArch64ISD::CSINV"; 654 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG"; 655 case AArch64ISD::CSINC: return "AArch64ISD::CSINC"; 656 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER"; 657 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL"; 658 case AArch64ISD::ADC: return "AArch64ISD::ADC"; 659 case AArch64ISD::SBC: return "AArch64ISD::SBC"; 660 case AArch64ISD::ADDS: return "AArch64ISD::ADDS"; 661 case AArch64ISD::SUBS: return "AArch64ISD::SUBS"; 662 case AArch64ISD::ADCS: return "AArch64ISD::ADCS"; 663 case AArch64ISD::SBCS: return "AArch64ISD::SBCS"; 664 case AArch64ISD::ANDS: return "AArch64ISD::ANDS"; 665 case AArch64ISD::FCMP: return "AArch64ISD::FCMP"; 666 case AArch64ISD::FMIN: return "AArch64ISD::FMIN"; 667 case AArch64ISD::FMAX: return "AArch64ISD::FMAX"; 668 case AArch64ISD::DUP: return "AArch64ISD::DUP"; 669 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8"; 670 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16"; 671 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32"; 672 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64"; 673 case AArch64ISD::MOVI: return "AArch64ISD::MOVI"; 674 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift"; 675 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit"; 676 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl"; 677 case AArch64ISD::FMOV: return "AArch64ISD::FMOV"; 678 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift"; 679 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl"; 680 case AArch64ISD::BICi: return "AArch64ISD::BICi"; 681 case AArch64ISD::ORRi: return "AArch64ISD::ORRi"; 682 case AArch64ISD::BSL: return "AArch64ISD::BSL"; 683 case AArch64ISD::NEG: return "AArch64ISD::NEG"; 684 case AArch64ISD::EXTR: return "AArch64ISD::EXTR"; 685 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1"; 686 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2"; 687 case AArch64ISD::UZP1: return "AArch64ISD::UZP1"; 688 case AArch64ISD::UZP2: return "AArch64ISD::UZP2"; 689 case AArch64ISD::TRN1: return "AArch64ISD::TRN1"; 690 case AArch64ISD::TRN2: return "AArch64ISD::TRN2"; 691 case AArch64ISD::REV16: return "AArch64ISD::REV16"; 692 case AArch64ISD::REV32: return "AArch64ISD::REV32"; 693 case AArch64ISD::REV64: return "AArch64ISD::REV64"; 694 case AArch64ISD::EXT: return "AArch64ISD::EXT"; 695 case AArch64ISD::VSHL: return "AArch64ISD::VSHL"; 696 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR"; 697 case AArch64ISD::VASHR: return "AArch64ISD::VASHR"; 698 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ"; 699 case AArch64ISD::CMGE: return "AArch64ISD::CMGE"; 700 case AArch64ISD::CMGT: return "AArch64ISD::CMGT"; 701 case AArch64ISD::CMHI: return "AArch64ISD::CMHI"; 702 case AArch64ISD::CMHS: return "AArch64ISD::CMHS"; 703 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ"; 704 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE"; 705 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT"; 706 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz"; 707 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz"; 708 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz"; 709 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz"; 710 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz"; 711 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz"; 712 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz"; 713 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz"; 714 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz"; 715 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz"; 716 case AArch64ISD::NOT: return "AArch64ISD::NOT"; 717 case AArch64ISD::BIT: return "AArch64ISD::BIT"; 718 case AArch64ISD::CBZ: return "AArch64ISD::CBZ"; 719 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ"; 720 case AArch64ISD::TBZ: return "AArch64ISD::TBZ"; 721 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ"; 722 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN"; 723 case AArch64ISD::SITOF: return "AArch64ISD::SITOF"; 724 case AArch64ISD::UITOF: return "AArch64ISD::UITOF"; 725 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I"; 726 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I"; 727 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I"; 728 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I"; 729 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I"; 730 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge"; 731 case AArch64ISD::LD2post: return "AArch64ISD::LD2post"; 732 case AArch64ISD::LD3post: return "AArch64ISD::LD3post"; 733 case AArch64ISD::LD4post: return "AArch64ISD::LD4post"; 734 case AArch64ISD::ST2post: return "AArch64ISD::ST2post"; 735 case AArch64ISD::ST3post: return "AArch64ISD::ST3post"; 736 case AArch64ISD::ST4post: return "AArch64ISD::ST4post"; 737 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post"; 738 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post"; 739 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post"; 740 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post"; 741 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post"; 742 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post"; 743 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost"; 744 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost"; 745 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost"; 746 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost"; 747 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost"; 748 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost"; 749 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost"; 750 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost"; 751 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost"; 752 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost"; 753 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost"; 754 } 755} 756 757MachineBasicBlock * 758AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI, 759 MachineBasicBlock *MBB) const { 760 // We materialise the F128CSEL pseudo-instruction as some control flow and a 761 // phi node: 762 763 // OrigBB: 764 // [... previous instrs leading to comparison ...] 765 // b.ne TrueBB 766 // b EndBB 767 // TrueBB: 768 // ; Fallthrough 769 // EndBB: 770 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB] 771 772 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 773 MachineFunction *MF = MBB->getParent(); 774 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 775 DebugLoc DL = MI->getDebugLoc(); 776 MachineFunction::iterator It = MBB; 777 ++It; 778 779 unsigned DestReg = MI->getOperand(0).getReg(); 780 unsigned IfTrueReg = MI->getOperand(1).getReg(); 781 unsigned IfFalseReg = MI->getOperand(2).getReg(); 782 unsigned CondCode = MI->getOperand(3).getImm(); 783 bool NZCVKilled = MI->getOperand(4).isKill(); 784 785 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB); 786 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB); 787 MF->insert(It, TrueBB); 788 MF->insert(It, EndBB); 789 790 // Transfer rest of current basic-block to EndBB 791 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)), 792 MBB->end()); 793 EndBB->transferSuccessorsAndUpdatePHIs(MBB); 794 795 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB); 796 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB); 797 MBB->addSuccessor(TrueBB); 798 MBB->addSuccessor(EndBB); 799 800 // TrueBB falls through to the end. 801 TrueBB->addSuccessor(EndBB); 802 803 if (!NZCVKilled) { 804 TrueBB->addLiveIn(AArch64::NZCV); 805 EndBB->addLiveIn(AArch64::NZCV); 806 } 807 808 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg) 809 .addReg(IfTrueReg) 810 .addMBB(TrueBB) 811 .addReg(IfFalseReg) 812 .addMBB(MBB); 813 814 MI->eraseFromParent(); 815 return EndBB; 816} 817 818MachineBasicBlock * 819AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 820 MachineBasicBlock *BB) const { 821 switch (MI->getOpcode()) { 822 default: 823#ifndef NDEBUG 824 MI->dump(); 825#endif 826 assert(0 && "Unexpected instruction for custom inserter!"); 827 break; 828 829 case AArch64::F128CSEL: 830 return EmitF128CSEL(MI, BB); 831 832 case TargetOpcode::STACKMAP: 833 case TargetOpcode::PATCHPOINT: 834 return emitPatchPoint(MI, BB); 835 } 836 llvm_unreachable("Unexpected instruction for custom inserter!"); 837} 838 839//===----------------------------------------------------------------------===// 840// AArch64 Lowering private implementation. 841//===----------------------------------------------------------------------===// 842 843//===----------------------------------------------------------------------===// 844// Lowering Code 845//===----------------------------------------------------------------------===// 846 847/// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64 848/// CC 849static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) { 850 switch (CC) { 851 default: 852 llvm_unreachable("Unknown condition code!"); 853 case ISD::SETNE: 854 return AArch64CC::NE; 855 case ISD::SETEQ: 856 return AArch64CC::EQ; 857 case ISD::SETGT: 858 return AArch64CC::GT; 859 case ISD::SETGE: 860 return AArch64CC::GE; 861 case ISD::SETLT: 862 return AArch64CC::LT; 863 case ISD::SETLE: 864 return AArch64CC::LE; 865 case ISD::SETUGT: 866 return AArch64CC::HI; 867 case ISD::SETUGE: 868 return AArch64CC::HS; 869 case ISD::SETULT: 870 return AArch64CC::LO; 871 case ISD::SETULE: 872 return AArch64CC::LS; 873 } 874} 875 876/// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC. 877static void changeFPCCToAArch64CC(ISD::CondCode CC, 878 AArch64CC::CondCode &CondCode, 879 AArch64CC::CondCode &CondCode2) { 880 CondCode2 = AArch64CC::AL; 881 switch (CC) { 882 default: 883 llvm_unreachable("Unknown FP condition!"); 884 case ISD::SETEQ: 885 case ISD::SETOEQ: 886 CondCode = AArch64CC::EQ; 887 break; 888 case ISD::SETGT: 889 case ISD::SETOGT: 890 CondCode = AArch64CC::GT; 891 break; 892 case ISD::SETGE: 893 case ISD::SETOGE: 894 CondCode = AArch64CC::GE; 895 break; 896 case ISD::SETOLT: 897 CondCode = AArch64CC::MI; 898 break; 899 case ISD::SETOLE: 900 CondCode = AArch64CC::LS; 901 break; 902 case ISD::SETONE: 903 CondCode = AArch64CC::MI; 904 CondCode2 = AArch64CC::GT; 905 break; 906 case ISD::SETO: 907 CondCode = AArch64CC::VC; 908 break; 909 case ISD::SETUO: 910 CondCode = AArch64CC::VS; 911 break; 912 case ISD::SETUEQ: 913 CondCode = AArch64CC::EQ; 914 CondCode2 = AArch64CC::VS; 915 break; 916 case ISD::SETUGT: 917 CondCode = AArch64CC::HI; 918 break; 919 case ISD::SETUGE: 920 CondCode = AArch64CC::PL; 921 break; 922 case ISD::SETLT: 923 case ISD::SETULT: 924 CondCode = AArch64CC::LT; 925 break; 926 case ISD::SETLE: 927 case ISD::SETULE: 928 CondCode = AArch64CC::LE; 929 break; 930 case ISD::SETNE: 931 case ISD::SETUNE: 932 CondCode = AArch64CC::NE; 933 break; 934 } 935} 936 937/// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 938/// CC usable with the vector instructions. Fewer operations are available 939/// without a real NZCV register, so we have to use less efficient combinations 940/// to get the same effect. 941static void changeVectorFPCCToAArch64CC(ISD::CondCode CC, 942 AArch64CC::CondCode &CondCode, 943 AArch64CC::CondCode &CondCode2, 944 bool &Invert) { 945 Invert = false; 946 switch (CC) { 947 default: 948 // Mostly the scalar mappings work fine. 949 changeFPCCToAArch64CC(CC, CondCode, CondCode2); 950 break; 951 case ISD::SETUO: 952 Invert = true; // Fallthrough 953 case ISD::SETO: 954 CondCode = AArch64CC::MI; 955 CondCode2 = AArch64CC::GE; 956 break; 957 case ISD::SETUEQ: 958 case ISD::SETULT: 959 case ISD::SETULE: 960 case ISD::SETUGT: 961 case ISD::SETUGE: 962 // All of the compare-mask comparisons are ordered, but we can switch 963 // between the two by a double inversion. E.g. ULE == !OGT. 964 Invert = true; 965 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2); 966 break; 967 } 968} 969 970static bool isLegalArithImmed(uint64_t C) { 971 // Matches AArch64DAGToDAGISel::SelectArithImmed(). 972 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0); 973} 974 975static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, 976 SDLoc dl, SelectionDAG &DAG) { 977 EVT VT = LHS.getValueType(); 978 979 if (VT.isFloatingPoint()) 980 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS); 981 982 // The CMP instruction is just an alias for SUBS, and representing it as 983 // SUBS means that it's possible to get CSE with subtract operations. 984 // A later phase can perform the optimization of setting the destination 985 // register to WZR/XZR if it ends up being unused. 986 unsigned Opcode = AArch64ISD::SUBS; 987 988 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) && 989 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 && 990 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 991 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on 992 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags 993 // can be set differently by this operation. It comes down to whether 994 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then 995 // everything is fine. If not then the optimization is wrong. Thus general 996 // comparisons are only valid if op2 != 0. 997 998 // So, finally, the only LLVM-native comparisons that don't mention C and V 999 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in 1000 // the absence of information about op2. 1001 Opcode = AArch64ISD::ADDS; 1002 RHS = RHS.getOperand(1); 1003 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) && 1004 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 && 1005 !isUnsignedIntSetCC(CC)) { 1006 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST 1007 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one 1008 // of the signed comparisons. 1009 Opcode = AArch64ISD::ANDS; 1010 RHS = LHS.getOperand(1); 1011 LHS = LHS.getOperand(0); 1012 } 1013 1014 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS) 1015 .getValue(1); 1016} 1017 1018static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 1019 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) { 1020 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 1021 EVT VT = RHS.getValueType(); 1022 uint64_t C = RHSC->getZExtValue(); 1023 if (!isLegalArithImmed(C)) { 1024 // Constant does not fit, try adjusting it by one? 1025 switch (CC) { 1026 default: 1027 break; 1028 case ISD::SETLT: 1029 case ISD::SETGE: 1030 if ((VT == MVT::i32 && C != 0x80000000 && 1031 isLegalArithImmed((uint32_t)(C - 1))) || 1032 (VT == MVT::i64 && C != 0x80000000ULL && 1033 isLegalArithImmed(C - 1ULL))) { 1034 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 1035 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1; 1036 RHS = DAG.getConstant(C, VT); 1037 } 1038 break; 1039 case ISD::SETULT: 1040 case ISD::SETUGE: 1041 if ((VT == MVT::i32 && C != 0 && 1042 isLegalArithImmed((uint32_t)(C - 1))) || 1043 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) { 1044 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 1045 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1; 1046 RHS = DAG.getConstant(C, VT); 1047 } 1048 break; 1049 case ISD::SETLE: 1050 case ISD::SETGT: 1051 if ((VT == MVT::i32 && C != 0x7fffffff && 1052 isLegalArithImmed((uint32_t)(C + 1))) || 1053 (VT == MVT::i64 && C != 0x7ffffffffffffffULL && 1054 isLegalArithImmed(C + 1ULL))) { 1055 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 1056 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1; 1057 RHS = DAG.getConstant(C, VT); 1058 } 1059 break; 1060 case ISD::SETULE: 1061 case ISD::SETUGT: 1062 if ((VT == MVT::i32 && C != 0xffffffff && 1063 isLegalArithImmed((uint32_t)(C + 1))) || 1064 (VT == MVT::i64 && C != 0xfffffffffffffffULL && 1065 isLegalArithImmed(C + 1ULL))) { 1066 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1067 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1; 1068 RHS = DAG.getConstant(C, VT); 1069 } 1070 break; 1071 } 1072 } 1073 } 1074 1075 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG); 1076 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC); 1077 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32); 1078 return Cmp; 1079} 1080 1081static std::pair<SDValue, SDValue> 1082getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) { 1083 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) && 1084 "Unsupported value type"); 1085 SDValue Value, Overflow; 1086 SDLoc DL(Op); 1087 SDValue LHS = Op.getOperand(0); 1088 SDValue RHS = Op.getOperand(1); 1089 unsigned Opc = 0; 1090 switch (Op.getOpcode()) { 1091 default: 1092 llvm_unreachable("Unknown overflow instruction!"); 1093 case ISD::SADDO: 1094 Opc = AArch64ISD::ADDS; 1095 CC = AArch64CC::VS; 1096 break; 1097 case ISD::UADDO: 1098 Opc = AArch64ISD::ADDS; 1099 CC = AArch64CC::HS; 1100 break; 1101 case ISD::SSUBO: 1102 Opc = AArch64ISD::SUBS; 1103 CC = AArch64CC::VS; 1104 break; 1105 case ISD::USUBO: 1106 Opc = AArch64ISD::SUBS; 1107 CC = AArch64CC::LO; 1108 break; 1109 // Multiply needs a little bit extra work. 1110 case ISD::SMULO: 1111 case ISD::UMULO: { 1112 CC = AArch64CC::NE; 1113 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false; 1114 if (Op.getValueType() == MVT::i32) { 1115 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 1116 // For a 32 bit multiply with overflow check we want the instruction 1117 // selector to generate a widening multiply (SMADDL/UMADDL). For that we 1118 // need to generate the following pattern: 1119 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b)) 1120 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS); 1121 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS); 1122 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS); 1123 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul, 1124 DAG.getConstant(0, MVT::i64)); 1125 // On AArch64 the upper 32 bits are always zero extended for a 32 bit 1126 // operation. We need to clear out the upper 32 bits, because we used a 1127 // widening multiply that wrote all 64 bits. In the end this should be a 1128 // noop. 1129 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add); 1130 if (IsSigned) { 1131 // The signed overflow check requires more than just a simple check for 1132 // any bit set in the upper 32 bits of the result. These bits could be 1133 // just the sign bits of a negative number. To perform the overflow 1134 // check we have to arithmetic shift right the 32nd bit of the result by 1135 // 31 bits. Then we compare the result to the upper 32 bits. 1136 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add, 1137 DAG.getConstant(32, MVT::i64)); 1138 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits); 1139 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value, 1140 DAG.getConstant(31, MVT::i64)); 1141 // It is important that LowerBits is last, otherwise the arithmetic 1142 // shift will not be folded into the compare (SUBS). 1143 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32); 1144 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits) 1145 .getValue(1); 1146 } else { 1147 // The overflow check for unsigned multiply is easy. We only need to 1148 // check if any of the upper 32 bits are set. This can be done with a 1149 // CMP (shifted register). For that we need to generate the following 1150 // pattern: 1151 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32) 1152 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, 1153 DAG.getConstant(32, MVT::i64)); 1154 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32); 1155 Overflow = 1156 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64), 1157 UpperBits).getValue(1); 1158 } 1159 break; 1160 } 1161 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type"); 1162 // For the 64 bit multiply 1163 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS); 1164 if (IsSigned) { 1165 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS); 1166 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value, 1167 DAG.getConstant(63, MVT::i64)); 1168 // It is important that LowerBits is last, otherwise the arithmetic 1169 // shift will not be folded into the compare (SUBS). 1170 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32); 1171 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits) 1172 .getValue(1); 1173 } else { 1174 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS); 1175 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32); 1176 Overflow = 1177 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64), 1178 UpperBits).getValue(1); 1179 } 1180 break; 1181 } 1182 } // switch (...) 1183 1184 if (Opc) { 1185 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32); 1186 1187 // Emit the AArch64 operation with overflow check. 1188 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS); 1189 Overflow = Value.getValue(1); 1190 } 1191 return std::make_pair(Value, Overflow); 1192} 1193 1194SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG, 1195 RTLIB::Libcall Call) const { 1196 SmallVector<SDValue, 2> Ops; 1197 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) 1198 Ops.push_back(Op.getOperand(i)); 1199 1200 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false, 1201 SDLoc(Op)).first; 1202} 1203 1204static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) { 1205 SDValue Sel = Op.getOperand(0); 1206 SDValue Other = Op.getOperand(1); 1207 1208 // If neither operand is a SELECT_CC, give up. 1209 if (Sel.getOpcode() != ISD::SELECT_CC) 1210 std::swap(Sel, Other); 1211 if (Sel.getOpcode() != ISD::SELECT_CC) 1212 return Op; 1213 1214 // The folding we want to perform is: 1215 // (xor x, (select_cc a, b, cc, 0, -1) ) 1216 // --> 1217 // (csel x, (xor x, -1), cc ...) 1218 // 1219 // The latter will get matched to a CSINV instruction. 1220 1221 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get(); 1222 SDValue LHS = Sel.getOperand(0); 1223 SDValue RHS = Sel.getOperand(1); 1224 SDValue TVal = Sel.getOperand(2); 1225 SDValue FVal = Sel.getOperand(3); 1226 SDLoc dl(Sel); 1227 1228 // FIXME: This could be generalized to non-integer comparisons. 1229 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64) 1230 return Op; 1231 1232 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal); 1233 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal); 1234 1235 // The the values aren't constants, this isn't the pattern we're looking for. 1236 if (!CFVal || !CTVal) 1237 return Op; 1238 1239 // We can commute the SELECT_CC by inverting the condition. This 1240 // might be needed to make this fit into a CSINV pattern. 1241 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) { 1242 std::swap(TVal, FVal); 1243 std::swap(CTVal, CFVal); 1244 CC = ISD::getSetCCInverse(CC, true); 1245 } 1246 1247 // If the constants line up, perform the transform! 1248 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) { 1249 SDValue CCVal; 1250 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl); 1251 1252 FVal = Other; 1253 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other, 1254 DAG.getConstant(-1ULL, Other.getValueType())); 1255 1256 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal, 1257 CCVal, Cmp); 1258 } 1259 1260 return Op; 1261} 1262 1263static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 1264 EVT VT = Op.getValueType(); 1265 1266 // Let legalize expand this if it isn't a legal type yet. 1267 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 1268 return SDValue(); 1269 1270 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 1271 1272 unsigned Opc; 1273 bool ExtraOp = false; 1274 switch (Op.getOpcode()) { 1275 default: 1276 assert(0 && "Invalid code"); 1277 case ISD::ADDC: 1278 Opc = AArch64ISD::ADDS; 1279 break; 1280 case ISD::SUBC: 1281 Opc = AArch64ISD::SUBS; 1282 break; 1283 case ISD::ADDE: 1284 Opc = AArch64ISD::ADCS; 1285 ExtraOp = true; 1286 break; 1287 case ISD::SUBE: 1288 Opc = AArch64ISD::SBCS; 1289 ExtraOp = true; 1290 break; 1291 } 1292 1293 if (!ExtraOp) 1294 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1)); 1295 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1), 1296 Op.getOperand(2)); 1297} 1298 1299static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) { 1300 // Let legalize expand this if it isn't a legal type yet. 1301 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType())) 1302 return SDValue(); 1303 1304 AArch64CC::CondCode CC; 1305 // The actual operation that sets the overflow or carry flag. 1306 SDValue Value, Overflow; 1307 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG); 1308 1309 // We use 0 and 1 as false and true values. 1310 SDValue TVal = DAG.getConstant(1, MVT::i32); 1311 SDValue FVal = DAG.getConstant(0, MVT::i32); 1312 1313 // We use an inverted condition, because the conditional select is inverted 1314 // too. This will allow it to be selected to a single instruction: 1315 // CSINC Wd, WZR, WZR, invert(cond). 1316 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32); 1317 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal, 1318 CCVal, Overflow); 1319 1320 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 1321 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow); 1322} 1323 1324// Prefetch operands are: 1325// 1: Address to prefetch 1326// 2: bool isWrite 1327// 3: int locality (0 = no locality ... 3 = extreme locality) 1328// 4: bool isDataCache 1329static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) { 1330 SDLoc DL(Op); 1331 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 1332 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 1333 // The data thing is not used. 1334 // unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 1335 1336 bool IsStream = !Locality; 1337 // When the locality number is set 1338 if (Locality) { 1339 // The front-end should have filtered out the out-of-range values 1340 assert(Locality <= 3 && "Prefetch locality out-of-range"); 1341 // The locality degree is the opposite of the cache speed. 1342 // Put the number the other way around. 1343 // The encoding starts at 0 for level 1 1344 Locality = 3 - Locality; 1345 } 1346 1347 // built the mask value encoding the expected behavior. 1348 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit 1349 (Locality << 1) | // Cache level bits 1350 (unsigned)IsStream; // Stream bit 1351 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0), 1352 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1)); 1353} 1354 1355SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op, 1356 SelectionDAG &DAG) const { 1357 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering"); 1358 1359 RTLIB::Libcall LC; 1360 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType()); 1361 1362 return LowerF128Call(Op, DAG, LC); 1363} 1364 1365SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op, 1366 SelectionDAG &DAG) const { 1367 if (Op.getOperand(0).getValueType() != MVT::f128) { 1368 // It's legal except when f128 is involved 1369 return Op; 1370 } 1371 1372 RTLIB::Libcall LC; 1373 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType()); 1374 1375 // FP_ROUND node has a second operand indicating whether it is known to be 1376 // precise. That doesn't take part in the LibCall so we can't directly use 1377 // LowerF128Call. 1378 SDValue SrcVal = Op.getOperand(0); 1379 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1, 1380 /*isSigned*/ false, SDLoc(Op)).first; 1381} 1382 1383static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 1384 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp. 1385 // Any additional optimization in this function should be recorded 1386 // in the cost tables. 1387 EVT InVT = Op.getOperand(0).getValueType(); 1388 EVT VT = Op.getValueType(); 1389 1390 // FP_TO_XINT conversion from the same type are legal. 1391 if (VT.getSizeInBits() == InVT.getSizeInBits()) 1392 return Op; 1393 1394 if (InVT == MVT::v2f64 || InVT == MVT::v4f32) { 1395 SDLoc dl(Op); 1396 SDValue Cv = 1397 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(), 1398 Op.getOperand(0)); 1399 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv); 1400 } else if (InVT == MVT::v2f32) { 1401 SDLoc dl(Op); 1402 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Op.getOperand(0)); 1403 return DAG.getNode(Op.getOpcode(), dl, VT, Ext); 1404 } 1405 1406 // Type changing conversions are illegal. 1407 return SDValue(); 1408} 1409 1410SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op, 1411 SelectionDAG &DAG) const { 1412 if (Op.getOperand(0).getValueType().isVector()) 1413 return LowerVectorFP_TO_INT(Op, DAG); 1414 1415 if (Op.getOperand(0).getValueType() != MVT::f128) { 1416 // It's legal except when f128 is involved 1417 return Op; 1418 } 1419 1420 RTLIB::Libcall LC; 1421 if (Op.getOpcode() == ISD::FP_TO_SINT) 1422 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType()); 1423 else 1424 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType()); 1425 1426 SmallVector<SDValue, 2> Ops; 1427 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) 1428 Ops.push_back(Op.getOperand(i)); 1429 1430 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false, 1431 SDLoc(Op)).first; 1432} 1433 1434static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 1435 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp. 1436 // Any additional optimization in this function should be recorded 1437 // in the cost tables. 1438 EVT VT = Op.getValueType(); 1439 SDLoc dl(Op); 1440 SDValue In = Op.getOperand(0); 1441 EVT InVT = In.getValueType(); 1442 1443 // v2i32 to v2f32 is legal. 1444 if (VT == MVT::v2f32 && InVT == MVT::v2i32) 1445 return Op; 1446 1447 // This function only handles v2f64 outputs. 1448 if (VT == MVT::v2f64) { 1449 // Extend the input argument to a v2i64 that we can feed into the 1450 // floating point conversion. Zero or sign extend based on whether 1451 // we're doing a signed or unsigned float conversion. 1452 unsigned Opc = 1453 Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; 1454 assert(Op.getNumOperands() == 1 && "FP conversions take one argument"); 1455 SDValue Promoted = DAG.getNode(Opc, dl, MVT::v2i64, Op.getOperand(0)); 1456 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Promoted); 1457 } 1458 1459 // Scalarize v2i64 to v2f32 conversions. 1460 std::vector<SDValue> BuildVectorOps; 1461 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) { 1462 SDValue Sclr = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, In, 1463 DAG.getConstant(i, MVT::i64)); 1464 Sclr = DAG.getNode(Op->getOpcode(), dl, MVT::f32, Sclr); 1465 BuildVectorOps.push_back(Sclr); 1466 } 1467 1468 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, BuildVectorOps); 1469} 1470 1471SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op, 1472 SelectionDAG &DAG) const { 1473 if (Op.getValueType().isVector()) 1474 return LowerVectorINT_TO_FP(Op, DAG); 1475 1476 // i128 conversions are libcalls. 1477 if (Op.getOperand(0).getValueType() == MVT::i128) 1478 return SDValue(); 1479 1480 // Other conversions are legal, unless it's to the completely software-based 1481 // fp128. 1482 if (Op.getValueType() != MVT::f128) 1483 return Op; 1484 1485 RTLIB::Libcall LC; 1486 if (Op.getOpcode() == ISD::SINT_TO_FP) 1487 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType()); 1488 else 1489 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType()); 1490 1491 return LowerF128Call(Op, DAG, LC); 1492} 1493 1494SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op, 1495 SelectionDAG &DAG) const { 1496 // For iOS, we want to call an alternative entry point: __sincos_stret, 1497 // which returns the values in two S / D registers. 1498 SDLoc dl(Op); 1499 SDValue Arg = Op.getOperand(0); 1500 EVT ArgVT = Arg.getValueType(); 1501 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1502 1503 ArgListTy Args; 1504 ArgListEntry Entry; 1505 1506 Entry.Node = Arg; 1507 Entry.Ty = ArgTy; 1508 Entry.isSExt = false; 1509 Entry.isZExt = false; 1510 Args.push_back(Entry); 1511 1512 const char *LibcallName = 1513 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret"; 1514 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy()); 1515 1516 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL); 1517 TargetLowering::CallLoweringInfo CLI(DAG); 1518 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) 1519 .setCallee(CallingConv::Fast, RetTy, Callee, &Args, 0); 1520 1521 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1522 return CallResult.first; 1523} 1524 1525SDValue AArch64TargetLowering::LowerOperation(SDValue Op, 1526 SelectionDAG &DAG) const { 1527 switch (Op.getOpcode()) { 1528 default: 1529 llvm_unreachable("unimplemented operand"); 1530 return SDValue(); 1531 case ISD::GlobalAddress: 1532 return LowerGlobalAddress(Op, DAG); 1533 case ISD::GlobalTLSAddress: 1534 return LowerGlobalTLSAddress(Op, DAG); 1535 case ISD::SETCC: 1536 return LowerSETCC(Op, DAG); 1537 case ISD::BR_CC: 1538 return LowerBR_CC(Op, DAG); 1539 case ISD::SELECT: 1540 return LowerSELECT(Op, DAG); 1541 case ISD::SELECT_CC: 1542 return LowerSELECT_CC(Op, DAG); 1543 case ISD::JumpTable: 1544 return LowerJumpTable(Op, DAG); 1545 case ISD::ConstantPool: 1546 return LowerConstantPool(Op, DAG); 1547 case ISD::BlockAddress: 1548 return LowerBlockAddress(Op, DAG); 1549 case ISD::VASTART: 1550 return LowerVASTART(Op, DAG); 1551 case ISD::VACOPY: 1552 return LowerVACOPY(Op, DAG); 1553 case ISD::VAARG: 1554 return LowerVAARG(Op, DAG); 1555 case ISD::ADDC: 1556 case ISD::ADDE: 1557 case ISD::SUBC: 1558 case ISD::SUBE: 1559 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 1560 case ISD::SADDO: 1561 case ISD::UADDO: 1562 case ISD::SSUBO: 1563 case ISD::USUBO: 1564 case ISD::SMULO: 1565 case ISD::UMULO: 1566 return LowerXALUO(Op, DAG); 1567 case ISD::FADD: 1568 return LowerF128Call(Op, DAG, RTLIB::ADD_F128); 1569 case ISD::FSUB: 1570 return LowerF128Call(Op, DAG, RTLIB::SUB_F128); 1571 case ISD::FMUL: 1572 return LowerF128Call(Op, DAG, RTLIB::MUL_F128); 1573 case ISD::FDIV: 1574 return LowerF128Call(Op, DAG, RTLIB::DIV_F128); 1575 case ISD::FP_ROUND: 1576 return LowerFP_ROUND(Op, DAG); 1577 case ISD::FP_EXTEND: 1578 return LowerFP_EXTEND(Op, DAG); 1579 case ISD::FRAMEADDR: 1580 return LowerFRAMEADDR(Op, DAG); 1581 case ISD::RETURNADDR: 1582 return LowerRETURNADDR(Op, DAG); 1583 case ISD::INSERT_VECTOR_ELT: 1584 return LowerINSERT_VECTOR_ELT(Op, DAG); 1585 case ISD::EXTRACT_VECTOR_ELT: 1586 return LowerEXTRACT_VECTOR_ELT(Op, DAG); 1587 case ISD::BUILD_VECTOR: 1588 return LowerBUILD_VECTOR(Op, DAG); 1589 case ISD::VECTOR_SHUFFLE: 1590 return LowerVECTOR_SHUFFLE(Op, DAG); 1591 case ISD::EXTRACT_SUBVECTOR: 1592 return LowerEXTRACT_SUBVECTOR(Op, DAG); 1593 case ISD::SRA: 1594 case ISD::SRL: 1595 case ISD::SHL: 1596 return LowerVectorSRA_SRL_SHL(Op, DAG); 1597 case ISD::SHL_PARTS: 1598 return LowerShiftLeftParts(Op, DAG); 1599 case ISD::SRL_PARTS: 1600 case ISD::SRA_PARTS: 1601 return LowerShiftRightParts(Op, DAG); 1602 case ISD::CTPOP: 1603 return LowerCTPOP(Op, DAG); 1604 case ISD::FCOPYSIGN: 1605 return LowerFCOPYSIGN(Op, DAG); 1606 case ISD::AND: 1607 return LowerVectorAND(Op, DAG); 1608 case ISD::OR: 1609 return LowerVectorOR(Op, DAG); 1610 case ISD::XOR: 1611 return LowerXOR(Op, DAG); 1612 case ISD::PREFETCH: 1613 return LowerPREFETCH(Op, DAG); 1614 case ISD::SINT_TO_FP: 1615 case ISD::UINT_TO_FP: 1616 return LowerINT_TO_FP(Op, DAG); 1617 case ISD::FP_TO_SINT: 1618 case ISD::FP_TO_UINT: 1619 return LowerFP_TO_INT(Op, DAG); 1620 case ISD::FSINCOS: 1621 return LowerFSINCOS(Op, DAG); 1622 } 1623} 1624 1625/// getFunctionAlignment - Return the Log2 alignment of this function. 1626unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const { 1627 return 2; 1628} 1629 1630//===----------------------------------------------------------------------===// 1631// Calling Convention Implementation 1632//===----------------------------------------------------------------------===// 1633 1634#include "AArch64GenCallingConv.inc" 1635 1636/// Selects the correct CCAssignFn for a the given CallingConvention 1637/// value. 1638CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC, 1639 bool IsVarArg) const { 1640 switch (CC) { 1641 default: 1642 llvm_unreachable("Unsupported calling convention."); 1643 case CallingConv::WebKit_JS: 1644 return CC_AArch64_WebKit_JS; 1645 case CallingConv::C: 1646 case CallingConv::Fast: 1647 if (!Subtarget->isTargetDarwin()) 1648 return CC_AArch64_AAPCS; 1649 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS; 1650 } 1651} 1652 1653SDValue AArch64TargetLowering::LowerFormalArguments( 1654 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1655 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, 1656 SmallVectorImpl<SDValue> &InVals) const { 1657 MachineFunction &MF = DAG.getMachineFunction(); 1658 MachineFrameInfo *MFI = MF.getFrameInfo(); 1659 1660 // Assign locations to all of the incoming arguments. 1661 SmallVector<CCValAssign, 16> ArgLocs; 1662 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1663 getTargetMachine(), ArgLocs, *DAG.getContext()); 1664 1665 // At this point, Ins[].VT may already be promoted to i32. To correctly 1666 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and 1667 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT. 1668 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here 1669 // we use a special version of AnalyzeFormalArguments to pass in ValVT and 1670 // LocVT. 1671 unsigned NumArgs = Ins.size(); 1672 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin(); 1673 unsigned CurArgIdx = 0; 1674 for (unsigned i = 0; i != NumArgs; ++i) { 1675 MVT ValVT = Ins[i].VT; 1676 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx); 1677 CurArgIdx = Ins[i].OrigArgIndex; 1678 1679 // Get type of the original argument. 1680 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true); 1681 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other; 1682 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16. 1683 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8) 1684 ValVT = MVT::i8; 1685 else if (ActualMVT == MVT::i16) 1686 ValVT = MVT::i16; 1687 1688 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false); 1689 bool Res = 1690 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo); 1691 assert(!Res && "Call operand has unhandled type"); 1692 (void)Res; 1693 } 1694 assert(ArgLocs.size() == Ins.size()); 1695 SmallVector<SDValue, 16> ArgValues; 1696 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1697 CCValAssign &VA = ArgLocs[i]; 1698 1699 if (Ins[i].Flags.isByVal()) { 1700 // Byval is used for HFAs in the PCS, but the system should work in a 1701 // non-compliant manner for larger structs. 1702 EVT PtrTy = getPointerTy(); 1703 int Size = Ins[i].Flags.getByValSize(); 1704 unsigned NumRegs = (Size + 7) / 8; 1705 1706 // FIXME: This works on big-endian for composite byvals, which are the common 1707 // case. It should also work for fundamental types too. 1708 unsigned FrameIdx = 1709 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false); 1710 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy); 1711 InVals.push_back(FrameIdxN); 1712 1713 continue; 1714 } if (VA.isRegLoc()) { 1715 // Arguments stored in registers. 1716 EVT RegVT = VA.getLocVT(); 1717 1718 SDValue ArgValue; 1719 const TargetRegisterClass *RC; 1720 1721 if (RegVT == MVT::i32) 1722 RC = &AArch64::GPR32RegClass; 1723 else if (RegVT == MVT::i64) 1724 RC = &AArch64::GPR64RegClass; 1725 else if (RegVT == MVT::f32) 1726 RC = &AArch64::FPR32RegClass; 1727 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) 1728 RC = &AArch64::FPR64RegClass; 1729 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) 1730 RC = &AArch64::FPR128RegClass; 1731 else 1732 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 1733 1734 // Transform the arguments in physical registers into virtual ones. 1735 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1736 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 1737 1738 // If this is an 8, 16 or 32-bit value, it is really passed promoted 1739 // to 64 bits. Insert an assert[sz]ext to capture this, then 1740 // truncate to the right size. 1741 switch (VA.getLocInfo()) { 1742 default: 1743 llvm_unreachable("Unknown loc info!"); 1744 case CCValAssign::Full: 1745 break; 1746 case CCValAssign::BCvt: 1747 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue); 1748 break; 1749 case CCValAssign::AExt: 1750 case CCValAssign::SExt: 1751 case CCValAssign::ZExt: 1752 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt 1753 // nodes after our lowering. 1754 assert(RegVT == Ins[i].VT && "incorrect register location selected"); 1755 break; 1756 } 1757 1758 InVals.push_back(ArgValue); 1759 1760 } else { // VA.isRegLoc() 1761 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem"); 1762 unsigned ArgOffset = VA.getLocMemOffset(); 1763 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1764 1765 uint32_t BEAlign = 0; 1766 if (ArgSize < 8 && !Subtarget->isLittleEndian()) 1767 BEAlign = 8 - ArgSize; 1768 1769 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true); 1770 1771 // Create load nodes to retrieve arguments from the stack. 1772 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1773 SDValue ArgValue; 1774 1775 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 1776 switch (VA.getLocInfo()) { 1777 default: 1778 break; 1779 case CCValAssign::SExt: 1780 ExtType = ISD::SEXTLOAD; 1781 break; 1782 case CCValAssign::ZExt: 1783 ExtType = ISD::ZEXTLOAD; 1784 break; 1785 case CCValAssign::AExt: 1786 ExtType = ISD::EXTLOAD; 1787 break; 1788 } 1789 1790 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getValVT(), Chain, FIN, 1791 MachinePointerInfo::getFixedStack(FI), 1792 VA.getLocVT(), 1793 false, false, false, 0); 1794 1795 InVals.push_back(ArgValue); 1796 } 1797 } 1798 1799 // varargs 1800 if (isVarArg) { 1801 if (!Subtarget->isTargetDarwin()) { 1802 // The AAPCS variadic function ABI is identical to the non-variadic 1803 // one. As a result there may be more arguments in registers and we should 1804 // save them for future reference. 1805 saveVarArgRegisters(CCInfo, DAG, DL, Chain); 1806 } 1807 1808 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); 1809 // This will point to the next argument passed via stack. 1810 unsigned StackOffset = CCInfo.getNextStackOffset(); 1811 // We currently pass all varargs at 8-byte alignment. 1812 StackOffset = ((StackOffset + 7) & ~7); 1813 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true)); 1814 } 1815 1816 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>(); 1817 unsigned StackArgSize = CCInfo.getNextStackOffset(); 1818 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt; 1819 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) { 1820 // This is a non-standard ABI so by fiat I say we're allowed to make full 1821 // use of the stack area to be popped, which must be aligned to 16 bytes in 1822 // any case: 1823 StackArgSize = RoundUpToAlignment(StackArgSize, 16); 1824 1825 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding 1826 // a multiple of 16. 1827 FuncInfo->setArgumentStackToRestore(StackArgSize); 1828 1829 // This realignment carries over to the available bytes below. Our own 1830 // callers will guarantee the space is free by giving an aligned value to 1831 // CALLSEQ_START. 1832 } 1833 // Even if we're not expected to free up the space, it's useful to know how 1834 // much is there while considering tail calls (because we can reuse it). 1835 FuncInfo->setBytesInStackArgArea(StackArgSize); 1836 1837 return Chain; 1838} 1839 1840void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo, 1841 SelectionDAG &DAG, SDLoc DL, 1842 SDValue &Chain) const { 1843 MachineFunction &MF = DAG.getMachineFunction(); 1844 MachineFrameInfo *MFI = MF.getFrameInfo(); 1845 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>(); 1846 1847 SmallVector<SDValue, 8> MemOps; 1848 1849 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2, 1850 AArch64::X3, AArch64::X4, AArch64::X5, 1851 AArch64::X6, AArch64::X7 }; 1852 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs); 1853 unsigned FirstVariadicGPR = 1854 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs); 1855 1856 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR); 1857 int GPRIdx = 0; 1858 if (GPRSaveSize != 0) { 1859 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false); 1860 1861 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy()); 1862 1863 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) { 1864 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass); 1865 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); 1866 SDValue Store = 1867 DAG.getStore(Val.getValue(1), DL, Val, FIN, 1868 MachinePointerInfo::getStack(i * 8), false, false, 0); 1869 MemOps.push_back(Store); 1870 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN, 1871 DAG.getConstant(8, getPointerTy())); 1872 } 1873 } 1874 FuncInfo->setVarArgsGPRIndex(GPRIdx); 1875 FuncInfo->setVarArgsGPRSize(GPRSaveSize); 1876 1877 if (Subtarget->hasFPARMv8()) { 1878 static const MCPhysReg FPRArgRegs[] = { 1879 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, 1880 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7}; 1881 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs); 1882 unsigned FirstVariadicFPR = 1883 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs); 1884 1885 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR); 1886 int FPRIdx = 0; 1887 if (FPRSaveSize != 0) { 1888 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false); 1889 1890 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy()); 1891 1892 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) { 1893 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass); 1894 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128); 1895 1896 SDValue Store = 1897 DAG.getStore(Val.getValue(1), DL, Val, FIN, 1898 MachinePointerInfo::getStack(i * 16), false, false, 0); 1899 MemOps.push_back(Store); 1900 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN, 1901 DAG.getConstant(16, getPointerTy())); 1902 } 1903 } 1904 FuncInfo->setVarArgsFPRIndex(FPRIdx); 1905 FuncInfo->setVarArgsFPRSize(FPRSaveSize); 1906 } 1907 1908 if (!MemOps.empty()) { 1909 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); 1910 } 1911} 1912 1913/// LowerCallResult - Lower the result values of a call into the 1914/// appropriate copies out of appropriate physical registers. 1915SDValue AArch64TargetLowering::LowerCallResult( 1916 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, 1917 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, 1918 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 1919 SDValue ThisVal) const { 1920 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS 1921 ? RetCC_AArch64_WebKit_JS 1922 : RetCC_AArch64_AAPCS; 1923 // Assign locations to each value returned by this call. 1924 SmallVector<CCValAssign, 16> RVLocs; 1925 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1926 getTargetMachine(), RVLocs, *DAG.getContext()); 1927 CCInfo.AnalyzeCallResult(Ins, RetCC); 1928 1929 // Copy all of the result registers out of their specified physreg. 1930 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1931 CCValAssign VA = RVLocs[i]; 1932 1933 // Pass 'this' value directly from the argument to return value, to avoid 1934 // reg unit interference 1935 if (i == 0 && isThisReturn) { 1936 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 && 1937 "unexpected return calling convention register assignment"); 1938 InVals.push_back(ThisVal); 1939 continue; 1940 } 1941 1942 SDValue Val = 1943 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag); 1944 Chain = Val.getValue(1); 1945 InFlag = Val.getValue(2); 1946 1947 switch (VA.getLocInfo()) { 1948 default: 1949 llvm_unreachable("Unknown loc info!"); 1950 case CCValAssign::Full: 1951 break; 1952 case CCValAssign::BCvt: 1953 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 1954 break; 1955 } 1956 1957 InVals.push_back(Val); 1958 } 1959 1960 return Chain; 1961} 1962 1963bool AArch64TargetLowering::isEligibleForTailCallOptimization( 1964 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 1965 bool isCalleeStructRet, bool isCallerStructRet, 1966 const SmallVectorImpl<ISD::OutputArg> &Outs, 1967 const SmallVectorImpl<SDValue> &OutVals, 1968 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const { 1969 // For CallingConv::C this function knows whether the ABI needs 1970 // changing. That's not true for other conventions so they will have to opt in 1971 // manually. 1972 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1973 return false; 1974 1975 const MachineFunction &MF = DAG.getMachineFunction(); 1976 const Function *CallerF = MF.getFunction(); 1977 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1978 bool CCMatch = CallerCC == CalleeCC; 1979 1980 // Byval parameters hand the function a pointer directly into the stack area 1981 // we want to reuse during a tail call. Working around this *is* possible (see 1982 // X86) but less efficient and uglier in LowerCall. 1983 for (Function::const_arg_iterator i = CallerF->arg_begin(), 1984 e = CallerF->arg_end(); 1985 i != e; ++i) 1986 if (i->hasByValAttr()) 1987 return false; 1988 1989 if (getTargetMachine().Options.GuaranteedTailCallOpt) { 1990 if (IsTailCallConvention(CalleeCC) && CCMatch) 1991 return true; 1992 return false; 1993 } 1994 1995 // Now we search for cases where we can use a tail call without changing the 1996 // ABI. Sibcall is used in some places (particularly gcc) to refer to this 1997 // concept. 1998 1999 // I want anyone implementing a new calling convention to think long and hard 2000 // about this assert. 2001 assert((!isVarArg || CalleeCC == CallingConv::C) && 2002 "Unexpected variadic calling convention"); 2003 2004 if (isVarArg && !Outs.empty()) { 2005 // At least two cases here: if caller is fastcc then we can't have any 2006 // memory arguments (we'd be expected to clean up the stack afterwards). If 2007 // caller is C then we could potentially use its argument area. 2008 2009 // FIXME: for now we take the most conservative of these in both cases: 2010 // disallow all variadic memory operands. 2011 SmallVector<CCValAssign, 16> ArgLocs; 2012 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2013 getTargetMachine(), ArgLocs, *DAG.getContext()); 2014 2015 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true)); 2016 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2017 if (!ArgLocs[i].isRegLoc()) 2018 return false; 2019 } 2020 2021 // If the calling conventions do not match, then we'd better make sure the 2022 // results are returned in the same way as what the caller expects. 2023 if (!CCMatch) { 2024 SmallVector<CCValAssign, 16> RVLocs1; 2025 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2026 getTargetMachine(), RVLocs1, *DAG.getContext()); 2027 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg)); 2028 2029 SmallVector<CCValAssign, 16> RVLocs2; 2030 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2031 getTargetMachine(), RVLocs2, *DAG.getContext()); 2032 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg)); 2033 2034 if (RVLocs1.size() != RVLocs2.size()) 2035 return false; 2036 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2037 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2038 return false; 2039 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2040 return false; 2041 if (RVLocs1[i].isRegLoc()) { 2042 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2043 return false; 2044 } else { 2045 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2046 return false; 2047 } 2048 } 2049 } 2050 2051 // Nothing more to check if the callee is taking no arguments 2052 if (Outs.empty()) 2053 return true; 2054 2055 SmallVector<CCValAssign, 16> ArgLocs; 2056 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2057 getTargetMachine(), ArgLocs, *DAG.getContext()); 2058 2059 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg)); 2060 2061 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>(); 2062 2063 // If the stack arguments for this call would fit into our own save area then 2064 // the call can be made tail. 2065 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea(); 2066} 2067 2068SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain, 2069 SelectionDAG &DAG, 2070 MachineFrameInfo *MFI, 2071 int ClobberedFI) const { 2072 SmallVector<SDValue, 8> ArgChains; 2073 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI); 2074 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1; 2075 2076 // Include the original chain at the beginning of the list. When this is 2077 // used by target LowerCall hooks, this helps legalize find the 2078 // CALLSEQ_BEGIN node. 2079 ArgChains.push_back(Chain); 2080 2081 // Add a chain value for each stack argument corresponding 2082 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(), 2083 UE = DAG.getEntryNode().getNode()->use_end(); 2084 U != UE; ++U) 2085 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U)) 2086 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr())) 2087 if (FI->getIndex() < 0) { 2088 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex()); 2089 int64_t InLastByte = InFirstByte; 2090 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1; 2091 2092 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) || 2093 (FirstByte <= InFirstByte && InFirstByte <= LastByte)) 2094 ArgChains.push_back(SDValue(L, 1)); 2095 } 2096 2097 // Build a tokenfactor for all the chains. 2098 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains); 2099} 2100 2101bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC, 2102 bool TailCallOpt) const { 2103 return CallCC == CallingConv::Fast && TailCallOpt; 2104} 2105 2106bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const { 2107 return CallCC == CallingConv::Fast; 2108} 2109 2110/// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain, 2111/// and add input and output parameter nodes. 2112SDValue 2113AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, 2114 SmallVectorImpl<SDValue> &InVals) const { 2115 SelectionDAG &DAG = CLI.DAG; 2116 SDLoc &DL = CLI.DL; 2117 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 2118 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 2119 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 2120 SDValue Chain = CLI.Chain; 2121 SDValue Callee = CLI.Callee; 2122 bool &IsTailCall = CLI.IsTailCall; 2123 CallingConv::ID CallConv = CLI.CallConv; 2124 bool IsVarArg = CLI.IsVarArg; 2125 2126 MachineFunction &MF = DAG.getMachineFunction(); 2127 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 2128 bool IsThisReturn = false; 2129 2130 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>(); 2131 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt; 2132 bool IsSibCall = false; 2133 2134 if (IsTailCall) { 2135 // Check if it's really possible to do a tail call. 2136 IsTailCall = isEligibleForTailCallOptimization( 2137 Callee, CallConv, IsVarArg, IsStructRet, 2138 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG); 2139 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall()) 2140 report_fatal_error("failed to perform tail call elimination on a call " 2141 "site marked musttail"); 2142 2143 // A sibling call is one where we're under the usual C ABI and not planning 2144 // to change that but can still do a tail call: 2145 if (!TailCallOpt && IsTailCall) 2146 IsSibCall = true; 2147 2148 if (IsTailCall) 2149 ++NumTailCalls; 2150 } 2151 2152 // Analyze operands of the call, assigning locations to each operand. 2153 SmallVector<CCValAssign, 16> ArgLocs; 2154 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2155 getTargetMachine(), ArgLocs, *DAG.getContext()); 2156 2157 if (IsVarArg) { 2158 // Handle fixed and variable vector arguments differently. 2159 // Variable vector arguments always go into memory. 2160 unsigned NumArgs = Outs.size(); 2161 2162 for (unsigned i = 0; i != NumArgs; ++i) { 2163 MVT ArgVT = Outs[i].VT; 2164 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2165 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, 2166 /*IsVarArg=*/ !Outs[i].IsFixed); 2167 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 2168 assert(!Res && "Call operand has unhandled type"); 2169 (void)Res; 2170 } 2171 } else { 2172 // At this point, Outs[].VT may already be promoted to i32. To correctly 2173 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and 2174 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT. 2175 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here 2176 // we use a special version of AnalyzeCallOperands to pass in ValVT and 2177 // LocVT. 2178 unsigned NumArgs = Outs.size(); 2179 for (unsigned i = 0; i != NumArgs; ++i) { 2180 MVT ValVT = Outs[i].VT; 2181 // Get type of the original argument. 2182 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty, 2183 /*AllowUnknown*/ true); 2184 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT; 2185 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2186 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16. 2187 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8) 2188 ValVT = MVT::i8; 2189 else if (ActualMVT == MVT::i16) 2190 ValVT = MVT::i16; 2191 2192 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false); 2193 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo); 2194 assert(!Res && "Call operand has unhandled type"); 2195 (void)Res; 2196 } 2197 } 2198 2199 // Get a count of how many bytes are to be pushed on the stack. 2200 unsigned NumBytes = CCInfo.getNextStackOffset(); 2201 2202 if (IsSibCall) { 2203 // Since we're not changing the ABI to make this a tail call, the memory 2204 // operands are already available in the caller's incoming argument space. 2205 NumBytes = 0; 2206 } 2207 2208 // FPDiff is the byte offset of the call's argument area from the callee's. 2209 // Stores to callee stack arguments will be placed in FixedStackSlots offset 2210 // by this amount for a tail call. In a sibling call it must be 0 because the 2211 // caller will deallocate the entire stack and the callee still expects its 2212 // arguments to begin at SP+0. Completely unused for non-tail calls. 2213 int FPDiff = 0; 2214 2215 if (IsTailCall && !IsSibCall) { 2216 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea(); 2217 2218 // Since callee will pop argument stack as a tail call, we must keep the 2219 // popped size 16-byte aligned. 2220 NumBytes = RoundUpToAlignment(NumBytes, 16); 2221 2222 // FPDiff will be negative if this tail call requires more space than we 2223 // would automatically have in our incoming argument space. Positive if we 2224 // can actually shrink the stack. 2225 FPDiff = NumReusableBytes - NumBytes; 2226 2227 // The stack pointer must be 16-byte aligned at all times it's used for a 2228 // memory operation, which in practice means at *all* times and in 2229 // particular across call boundaries. Therefore our own arguments started at 2230 // a 16-byte aligned SP and the delta applied for the tail call should 2231 // satisfy the same constraint. 2232 assert(FPDiff % 16 == 0 && "unaligned stack on tail call"); 2233 } 2234 2235 // Adjust the stack pointer for the new arguments... 2236 // These operations are automatically eliminated by the prolog/epilog pass 2237 if (!IsSibCall) 2238 Chain = 2239 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL); 2240 2241 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy()); 2242 2243 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2244 SmallVector<SDValue, 8> MemOpChains; 2245 2246 // Walk the register/memloc assignments, inserting copies/loads. 2247 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e; 2248 ++i, ++realArgIdx) { 2249 CCValAssign &VA = ArgLocs[i]; 2250 SDValue Arg = OutVals[realArgIdx]; 2251 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 2252 2253 // Promote the value if needed. 2254 switch (VA.getLocInfo()) { 2255 default: 2256 llvm_unreachable("Unknown loc info!"); 2257 case CCValAssign::Full: 2258 break; 2259 case CCValAssign::SExt: 2260 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); 2261 break; 2262 case CCValAssign::ZExt: 2263 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); 2264 break; 2265 case CCValAssign::AExt: 2266 if (Outs[realArgIdx].ArgVT == MVT::i1) { 2267 // AAPCS requires i1 to be zero-extended to 8-bits by the caller. 2268 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg); 2269 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg); 2270 } 2271 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); 2272 break; 2273 case CCValAssign::BCvt: 2274 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); 2275 break; 2276 case CCValAssign::FPExt: 2277 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg); 2278 break; 2279 } 2280 2281 if (VA.isRegLoc()) { 2282 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) { 2283 assert(VA.getLocVT() == MVT::i64 && 2284 "unexpected calling convention register assignment"); 2285 assert(!Ins.empty() && Ins[0].VT == MVT::i64 && 2286 "unexpected use of 'returned'"); 2287 IsThisReturn = true; 2288 } 2289 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2290 } else { 2291 assert(VA.isMemLoc()); 2292 2293 SDValue DstAddr; 2294 MachinePointerInfo DstInfo; 2295 2296 // FIXME: This works on big-endian for composite byvals, which are the 2297 // common case. It should also work for fundamental types too. 2298 uint32_t BEAlign = 0; 2299 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8 2300 : VA.getLocVT().getSizeInBits(); 2301 OpSize = (OpSize + 7) / 8; 2302 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) { 2303 if (OpSize < 8) 2304 BEAlign = 8 - OpSize; 2305 } 2306 unsigned LocMemOffset = VA.getLocMemOffset(); 2307 int32_t Offset = LocMemOffset + BEAlign; 2308 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 2309 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff); 2310 2311 if (IsTailCall) { 2312 Offset = Offset + FPDiff; 2313 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2314 2315 DstAddr = DAG.getFrameIndex(FI, getPointerTy()); 2316 DstInfo = MachinePointerInfo::getFixedStack(FI); 2317 2318 // Make sure any stack arguments overlapping with where we're storing 2319 // are loaded before this eventual operation. Otherwise they'll be 2320 // clobbered. 2321 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI); 2322 } else { 2323 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 2324 2325 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff); 2326 DstInfo = MachinePointerInfo::getStack(LocMemOffset); 2327 } 2328 2329 if (Outs[i].Flags.isByVal()) { 2330 SDValue SizeNode = 2331 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64); 2332 SDValue Cpy = DAG.getMemcpy( 2333 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(), 2334 /*isVolatile = */ false, 2335 /*alwaysInline = */ false, DstInfo, MachinePointerInfo()); 2336 2337 MemOpChains.push_back(Cpy); 2338 } else { 2339 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already 2340 // promoted to a legal register type i32, we should truncate Arg back to 2341 // i1/i8/i16. 2342 if (Arg.getValueType().isSimple() && 2343 Arg.getValueType().getSimpleVT() == MVT::i32 && 2344 (VA.getLocVT() == MVT::i1 || VA.getLocVT() == MVT::i8 || 2345 VA.getLocVT() == MVT::i16)) 2346 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getLocVT(), Arg); 2347 2348 SDValue Store = 2349 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0); 2350 MemOpChains.push_back(Store); 2351 } 2352 } 2353 } 2354 2355 if (!MemOpChains.empty()) 2356 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 2357 2358 // Build a sequence of copy-to-reg nodes chained together with token chain 2359 // and flag operands which copy the outgoing args into the appropriate regs. 2360 SDValue InFlag; 2361 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2362 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first, 2363 RegsToPass[i].second, InFlag); 2364 InFlag = Chain.getValue(1); 2365 } 2366 2367 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2368 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2369 // node so that legalize doesn't hack it. 2370 if (getTargetMachine().getCodeModel() == CodeModel::Large && 2371 Subtarget->isTargetMachO()) { 2372 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2373 const GlobalValue *GV = G->getGlobal(); 2374 bool InternalLinkage = GV->hasInternalLinkage(); 2375 if (InternalLinkage) 2376 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0); 2377 else { 2378 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 2379 AArch64II::MO_GOT); 2380 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee); 2381 } 2382 } else if (ExternalSymbolSDNode *S = 2383 dyn_cast<ExternalSymbolSDNode>(Callee)) { 2384 const char *Sym = S->getSymbol(); 2385 Callee = 2386 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT); 2387 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee); 2388 } 2389 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2390 const GlobalValue *GV = G->getGlobal(); 2391 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0); 2392 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2393 const char *Sym = S->getSymbol(); 2394 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0); 2395 } 2396 2397 // We don't usually want to end the call-sequence here because we would tidy 2398 // the frame up *after* the call, however in the ABI-changing tail-call case 2399 // we've carefully laid out the parameters so that when sp is reset they'll be 2400 // in the correct location. 2401 if (IsTailCall && !IsSibCall) { 2402 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2403 DAG.getIntPtrConstant(0, true), InFlag, DL); 2404 InFlag = Chain.getValue(1); 2405 } 2406 2407 std::vector<SDValue> Ops; 2408 Ops.push_back(Chain); 2409 Ops.push_back(Callee); 2410 2411 if (IsTailCall) { 2412 // Each tail call may have to adjust the stack by a different amount, so 2413 // this information must travel along with the operation for eventual 2414 // consumption by emitEpilogue. 2415 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32)); 2416 } 2417 2418 // Add argument registers to the end of the list so that they are known live 2419 // into the call. 2420 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2421 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2422 RegsToPass[i].second.getValueType())); 2423 2424 // Add a register mask operand representing the call-preserved registers. 2425 const uint32_t *Mask; 2426 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2427 const AArch64RegisterInfo *ARI = 2428 static_cast<const AArch64RegisterInfo *>(TRI); 2429 if (IsThisReturn) { 2430 // For 'this' returns, use the X0-preserving mask if applicable 2431 Mask = ARI->getThisReturnPreservedMask(CallConv); 2432 if (!Mask) { 2433 IsThisReturn = false; 2434 Mask = ARI->getCallPreservedMask(CallConv); 2435 } 2436 } else 2437 Mask = ARI->getCallPreservedMask(CallConv); 2438 2439 assert(Mask && "Missing call preserved mask for calling convention"); 2440 Ops.push_back(DAG.getRegisterMask(Mask)); 2441 2442 if (InFlag.getNode()) 2443 Ops.push_back(InFlag); 2444 2445 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2446 2447 // If we're doing a tall call, use a TC_RETURN here rather than an 2448 // actual call instruction. 2449 if (IsTailCall) 2450 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops); 2451 2452 // Returns a chain and a flag for retval copy to use. 2453 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops); 2454 InFlag = Chain.getValue(1); 2455 2456 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt) 2457 ? RoundUpToAlignment(NumBytes, 16) 2458 : 0; 2459 2460 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2461 DAG.getIntPtrConstant(CalleePopBytes, true), 2462 InFlag, DL); 2463 if (!Ins.empty()) 2464 InFlag = Chain.getValue(1); 2465 2466 // Handle result values, copying them out of physregs into vregs that we 2467 // return. 2468 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, 2469 InVals, IsThisReturn, 2470 IsThisReturn ? OutVals[0] : SDValue()); 2471} 2472 2473bool AArch64TargetLowering::CanLowerReturn( 2474 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, 2475 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { 2476 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS 2477 ? RetCC_AArch64_WebKit_JS 2478 : RetCC_AArch64_AAPCS; 2479 SmallVector<CCValAssign, 16> RVLocs; 2480 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); 2481 return CCInfo.CheckReturn(Outs, RetCC); 2482} 2483 2484SDValue 2485AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 2486 bool isVarArg, 2487 const SmallVectorImpl<ISD::OutputArg> &Outs, 2488 const SmallVectorImpl<SDValue> &OutVals, 2489 SDLoc DL, SelectionDAG &DAG) const { 2490 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS 2491 ? RetCC_AArch64_WebKit_JS 2492 : RetCC_AArch64_AAPCS; 2493 SmallVector<CCValAssign, 16> RVLocs; 2494 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2495 getTargetMachine(), RVLocs, *DAG.getContext()); 2496 CCInfo.AnalyzeReturn(Outs, RetCC); 2497 2498 // Copy the result values into the output registers. 2499 SDValue Flag; 2500 SmallVector<SDValue, 4> RetOps(1, Chain); 2501 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size(); 2502 ++i, ++realRVLocIdx) { 2503 CCValAssign &VA = RVLocs[i]; 2504 assert(VA.isRegLoc() && "Can only return in registers!"); 2505 SDValue Arg = OutVals[realRVLocIdx]; 2506 2507 switch (VA.getLocInfo()) { 2508 default: 2509 llvm_unreachable("Unknown loc info!"); 2510 case CCValAssign::Full: 2511 if (Outs[i].ArgVT == MVT::i1) { 2512 // AAPCS requires i1 to be zero-extended to i8 by the producer of the 2513 // value. This is strictly redundant on Darwin (which uses "zeroext 2514 // i1"), but will be optimised out before ISel. 2515 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg); 2516 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); 2517 } 2518 break; 2519 case CCValAssign::BCvt: 2520 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); 2521 break; 2522 } 2523 2524 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); 2525 Flag = Chain.getValue(1); 2526 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 2527 } 2528 2529 RetOps[0] = Chain; // Update chain. 2530 2531 // Add the flag if we have it. 2532 if (Flag.getNode()) 2533 RetOps.push_back(Flag); 2534 2535 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps); 2536} 2537 2538//===----------------------------------------------------------------------===// 2539// Other Lowering Code 2540//===----------------------------------------------------------------------===// 2541 2542SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op, 2543 SelectionDAG &DAG) const { 2544 EVT PtrVT = getPointerTy(); 2545 SDLoc DL(Op); 2546 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2547 unsigned char OpFlags = 2548 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 2549 2550 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 && 2551 "unexpected offset in global node"); 2552 2553 // This also catched the large code model case for Darwin. 2554 if ((OpFlags & AArch64II::MO_GOT) != 0) { 2555 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags); 2556 // FIXME: Once remat is capable of dealing with instructions with register 2557 // operands, expand this into two nodes instead of using a wrapper node. 2558 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr); 2559 } 2560 2561 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2562 const unsigned char MO_NC = AArch64II::MO_NC; 2563 return DAG.getNode( 2564 AArch64ISD::WrapperLarge, DL, PtrVT, 2565 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3), 2566 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC), 2567 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC), 2568 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC)); 2569 } else { 2570 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and 2571 // the only correct model on Darwin. 2572 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 2573 OpFlags | AArch64II::MO_PAGE); 2574 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC; 2575 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags); 2576 2577 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi); 2578 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo); 2579 } 2580} 2581 2582/// \brief Convert a TLS address reference into the correct sequence of loads 2583/// and calls to compute the variable's address (for Darwin, currently) and 2584/// return an SDValue containing the final node. 2585 2586/// Darwin only has one TLS scheme which must be capable of dealing with the 2587/// fully general situation, in the worst case. This means: 2588/// + "extern __thread" declaration. 2589/// + Defined in a possibly unknown dynamic library. 2590/// 2591/// The general system is that each __thread variable has a [3 x i64] descriptor 2592/// which contains information used by the runtime to calculate the address. The 2593/// only part of this the compiler needs to know about is the first xword, which 2594/// contains a function pointer that must be called with the address of the 2595/// entire descriptor in "x0". 2596/// 2597/// Since this descriptor may be in a different unit, in general even the 2598/// descriptor must be accessed via an indirect load. The "ideal" code sequence 2599/// is: 2600/// adrp x0, _var@TLVPPAGE 2601/// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor 2602/// ldr x1, [x0] ; x1 contains 1st entry of descriptor, 2603/// ; the function pointer 2604/// blr x1 ; Uses descriptor address in x0 2605/// ; Address of _var is now in x0. 2606/// 2607/// If the address of _var's descriptor *is* known to the linker, then it can 2608/// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for 2609/// a slight efficiency gain. 2610SDValue 2611AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op, 2612 SelectionDAG &DAG) const { 2613 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin"); 2614 2615 SDLoc DL(Op); 2616 MVT PtrVT = getPointerTy(); 2617 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2618 2619 SDValue TLVPAddr = 2620 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS); 2621 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr); 2622 2623 // The first entry in the descriptor is a function pointer that we must call 2624 // to obtain the address of the variable. 2625 SDValue Chain = DAG.getEntryNode(); 2626 SDValue FuncTLVGet = 2627 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(), 2628 false, true, true, 8); 2629 Chain = FuncTLVGet.getValue(1); 2630 2631 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2632 MFI->setAdjustsStack(true); 2633 2634 // TLS calls preserve all registers except those that absolutely must be 2635 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be 2636 // silly). 2637 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2638 const AArch64RegisterInfo *ARI = 2639 static_cast<const AArch64RegisterInfo *>(TRI); 2640 const uint32_t *Mask = ARI->getTLSCallPreservedMask(); 2641 2642 // Finally, we can make the call. This is just a degenerate version of a 2643 // normal AArch64 call node: x0 takes the address of the descriptor, and 2644 // returns the address of the variable in this thread. 2645 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue()); 2646 Chain = 2647 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue), 2648 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64), 2649 DAG.getRegisterMask(Mask), Chain.getValue(1)); 2650 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1)); 2651} 2652 2653/// When accessing thread-local variables under either the general-dynamic or 2654/// local-dynamic system, we make a "TLS-descriptor" call. The variable will 2655/// have a descriptor, accessible via a PC-relative ADRP, and whose first entry 2656/// is a function pointer to carry out the resolution. This function takes the 2657/// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All 2658/// other registers (except LR, NZCV) are preserved. 2659/// 2660/// Thus, the ideal call sequence on AArch64 is: 2661/// 2662/// adrp x0, :tlsdesc:thread_var 2663/// ldr x8, [x0, :tlsdesc_lo12:thread_var] 2664/// add x0, x0, :tlsdesc_lo12:thread_var 2665/// .tlsdesccall thread_var 2666/// blr x8 2667/// (TPIDR_EL0 offset now in x0). 2668/// 2669/// The ".tlsdesccall" directive instructs the assembler to insert a particular 2670/// relocation to help the linker relax this sequence if it turns out to be too 2671/// conservative. 2672/// 2673/// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this 2674/// is harmless. 2675SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr, 2676 SDValue DescAddr, SDLoc DL, 2677 SelectionDAG &DAG) const { 2678 EVT PtrVT = getPointerTy(); 2679 2680 // The function we need to call is simply the first entry in the GOT for this 2681 // descriptor, load it in preparation. 2682 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr); 2683 2684 // TLS calls preserve all registers except those that absolutely must be 2685 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be 2686 // silly). 2687 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2688 const AArch64RegisterInfo *ARI = 2689 static_cast<const AArch64RegisterInfo *>(TRI); 2690 const uint32_t *Mask = ARI->getTLSCallPreservedMask(); 2691 2692 // The function takes only one argument: the address of the descriptor itself 2693 // in X0. 2694 SDValue Glue, Chain; 2695 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue); 2696 Glue = Chain.getValue(1); 2697 2698 // We're now ready to populate the argument list, as with a normal call: 2699 SmallVector<SDValue, 6> Ops; 2700 Ops.push_back(Chain); 2701 Ops.push_back(Func); 2702 Ops.push_back(SymAddr); 2703 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT)); 2704 Ops.push_back(DAG.getRegisterMask(Mask)); 2705 Ops.push_back(Glue); 2706 2707 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2708 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops); 2709 Glue = Chain.getValue(1); 2710 2711 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue); 2712} 2713 2714SDValue 2715AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op, 2716 SelectionDAG &DAG) const { 2717 assert(Subtarget->isTargetELF() && "This function expects an ELF target"); 2718 assert(getTargetMachine().getCodeModel() == CodeModel::Small && 2719 "ELF TLS only supported in small memory model"); 2720 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2721 2722 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal()); 2723 2724 SDValue TPOff; 2725 EVT PtrVT = getPointerTy(); 2726 SDLoc DL(Op); 2727 const GlobalValue *GV = GA->getGlobal(); 2728 2729 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT); 2730 2731 if (Model == TLSModel::LocalExec) { 2732 SDValue HiVar = DAG.getTargetGlobalAddress( 2733 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1); 2734 SDValue LoVar = DAG.getTargetGlobalAddress( 2735 GV, DL, PtrVT, 0, 2736 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC); 2737 2738 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar, 2739 DAG.getTargetConstant(16, MVT::i32)), 2740 0); 2741 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar, 2742 DAG.getTargetConstant(0, MVT::i32)), 2743 0); 2744 } else if (Model == TLSModel::InitialExec) { 2745 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS); 2746 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff); 2747 } else if (Model == TLSModel::LocalDynamic) { 2748 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS 2749 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate 2750 // the beginning of the module's TLS region, followed by a DTPREL offset 2751 // calculation. 2752 2753 // These accesses will need deduplicating if there's more than one. 2754 AArch64FunctionInfo *MFI = 2755 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>(); 2756 MFI->incNumLocalDynamicTLSAccesses(); 2757 2758 // Accesses used in this sequence go via the TLS descriptor which lives in 2759 // the GOT. Prepare an address we can use to handle this. 2760 SDValue HiDesc = DAG.getTargetExternalSymbol( 2761 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE); 2762 SDValue LoDesc = DAG.getTargetExternalSymbol( 2763 "_TLS_MODULE_BASE_", PtrVT, 2764 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC); 2765 2766 // First argument to the descriptor call is the address of the descriptor 2767 // itself. 2768 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc); 2769 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc); 2770 2771 // The call needs a relocation too for linker relaxation. It doesn't make 2772 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of 2773 // the address. 2774 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT, 2775 AArch64II::MO_TLS); 2776 2777 // Now we can calculate the offset from TPIDR_EL0 to this module's 2778 // thread-local area. 2779 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG); 2780 2781 // Now use :dtprel_whatever: operations to calculate this variable's offset 2782 // in its thread-storage area. 2783 SDValue HiVar = DAG.getTargetGlobalAddress( 2784 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1); 2785 SDValue LoVar = DAG.getTargetGlobalAddress( 2786 GV, DL, MVT::i64, 0, 2787 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC); 2788 2789 SDValue DTPOff = 2790 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar, 2791 DAG.getTargetConstant(16, MVT::i32)), 2792 0); 2793 DTPOff = 2794 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar, 2795 DAG.getTargetConstant(0, MVT::i32)), 2796 0); 2797 2798 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff); 2799 } else if (Model == TLSModel::GeneralDynamic) { 2800 // Accesses used in this sequence go via the TLS descriptor which lives in 2801 // the GOT. Prepare an address we can use to handle this. 2802 SDValue HiDesc = DAG.getTargetGlobalAddress( 2803 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE); 2804 SDValue LoDesc = DAG.getTargetGlobalAddress( 2805 GV, DL, PtrVT, 0, 2806 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC); 2807 2808 // First argument to the descriptor call is the address of the descriptor 2809 // itself. 2810 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc); 2811 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc); 2812 2813 // The call needs a relocation too for linker relaxation. It doesn't make 2814 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of 2815 // the address. 2816 SDValue SymAddr = 2817 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS); 2818 2819 // Finally we can make a call to calculate the offset from tpidr_el0. 2820 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG); 2821 } else 2822 llvm_unreachable("Unsupported ELF TLS access model"); 2823 2824 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff); 2825} 2826 2827SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op, 2828 SelectionDAG &DAG) const { 2829 if (Subtarget->isTargetDarwin()) 2830 return LowerDarwinGlobalTLSAddress(Op, DAG); 2831 else if (Subtarget->isTargetELF()) 2832 return LowerELFGlobalTLSAddress(Op, DAG); 2833 2834 llvm_unreachable("Unexpected platform trying to use TLS"); 2835} 2836SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 2837 SDValue Chain = Op.getOperand(0); 2838 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2839 SDValue LHS = Op.getOperand(2); 2840 SDValue RHS = Op.getOperand(3); 2841 SDValue Dest = Op.getOperand(4); 2842 SDLoc dl(Op); 2843 2844 // Handle f128 first, since lowering it will result in comparing the return 2845 // value of a libcall against zero, which is just what the rest of LowerBR_CC 2846 // is expecting to deal with. 2847 if (LHS.getValueType() == MVT::f128) { 2848 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl); 2849 2850 // If softenSetCCOperands returned a scalar, we need to compare the result 2851 // against zero to select between true and false values. 2852 if (!RHS.getNode()) { 2853 RHS = DAG.getConstant(0, LHS.getValueType()); 2854 CC = ISD::SETNE; 2855 } 2856 } 2857 2858 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch 2859 // instruction. 2860 unsigned Opc = LHS.getOpcode(); 2861 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) && 2862 cast<ConstantSDNode>(RHS)->isOne() && 2863 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || 2864 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { 2865 assert((CC == ISD::SETEQ || CC == ISD::SETNE) && 2866 "Unexpected condition code."); 2867 // Only lower legal XALUO ops. 2868 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0))) 2869 return SDValue(); 2870 2871 // The actual operation with overflow check. 2872 AArch64CC::CondCode OFCC; 2873 SDValue Value, Overflow; 2874 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG); 2875 2876 if (CC == ISD::SETNE) 2877 OFCC = getInvertedCondCode(OFCC); 2878 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32); 2879 2880 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest, 2881 CCVal, Overflow); 2882 } 2883 2884 if (LHS.getValueType().isInteger()) { 2885 assert((LHS.getValueType() == RHS.getValueType()) && 2886 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64)); 2887 2888 // If the RHS of the comparison is zero, we can potentially fold this 2889 // to a specialized branch. 2890 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS); 2891 if (RHSC && RHSC->getZExtValue() == 0) { 2892 if (CC == ISD::SETEQ) { 2893 // See if we can use a TBZ to fold in an AND as well. 2894 // TBZ has a smaller branch displacement than CBZ. If the offset is 2895 // out of bounds, a late MI-layer pass rewrites branches. 2896 // 403.gcc is an example that hits this case. 2897 if (LHS.getOpcode() == ISD::AND && 2898 isa<ConstantSDNode>(LHS.getOperand(1)) && 2899 isPowerOf2_64(LHS.getConstantOperandVal(1))) { 2900 SDValue Test = LHS.getOperand(0); 2901 uint64_t Mask = LHS.getConstantOperandVal(1); 2902 2903 // TBZ only operates on i64's, but the ext should be free. 2904 if (Test.getValueType() == MVT::i32) 2905 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64); 2906 2907 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test, 2908 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest); 2909 } 2910 2911 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest); 2912 } else if (CC == ISD::SETNE) { 2913 // See if we can use a TBZ to fold in an AND as well. 2914 // TBZ has a smaller branch displacement than CBZ. If the offset is 2915 // out of bounds, a late MI-layer pass rewrites branches. 2916 // 403.gcc is an example that hits this case. 2917 if (LHS.getOpcode() == ISD::AND && 2918 isa<ConstantSDNode>(LHS.getOperand(1)) && 2919 isPowerOf2_64(LHS.getConstantOperandVal(1))) { 2920 SDValue Test = LHS.getOperand(0); 2921 uint64_t Mask = LHS.getConstantOperandVal(1); 2922 2923 // TBNZ only operates on i64's, but the ext should be free. 2924 if (Test.getValueType() == MVT::i32) 2925 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64); 2926 2927 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test, 2928 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest); 2929 } 2930 2931 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest); 2932 } 2933 } 2934 2935 SDValue CCVal; 2936 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl); 2937 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, 2938 Cmp); 2939 } 2940 2941 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 2942 2943 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally 2944 // clean. Some of them require two branches to implement. 2945 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG); 2946 AArch64CC::CondCode CC1, CC2; 2947 changeFPCCToAArch64CC(CC, CC1, CC2); 2948 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32); 2949 SDValue BR1 = 2950 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp); 2951 if (CC2 != AArch64CC::AL) { 2952 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32); 2953 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val, 2954 Cmp); 2955 } 2956 2957 return BR1; 2958} 2959 2960SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op, 2961 SelectionDAG &DAG) const { 2962 EVT VT = Op.getValueType(); 2963 SDLoc DL(Op); 2964 2965 SDValue In1 = Op.getOperand(0); 2966 SDValue In2 = Op.getOperand(1); 2967 EVT SrcVT = In2.getValueType(); 2968 if (SrcVT != VT) { 2969 if (SrcVT == MVT::f32 && VT == MVT::f64) 2970 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2); 2971 else if (SrcVT == MVT::f64 && VT == MVT::f32) 2972 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0)); 2973 else 2974 // FIXME: Src type is different, bail out for now. Can VT really be a 2975 // vector type? 2976 return SDValue(); 2977 } 2978 2979 EVT VecVT; 2980 EVT EltVT; 2981 SDValue EltMask, VecVal1, VecVal2; 2982 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) { 2983 EltVT = MVT::i32; 2984 VecVT = MVT::v4i32; 2985 EltMask = DAG.getConstant(0x80000000ULL, EltVT); 2986 2987 if (!VT.isVector()) { 2988 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT, 2989 DAG.getUNDEF(VecVT), In1); 2990 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT, 2991 DAG.getUNDEF(VecVT), In2); 2992 } else { 2993 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1); 2994 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2); 2995 } 2996 } else if (VT == MVT::f64 || VT == MVT::v2f64) { 2997 EltVT = MVT::i64; 2998 VecVT = MVT::v2i64; 2999 3000 // We want to materialize a mask with the the high bit set, but the AdvSIMD 3001 // immediate moves cannot materialize that in a single instruction for 3002 // 64-bit elements. Instead, materialize zero and then negate it. 3003 EltMask = DAG.getConstant(0, EltVT); 3004 3005 if (!VT.isVector()) { 3006 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT, 3007 DAG.getUNDEF(VecVT), In1); 3008 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT, 3009 DAG.getUNDEF(VecVT), In2); 3010 } else { 3011 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1); 3012 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2); 3013 } 3014 } else { 3015 llvm_unreachable("Invalid type for copysign!"); 3016 } 3017 3018 std::vector<SDValue> BuildVectorOps; 3019 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) 3020 BuildVectorOps.push_back(EltMask); 3021 3022 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps); 3023 3024 // If we couldn't materialize the mask above, then the mask vector will be 3025 // the zero vector, and we need to negate it here. 3026 if (VT == MVT::f64 || VT == MVT::v2f64) { 3027 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec); 3028 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec); 3029 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec); 3030 } 3031 3032 SDValue Sel = 3033 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec); 3034 3035 if (VT == MVT::f32) 3036 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel); 3037 else if (VT == MVT::f64) 3038 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel); 3039 else 3040 return DAG.getNode(ISD::BITCAST, DL, VT, Sel); 3041} 3042 3043SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const { 3044 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute( 3045 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat)) 3046 return SDValue(); 3047 3048 // While there is no integer popcount instruction, it can 3049 // be more efficiently lowered to the following sequence that uses 3050 // AdvSIMD registers/instructions as long as the copies to/from 3051 // the AdvSIMD registers are cheap. 3052 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd 3053 // CNT V0.8B, V0.8B // 8xbyte pop-counts 3054 // ADDV B0, V0.8B // sum 8xbyte pop-counts 3055 // UMOV X0, V0.B[0] // copy byte result back to integer reg 3056 SDValue Val = Op.getOperand(0); 3057 SDLoc DL(Op); 3058 EVT VT = Op.getValueType(); 3059 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8); 3060 3061 SDValue VecVal; 3062 if (VT == MVT::i32) { 3063 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val); 3064 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec, 3065 VecVal); 3066 } else { 3067 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val); 3068 } 3069 3070 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal); 3071 SDValue UaddLV = DAG.getNode( 3072 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32, 3073 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop); 3074 3075 if (VT == MVT::i64) 3076 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV); 3077 return UaddLV; 3078} 3079 3080SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 3081 3082 if (Op.getValueType().isVector()) 3083 return LowerVSETCC(Op, DAG); 3084 3085 SDValue LHS = Op.getOperand(0); 3086 SDValue RHS = Op.getOperand(1); 3087 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 3088 SDLoc dl(Op); 3089 3090 // We chose ZeroOrOneBooleanContents, so use zero and one. 3091 EVT VT = Op.getValueType(); 3092 SDValue TVal = DAG.getConstant(1, VT); 3093 SDValue FVal = DAG.getConstant(0, VT); 3094 3095 // Handle f128 first, since one possible outcome is a normal integer 3096 // comparison which gets picked up by the next if statement. 3097 if (LHS.getValueType() == MVT::f128) { 3098 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl); 3099 3100 // If softenSetCCOperands returned a scalar, use it. 3101 if (!RHS.getNode()) { 3102 assert(LHS.getValueType() == Op.getValueType() && 3103 "Unexpected setcc expansion!"); 3104 return LHS; 3105 } 3106 } 3107 3108 if (LHS.getValueType().isInteger()) { 3109 SDValue CCVal; 3110 SDValue Cmp = 3111 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl); 3112 3113 // Note that we inverted the condition above, so we reverse the order of 3114 // the true and false operands here. This will allow the setcc to be 3115 // matched to a single CSINC instruction. 3116 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp); 3117 } 3118 3119 // Now we know we're dealing with FP values. 3120 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 3121 3122 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead 3123 // and do the comparison. 3124 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG); 3125 3126 AArch64CC::CondCode CC1, CC2; 3127 changeFPCCToAArch64CC(CC, CC1, CC2); 3128 if (CC2 == AArch64CC::AL) { 3129 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2); 3130 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32); 3131 3132 // Note that we inverted the condition above, so we reverse the order of 3133 // the true and false operands here. This will allow the setcc to be 3134 // matched to a single CSINC instruction. 3135 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp); 3136 } else { 3137 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't 3138 // totally clean. Some of them require two CSELs to implement. As is in 3139 // this case, we emit the first CSEL and then emit a second using the output 3140 // of the first as the RHS. We're effectively OR'ing the two CC's together. 3141 3142 // FIXME: It would be nice if we could match the two CSELs to two CSINCs. 3143 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32); 3144 SDValue CS1 = 3145 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp); 3146 3147 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32); 3148 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp); 3149 } 3150} 3151 3152/// A SELECT_CC operation is really some kind of max or min if both values being 3153/// compared are, in some sense, equal to the results in either case. However, 3154/// it is permissible to compare f32 values and produce directly extended f64 3155/// values. 3156/// 3157/// Extending the comparison operands would also be allowed, but is less likely 3158/// to happen in practice since their use is right here. Note that truncate 3159/// operations would *not* be semantically equivalent. 3160static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) { 3161 if (Cmp == Result) 3162 return true; 3163 3164 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp); 3165 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result); 3166 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 && 3167 Result.getValueType() == MVT::f64) { 3168 bool Lossy; 3169 APFloat CmpVal = CCmp->getValueAPF(); 3170 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy); 3171 return CResult->getValueAPF().bitwiseIsEqual(CmpVal); 3172 } 3173 3174 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp; 3175} 3176 3177SDValue AArch64TargetLowering::LowerSELECT(SDValue Op, 3178 SelectionDAG &DAG) const { 3179 SDValue CC = Op->getOperand(0); 3180 SDValue TVal = Op->getOperand(1); 3181 SDValue FVal = Op->getOperand(2); 3182 SDLoc DL(Op); 3183 3184 unsigned Opc = CC.getOpcode(); 3185 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select 3186 // instruction. 3187 if (CC.getResNo() == 1 && 3188 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO || 3189 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { 3190 // Only lower legal XALUO ops. 3191 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0))) 3192 return SDValue(); 3193 3194 AArch64CC::CondCode OFCC; 3195 SDValue Value, Overflow; 3196 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG); 3197 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32); 3198 3199 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal, 3200 CCVal, Overflow); 3201 } 3202 3203 if (CC.getOpcode() == ISD::SETCC) 3204 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal, 3205 cast<CondCodeSDNode>(CC.getOperand(2))->get()); 3206 else 3207 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal, 3208 FVal, ISD::SETNE); 3209} 3210 3211SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op, 3212 SelectionDAG &DAG) const { 3213 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 3214 SDValue LHS = Op.getOperand(0); 3215 SDValue RHS = Op.getOperand(1); 3216 SDValue TVal = Op.getOperand(2); 3217 SDValue FVal = Op.getOperand(3); 3218 SDLoc dl(Op); 3219 3220 // Handle f128 first, because it will result in a comparison of some RTLIB 3221 // call result against zero. 3222 if (LHS.getValueType() == MVT::f128) { 3223 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl); 3224 3225 // If softenSetCCOperands returned a scalar, we need to compare the result 3226 // against zero to select between true and false values. 3227 if (!RHS.getNode()) { 3228 RHS = DAG.getConstant(0, LHS.getValueType()); 3229 CC = ISD::SETNE; 3230 } 3231 } 3232 3233 // Handle integers first. 3234 if (LHS.getValueType().isInteger()) { 3235 assert((LHS.getValueType() == RHS.getValueType()) && 3236 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64)); 3237 3238 unsigned Opcode = AArch64ISD::CSEL; 3239 3240 // If both the TVal and the FVal are constants, see if we can swap them in 3241 // order to for a CSINV or CSINC out of them. 3242 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal); 3243 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal); 3244 3245 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) { 3246 std::swap(TVal, FVal); 3247 std::swap(CTVal, CFVal); 3248 CC = ISD::getSetCCInverse(CC, true); 3249 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) { 3250 std::swap(TVal, FVal); 3251 std::swap(CTVal, CFVal); 3252 CC = ISD::getSetCCInverse(CC, true); 3253 } else if (TVal.getOpcode() == ISD::XOR) { 3254 // If TVal is a NOT we want to swap TVal and FVal so that we can match 3255 // with a CSINV rather than a CSEL. 3256 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1)); 3257 3258 if (CVal && CVal->isAllOnesValue()) { 3259 std::swap(TVal, FVal); 3260 std::swap(CTVal, CFVal); 3261 CC = ISD::getSetCCInverse(CC, true); 3262 } 3263 } else if (TVal.getOpcode() == ISD::SUB) { 3264 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so 3265 // that we can match with a CSNEG rather than a CSEL. 3266 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0)); 3267 3268 if (CVal && CVal->isNullValue()) { 3269 std::swap(TVal, FVal); 3270 std::swap(CTVal, CFVal); 3271 CC = ISD::getSetCCInverse(CC, true); 3272 } 3273 } else if (CTVal && CFVal) { 3274 const int64_t TrueVal = CTVal->getSExtValue(); 3275 const int64_t FalseVal = CFVal->getSExtValue(); 3276 bool Swap = false; 3277 3278 // If both TVal and FVal are constants, see if FVal is the 3279 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC 3280 // instead of a CSEL in that case. 3281 if (TrueVal == ~FalseVal) { 3282 Opcode = AArch64ISD::CSINV; 3283 } else if (TrueVal == -FalseVal) { 3284 Opcode = AArch64ISD::CSNEG; 3285 } else if (TVal.getValueType() == MVT::i32) { 3286 // If our operands are only 32-bit wide, make sure we use 32-bit 3287 // arithmetic for the check whether we can use CSINC. This ensures that 3288 // the addition in the check will wrap around properly in case there is 3289 // an overflow (which would not be the case if we do the check with 3290 // 64-bit arithmetic). 3291 const uint32_t TrueVal32 = CTVal->getZExtValue(); 3292 const uint32_t FalseVal32 = CFVal->getZExtValue(); 3293 3294 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) { 3295 Opcode = AArch64ISD::CSINC; 3296 3297 if (TrueVal32 > FalseVal32) { 3298 Swap = true; 3299 } 3300 } 3301 // 64-bit check whether we can use CSINC. 3302 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) { 3303 Opcode = AArch64ISD::CSINC; 3304 3305 if (TrueVal > FalseVal) { 3306 Swap = true; 3307 } 3308 } 3309 3310 // Swap TVal and FVal if necessary. 3311 if (Swap) { 3312 std::swap(TVal, FVal); 3313 std::swap(CTVal, CFVal); 3314 CC = ISD::getSetCCInverse(CC, true); 3315 } 3316 3317 if (Opcode != AArch64ISD::CSEL) { 3318 // Drop FVal since we can get its value by simply inverting/negating 3319 // TVal. 3320 FVal = TVal; 3321 } 3322 } 3323 3324 SDValue CCVal; 3325 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl); 3326 3327 EVT VT = Op.getValueType(); 3328 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp); 3329 } 3330 3331 // Now we know we're dealing with FP values. 3332 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 3333 assert(LHS.getValueType() == RHS.getValueType()); 3334 EVT VT = Op.getValueType(); 3335 3336 // Try to match this select into a max/min operation, which have dedicated 3337 // opcode in the instruction set. 3338 // FIXME: This is not correct in the presence of NaNs, so we only enable this 3339 // in no-NaNs mode. 3340 if (getTargetMachine().Options.NoNaNsFPMath) { 3341 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal; 3342 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) && 3343 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) { 3344 CC = ISD::getSetCCSwappedOperands(CC); 3345 std::swap(MinMaxLHS, MinMaxRHS); 3346 } 3347 3348 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) && 3349 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) { 3350 switch (CC) { 3351 default: 3352 break; 3353 case ISD::SETGT: 3354 case ISD::SETGE: 3355 case ISD::SETUGT: 3356 case ISD::SETUGE: 3357 case ISD::SETOGT: 3358 case ISD::SETOGE: 3359 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS); 3360 break; 3361 case ISD::SETLT: 3362 case ISD::SETLE: 3363 case ISD::SETULT: 3364 case ISD::SETULE: 3365 case ISD::SETOLT: 3366 case ISD::SETOLE: 3367 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS); 3368 break; 3369 } 3370 } 3371 } 3372 3373 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead 3374 // and do the comparison. 3375 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG); 3376 3377 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally 3378 // clean. Some of them require two CSELs to implement. 3379 AArch64CC::CondCode CC1, CC2; 3380 changeFPCCToAArch64CC(CC, CC1, CC2); 3381 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32); 3382 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp); 3383 3384 // If we need a second CSEL, emit it, using the output of the first as the 3385 // RHS. We're effectively OR'ing the two CC's together. 3386 if (CC2 != AArch64CC::AL) { 3387 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32); 3388 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp); 3389 } 3390 3391 // Otherwise, return the output of the first CSEL. 3392 return CS1; 3393} 3394 3395SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op, 3396 SelectionDAG &DAG) const { 3397 // Jump table entries as PC relative offsets. No additional tweaking 3398 // is necessary here. Just get the address of the jump table. 3399 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 3400 EVT PtrVT = getPointerTy(); 3401 SDLoc DL(Op); 3402 3403 if (getTargetMachine().getCodeModel() == CodeModel::Large && 3404 !Subtarget->isTargetMachO()) { 3405 const unsigned char MO_NC = AArch64II::MO_NC; 3406 return DAG.getNode( 3407 AArch64ISD::WrapperLarge, DL, PtrVT, 3408 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3), 3409 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC), 3410 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC), 3411 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 3412 AArch64II::MO_G0 | MO_NC)); 3413 } 3414 3415 SDValue Hi = 3416 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE); 3417 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 3418 AArch64II::MO_PAGEOFF | AArch64II::MO_NC); 3419 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi); 3420 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo); 3421} 3422 3423SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op, 3424 SelectionDAG &DAG) const { 3425 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 3426 EVT PtrVT = getPointerTy(); 3427 SDLoc DL(Op); 3428 3429 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 3430 // Use the GOT for the large code model on iOS. 3431 if (Subtarget->isTargetMachO()) { 3432 SDValue GotAddr = DAG.getTargetConstantPool( 3433 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), 3434 AArch64II::MO_GOT); 3435 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr); 3436 } 3437 3438 const unsigned char MO_NC = AArch64II::MO_NC; 3439 return DAG.getNode( 3440 AArch64ISD::WrapperLarge, DL, PtrVT, 3441 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(), 3442 CP->getOffset(), AArch64II::MO_G3), 3443 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(), 3444 CP->getOffset(), AArch64II::MO_G2 | MO_NC), 3445 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(), 3446 CP->getOffset(), AArch64II::MO_G1 | MO_NC), 3447 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(), 3448 CP->getOffset(), AArch64II::MO_G0 | MO_NC)); 3449 } else { 3450 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on 3451 // ELF, the only valid one on Darwin. 3452 SDValue Hi = 3453 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(), 3454 CP->getOffset(), AArch64II::MO_PAGE); 3455 SDValue Lo = DAG.getTargetConstantPool( 3456 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), 3457 AArch64II::MO_PAGEOFF | AArch64II::MO_NC); 3458 3459 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi); 3460 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo); 3461 } 3462} 3463 3464SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op, 3465 SelectionDAG &DAG) const { 3466 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 3467 EVT PtrVT = getPointerTy(); 3468 SDLoc DL(Op); 3469 if (getTargetMachine().getCodeModel() == CodeModel::Large && 3470 !Subtarget->isTargetMachO()) { 3471 const unsigned char MO_NC = AArch64II::MO_NC; 3472 return DAG.getNode( 3473 AArch64ISD::WrapperLarge, DL, PtrVT, 3474 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3), 3475 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC), 3476 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC), 3477 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC)); 3478 } else { 3479 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE); 3480 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF | 3481 AArch64II::MO_NC); 3482 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi); 3483 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo); 3484 } 3485} 3486 3487SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op, 3488 SelectionDAG &DAG) const { 3489 AArch64FunctionInfo *FuncInfo = 3490 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>(); 3491 3492 SDLoc DL(Op); 3493 SDValue FR = 3494 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy()); 3495 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 3496 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 3497 MachinePointerInfo(SV), false, false, 0); 3498} 3499 3500SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op, 3501 SelectionDAG &DAG) const { 3502 // The layout of the va_list struct is specified in the AArch64 Procedure Call 3503 // Standard, section B.3. 3504 MachineFunction &MF = DAG.getMachineFunction(); 3505 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>(); 3506 SDLoc DL(Op); 3507 3508 SDValue Chain = Op.getOperand(0); 3509 SDValue VAList = Op.getOperand(1); 3510 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 3511 SmallVector<SDValue, 4> MemOps; 3512 3513 // void *__stack at offset 0 3514 SDValue Stack = 3515 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy()); 3516 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList, 3517 MachinePointerInfo(SV), false, false, 8)); 3518 3519 // void *__gr_top at offset 8 3520 int GPRSize = FuncInfo->getVarArgsGPRSize(); 3521 if (GPRSize > 0) { 3522 SDValue GRTop, GRTopAddr; 3523 3524 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 3525 DAG.getConstant(8, getPointerTy())); 3526 3527 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy()); 3528 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop, 3529 DAG.getConstant(GPRSize, getPointerTy())); 3530 3531 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr, 3532 MachinePointerInfo(SV, 8), false, false, 8)); 3533 } 3534 3535 // void *__vr_top at offset 16 3536 int FPRSize = FuncInfo->getVarArgsFPRSize(); 3537 if (FPRSize > 0) { 3538 SDValue VRTop, VRTopAddr; 3539 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 3540 DAG.getConstant(16, getPointerTy())); 3541 3542 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy()); 3543 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop, 3544 DAG.getConstant(FPRSize, getPointerTy())); 3545 3546 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr, 3547 MachinePointerInfo(SV, 16), false, false, 8)); 3548 } 3549 3550 // int __gr_offs at offset 24 3551 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 3552 DAG.getConstant(24, getPointerTy())); 3553 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32), 3554 GROffsAddr, MachinePointerInfo(SV, 24), false, 3555 false, 4)); 3556 3557 // int __vr_offs at offset 28 3558 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 3559 DAG.getConstant(28, getPointerTy())); 3560 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32), 3561 VROffsAddr, MachinePointerInfo(SV, 28), false, 3562 false, 4)); 3563 3564 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); 3565} 3566 3567SDValue AArch64TargetLowering::LowerVASTART(SDValue Op, 3568 SelectionDAG &DAG) const { 3569 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG) 3570 : LowerAAPCS_VASTART(Op, DAG); 3571} 3572 3573SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op, 3574 SelectionDAG &DAG) const { 3575 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single 3576 // pointer. 3577 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32; 3578 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 3579 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 3580 3581 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1), 3582 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32), 3583 8, false, false, MachinePointerInfo(DestSV), 3584 MachinePointerInfo(SrcSV)); 3585} 3586 3587SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 3588 assert(Subtarget->isTargetDarwin() && 3589 "automatic va_arg instruction only works on Darwin"); 3590 3591 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 3592 EVT VT = Op.getValueType(); 3593 SDLoc DL(Op); 3594 SDValue Chain = Op.getOperand(0); 3595 SDValue Addr = Op.getOperand(1); 3596 unsigned Align = Op.getConstantOperandVal(3); 3597 3598 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr, 3599 MachinePointerInfo(V), false, false, false, 0); 3600 Chain = VAList.getValue(1); 3601 3602 if (Align > 8) { 3603 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2"); 3604 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 3605 DAG.getConstant(Align - 1, getPointerTy())); 3606 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList, 3607 DAG.getConstant(-(int64_t)Align, getPointerTy())); 3608 } 3609 3610 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 3611 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy); 3612 3613 // Scalar integer and FP values smaller than 64 bits are implicitly extended 3614 // up to 64 bits. At the very least, we have to increase the striding of the 3615 // vaargs list to match this, and for FP values we need to introduce 3616 // FP_ROUND nodes as well. 3617 if (VT.isInteger() && !VT.isVector()) 3618 ArgSize = 8; 3619 bool NeedFPTrunc = false; 3620 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) { 3621 ArgSize = 8; 3622 NeedFPTrunc = true; 3623 } 3624 3625 // Increment the pointer, VAList, to the next vaarg 3626 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList, 3627 DAG.getConstant(ArgSize, getPointerTy())); 3628 // Store the incremented VAList to the legalized pointer 3629 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V), 3630 false, false, 0); 3631 3632 // Load the actual argument out of the pointer VAList 3633 if (NeedFPTrunc) { 3634 // Load the value as an f64. 3635 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList, 3636 MachinePointerInfo(), false, false, false, 0); 3637 // Round the value down to an f32. 3638 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0), 3639 DAG.getIntPtrConstant(1)); 3640 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) }; 3641 // Merge the rounded value with the chain output of the load. 3642 return DAG.getMergeValues(Ops, DL); 3643 } 3644 3645 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false, 3646 false, false, 0); 3647} 3648 3649SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op, 3650 SelectionDAG &DAG) const { 3651 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3652 MFI->setFrameAddressIsTaken(true); 3653 3654 EVT VT = Op.getValueType(); 3655 SDLoc DL(Op); 3656 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3657 SDValue FrameAddr = 3658 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT); 3659 while (Depth--) 3660 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr, 3661 MachinePointerInfo(), false, false, false, 0); 3662 return FrameAddr; 3663} 3664 3665// FIXME? Maybe this could be a TableGen attribute on some registers and 3666// this table could be generated automatically from RegInfo. 3667unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, 3668 EVT VT) const { 3669 unsigned Reg = StringSwitch<unsigned>(RegName) 3670 .Case("sp", AArch64::SP) 3671 .Default(0); 3672 if (Reg) 3673 return Reg; 3674 report_fatal_error("Invalid register name global variable"); 3675} 3676 3677SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op, 3678 SelectionDAG &DAG) const { 3679 MachineFunction &MF = DAG.getMachineFunction(); 3680 MachineFrameInfo *MFI = MF.getFrameInfo(); 3681 MFI->setReturnAddressIsTaken(true); 3682 3683 EVT VT = Op.getValueType(); 3684 SDLoc DL(Op); 3685 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3686 if (Depth) { 3687 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 3688 SDValue Offset = DAG.getConstant(8, getPointerTy()); 3689 return DAG.getLoad(VT, DL, DAG.getEntryNode(), 3690 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset), 3691 MachinePointerInfo(), false, false, false, 0); 3692 } 3693 3694 // Return LR, which contains the return address. Mark it an implicit live-in. 3695 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass); 3696 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT); 3697} 3698 3699/// LowerShiftRightParts - Lower SRA_PARTS, which returns two 3700/// i64 values and take a 2 x i64 value to shift plus a shift amount. 3701SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op, 3702 SelectionDAG &DAG) const { 3703 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3704 EVT VT = Op.getValueType(); 3705 unsigned VTBits = VT.getSizeInBits(); 3706 SDLoc dl(Op); 3707 SDValue ShOpLo = Op.getOperand(0); 3708 SDValue ShOpHi = Op.getOperand(1); 3709 SDValue ShAmt = Op.getOperand(2); 3710 SDValue ARMcc; 3711 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; 3712 3713 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS); 3714 3715 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, 3716 DAG.getConstant(VTBits, MVT::i64), ShAmt); 3717 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); 3718 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt, 3719 DAG.getConstant(VTBits, MVT::i64)); 3720 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 3721 3722 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64), 3723 ISD::SETGE, dl, DAG); 3724 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32); 3725 3726 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3727 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); 3728 SDValue Lo = 3729 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp); 3730 3731 // AArch64 shifts larger than the register width are wrapped rather than 3732 // clamped, so we can't just emit "hi >> x". 3733 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); 3734 SDValue TrueValHi = Opc == ISD::SRA 3735 ? DAG.getNode(Opc, dl, VT, ShOpHi, 3736 DAG.getConstant(VTBits - 1, MVT::i64)) 3737 : DAG.getConstant(0, VT); 3738 SDValue Hi = 3739 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp); 3740 3741 SDValue Ops[2] = { Lo, Hi }; 3742 return DAG.getMergeValues(Ops, dl); 3743} 3744 3745/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two 3746/// i64 values and take a 2 x i64 value to shift plus a shift amount. 3747SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op, 3748 SelectionDAG &DAG) const { 3749 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3750 EVT VT = Op.getValueType(); 3751 unsigned VTBits = VT.getSizeInBits(); 3752 SDLoc dl(Op); 3753 SDValue ShOpLo = Op.getOperand(0); 3754 SDValue ShOpHi = Op.getOperand(1); 3755 SDValue ShAmt = Op.getOperand(2); 3756 SDValue ARMcc; 3757 3758 assert(Op.getOpcode() == ISD::SHL_PARTS); 3759 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, 3760 DAG.getConstant(VTBits, MVT::i64), ShAmt); 3761 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); 3762 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt, 3763 DAG.getConstant(VTBits, MVT::i64)); 3764 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 3765 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 3766 3767 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3768 3769 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64), 3770 ISD::SETGE, dl, DAG); 3771 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32); 3772 SDValue Hi = 3773 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp); 3774 3775 // AArch64 shifts of larger than register sizes are wrapped rather than 3776 // clamped, so we can't just emit "lo << a" if a is too big. 3777 SDValue TrueValLo = DAG.getConstant(0, VT); 3778 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 3779 SDValue Lo = 3780 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp); 3781 3782 SDValue Ops[2] = { Lo, Hi }; 3783 return DAG.getMergeValues(Ops, dl); 3784} 3785 3786bool AArch64TargetLowering::isOffsetFoldingLegal( 3787 const GlobalAddressSDNode *GA) const { 3788 // The AArch64 target doesn't support folding offsets into global addresses. 3789 return false; 3790} 3791 3792bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3793 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases. 3794 // FIXME: We should be able to handle f128 as well with a clever lowering. 3795 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32)) 3796 return true; 3797 3798 if (VT == MVT::f64) 3799 return AArch64_AM::getFP64Imm(Imm) != -1; 3800 else if (VT == MVT::f32) 3801 return AArch64_AM::getFP32Imm(Imm) != -1; 3802 return false; 3803} 3804 3805//===----------------------------------------------------------------------===// 3806// AArch64 Optimization Hooks 3807//===----------------------------------------------------------------------===// 3808 3809//===----------------------------------------------------------------------===// 3810// AArch64 Inline Assembly Support 3811//===----------------------------------------------------------------------===// 3812 3813// Table of Constraints 3814// TODO: This is the current set of constraints supported by ARM for the 3815// compiler, not all of them may make sense, e.g. S may be difficult to support. 3816// 3817// r - A general register 3818// w - An FP/SIMD register of some size in the range v0-v31 3819// x - An FP/SIMD register of some size in the range v0-v15 3820// I - Constant that can be used with an ADD instruction 3821// J - Constant that can be used with a SUB instruction 3822// K - Constant that can be used with a 32-bit logical instruction 3823// L - Constant that can be used with a 64-bit logical instruction 3824// M - Constant that can be used as a 32-bit MOV immediate 3825// N - Constant that can be used as a 64-bit MOV immediate 3826// Q - A memory reference with base register and no offset 3827// S - A symbolic address 3828// Y - Floating point constant zero 3829// Z - Integer constant zero 3830// 3831// Note that general register operands will be output using their 64-bit x 3832// register name, whatever the size of the variable, unless the asm operand 3833// is prefixed by the %w modifier. Floating-point and SIMD register operands 3834// will be output with the v prefix unless prefixed by the %b, %h, %s, %d or 3835// %q modifier. 3836 3837/// getConstraintType - Given a constraint letter, return the type of 3838/// constraint it is for this target. 3839AArch64TargetLowering::ConstraintType 3840AArch64TargetLowering::getConstraintType(const std::string &Constraint) const { 3841 if (Constraint.size() == 1) { 3842 switch (Constraint[0]) { 3843 default: 3844 break; 3845 case 'z': 3846 return C_Other; 3847 case 'x': 3848 case 'w': 3849 return C_RegisterClass; 3850 // An address with a single base register. Due to the way we 3851 // currently handle addresses it is the same as 'r'. 3852 case 'Q': 3853 return C_Memory; 3854 } 3855 } 3856 return TargetLowering::getConstraintType(Constraint); 3857} 3858 3859/// Examine constraint type and operand type and determine a weight value. 3860/// This object must already have been set up with the operand type 3861/// and the current alternative constraint selected. 3862TargetLowering::ConstraintWeight 3863AArch64TargetLowering::getSingleConstraintMatchWeight( 3864 AsmOperandInfo &info, const char *constraint) const { 3865 ConstraintWeight weight = CW_Invalid; 3866 Value *CallOperandVal = info.CallOperandVal; 3867 // If we don't have a value, we can't do a match, 3868 // but allow it at the lowest weight. 3869 if (!CallOperandVal) 3870 return CW_Default; 3871 Type *type = CallOperandVal->getType(); 3872 // Look at the constraint type. 3873 switch (*constraint) { 3874 default: 3875 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3876 break; 3877 case 'x': 3878 case 'w': 3879 if (type->isFloatingPointTy() || type->isVectorTy()) 3880 weight = CW_Register; 3881 break; 3882 case 'z': 3883 weight = CW_Constant; 3884 break; 3885 } 3886 return weight; 3887} 3888 3889std::pair<unsigned, const TargetRegisterClass *> 3890AArch64TargetLowering::getRegForInlineAsmConstraint( 3891 const std::string &Constraint, MVT VT) const { 3892 if (Constraint.size() == 1) { 3893 switch (Constraint[0]) { 3894 case 'r': 3895 if (VT.getSizeInBits() == 64) 3896 return std::make_pair(0U, &AArch64::GPR64commonRegClass); 3897 return std::make_pair(0U, &AArch64::GPR32commonRegClass); 3898 case 'w': 3899 if (VT == MVT::f32) 3900 return std::make_pair(0U, &AArch64::FPR32RegClass); 3901 if (VT.getSizeInBits() == 64) 3902 return std::make_pair(0U, &AArch64::FPR64RegClass); 3903 if (VT.getSizeInBits() == 128) 3904 return std::make_pair(0U, &AArch64::FPR128RegClass); 3905 break; 3906 // The instructions that this constraint is designed for can 3907 // only take 128-bit registers so just use that regclass. 3908 case 'x': 3909 if (VT.getSizeInBits() == 128) 3910 return std::make_pair(0U, &AArch64::FPR128_loRegClass); 3911 break; 3912 } 3913 } 3914 if (StringRef("{cc}").equals_lower(Constraint)) 3915 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass); 3916 3917 // Use the default implementation in TargetLowering to convert the register 3918 // constraint into a member of a register class. 3919 std::pair<unsigned, const TargetRegisterClass *> Res; 3920 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3921 3922 // Not found as a standard register? 3923 if (!Res.second) { 3924 unsigned Size = Constraint.size(); 3925 if ((Size == 4 || Size == 5) && Constraint[0] == '{' && 3926 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') { 3927 const std::string Reg = 3928 std::string(&Constraint[2], &Constraint[Size - 1]); 3929 int RegNo = atoi(Reg.c_str()); 3930 if (RegNo >= 0 && RegNo <= 31) { 3931 // v0 - v31 are aliases of q0 - q31. 3932 // By default we'll emit v0-v31 for this unless there's a modifier where 3933 // we'll emit the correct register as well. 3934 Res.first = AArch64::FPR128RegClass.getRegister(RegNo); 3935 Res.second = &AArch64::FPR128RegClass; 3936 } 3937 } 3938 } 3939 3940 return Res; 3941} 3942 3943/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3944/// vector. If it is invalid, don't add anything to Ops. 3945void AArch64TargetLowering::LowerAsmOperandForConstraint( 3946 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, 3947 SelectionDAG &DAG) const { 3948 SDValue Result; 3949 3950 // Currently only support length 1 constraints. 3951 if (Constraint.length() != 1) 3952 return; 3953 3954 char ConstraintLetter = Constraint[0]; 3955 switch (ConstraintLetter) { 3956 default: 3957 break; 3958 3959 // This set of constraints deal with valid constants for various instructions. 3960 // Validate and return a target constant for them if we can. 3961 case 'z': { 3962 // 'z' maps to xzr or wzr so it needs an input of 0. 3963 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 3964 if (!C || C->getZExtValue() != 0) 3965 return; 3966 3967 if (Op.getValueType() == MVT::i64) 3968 Result = DAG.getRegister(AArch64::XZR, MVT::i64); 3969 else 3970 Result = DAG.getRegister(AArch64::WZR, MVT::i32); 3971 break; 3972 } 3973 3974 case 'I': 3975 case 'J': 3976 case 'K': 3977 case 'L': 3978 case 'M': 3979 case 'N': 3980 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 3981 if (!C) 3982 return; 3983 3984 // Grab the value and do some validation. 3985 uint64_t CVal = C->getZExtValue(); 3986 switch (ConstraintLetter) { 3987 // The I constraint applies only to simple ADD or SUB immediate operands: 3988 // i.e. 0 to 4095 with optional shift by 12 3989 // The J constraint applies only to ADD or SUB immediates that would be 3990 // valid when negated, i.e. if [an add pattern] were to be output as a SUB 3991 // instruction [or vice versa], in other words -1 to -4095 with optional 3992 // left shift by 12. 3993 case 'I': 3994 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal)) 3995 break; 3996 return; 3997 case 'J': { 3998 uint64_t NVal = -C->getSExtValue(); 3999 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) 4000 break; 4001 return; 4002 } 4003 // The K and L constraints apply *only* to logical immediates, including 4004 // what used to be the MOVI alias for ORR (though the MOVI alias has now 4005 // been removed and MOV should be used). So these constraints have to 4006 // distinguish between bit patterns that are valid 32-bit or 64-bit 4007 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but 4008 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice 4009 // versa. 4010 case 'K': 4011 if (AArch64_AM::isLogicalImmediate(CVal, 32)) 4012 break; 4013 return; 4014 case 'L': 4015 if (AArch64_AM::isLogicalImmediate(CVal, 64)) 4016 break; 4017 return; 4018 // The M and N constraints are a superset of K and L respectively, for use 4019 // with the MOV (immediate) alias. As well as the logical immediates they 4020 // also match 32 or 64-bit immediates that can be loaded either using a 4021 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca 4022 // (M) or 64-bit 0x1234000000000000 (N) etc. 4023 // As a note some of this code is liberally stolen from the asm parser. 4024 case 'M': { 4025 if (!isUInt<32>(CVal)) 4026 return; 4027 if (AArch64_AM::isLogicalImmediate(CVal, 32)) 4028 break; 4029 if ((CVal & 0xFFFF) == CVal) 4030 break; 4031 if ((CVal & 0xFFFF0000ULL) == CVal) 4032 break; 4033 uint64_t NCVal = ~(uint32_t)CVal; 4034 if ((NCVal & 0xFFFFULL) == NCVal) 4035 break; 4036 if ((NCVal & 0xFFFF0000ULL) == NCVal) 4037 break; 4038 return; 4039 } 4040 case 'N': { 4041 if (AArch64_AM::isLogicalImmediate(CVal, 64)) 4042 break; 4043 if ((CVal & 0xFFFFULL) == CVal) 4044 break; 4045 if ((CVal & 0xFFFF0000ULL) == CVal) 4046 break; 4047 if ((CVal & 0xFFFF00000000ULL) == CVal) 4048 break; 4049 if ((CVal & 0xFFFF000000000000ULL) == CVal) 4050 break; 4051 uint64_t NCVal = ~CVal; 4052 if ((NCVal & 0xFFFFULL) == NCVal) 4053 break; 4054 if ((NCVal & 0xFFFF0000ULL) == NCVal) 4055 break; 4056 if ((NCVal & 0xFFFF00000000ULL) == NCVal) 4057 break; 4058 if ((NCVal & 0xFFFF000000000000ULL) == NCVal) 4059 break; 4060 return; 4061 } 4062 default: 4063 return; 4064 } 4065 4066 // All assembler immediates are 64-bit integers. 4067 Result = DAG.getTargetConstant(CVal, MVT::i64); 4068 break; 4069 } 4070 4071 if (Result.getNode()) { 4072 Ops.push_back(Result); 4073 return; 4074 } 4075 4076 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 4077} 4078 4079//===----------------------------------------------------------------------===// 4080// AArch64 Advanced SIMD Support 4081//===----------------------------------------------------------------------===// 4082 4083/// WidenVector - Given a value in the V64 register class, produce the 4084/// equivalent value in the V128 register class. 4085static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) { 4086 EVT VT = V64Reg.getValueType(); 4087 unsigned NarrowSize = VT.getVectorNumElements(); 4088 MVT EltTy = VT.getVectorElementType().getSimpleVT(); 4089 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize); 4090 SDLoc DL(V64Reg); 4091 4092 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy), 4093 V64Reg, DAG.getConstant(0, MVT::i32)); 4094} 4095 4096/// getExtFactor - Determine the adjustment factor for the position when 4097/// generating an "extract from vector registers" instruction. 4098static unsigned getExtFactor(SDValue &V) { 4099 EVT EltType = V.getValueType().getVectorElementType(); 4100 return EltType.getSizeInBits() / 8; 4101} 4102 4103/// NarrowVector - Given a value in the V128 register class, produce the 4104/// equivalent value in the V64 register class. 4105static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) { 4106 EVT VT = V128Reg.getValueType(); 4107 unsigned WideSize = VT.getVectorNumElements(); 4108 MVT EltTy = VT.getVectorElementType().getSimpleVT(); 4109 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2); 4110 SDLoc DL(V128Reg); 4111 4112 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg); 4113} 4114 4115// Gather data to see if the operation can be modelled as a 4116// shuffle in combination with VEXTs. 4117SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op, 4118 SelectionDAG &DAG) const { 4119 SDLoc dl(Op); 4120 EVT VT = Op.getValueType(); 4121 unsigned NumElts = VT.getVectorNumElements(); 4122 4123 SmallVector<SDValue, 2> SourceVecs; 4124 SmallVector<unsigned, 2> MinElts; 4125 SmallVector<unsigned, 2> MaxElts; 4126 4127 for (unsigned i = 0; i < NumElts; ++i) { 4128 SDValue V = Op.getOperand(i); 4129 if (V.getOpcode() == ISD::UNDEF) 4130 continue; 4131 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) { 4132 // A shuffle can only come from building a vector from various 4133 // elements of other vectors. 4134 return SDValue(); 4135 } 4136 4137 // Record this extraction against the appropriate vector if possible... 4138 SDValue SourceVec = V.getOperand(0); 4139 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue(); 4140 bool FoundSource = false; 4141 for (unsigned j = 0; j < SourceVecs.size(); ++j) { 4142 if (SourceVecs[j] == SourceVec) { 4143 if (MinElts[j] > EltNo) 4144 MinElts[j] = EltNo; 4145 if (MaxElts[j] < EltNo) 4146 MaxElts[j] = EltNo; 4147 FoundSource = true; 4148 break; 4149 } 4150 } 4151 4152 // Or record a new source if not... 4153 if (!FoundSource) { 4154 SourceVecs.push_back(SourceVec); 4155 MinElts.push_back(EltNo); 4156 MaxElts.push_back(EltNo); 4157 } 4158 } 4159 4160 // Currently only do something sane when at most two source vectors 4161 // involved. 4162 if (SourceVecs.size() > 2) 4163 return SDValue(); 4164 4165 SDValue ShuffleSrcs[2] = { DAG.getUNDEF(VT), DAG.getUNDEF(VT) }; 4166 int VEXTOffsets[2] = { 0, 0 }; 4167 4168 // This loop extracts the usage patterns of the source vectors 4169 // and prepares appropriate SDValues for a shuffle if possible. 4170 for (unsigned i = 0; i < SourceVecs.size(); ++i) { 4171 if (SourceVecs[i].getValueType() == VT) { 4172 // No VEXT necessary 4173 ShuffleSrcs[i] = SourceVecs[i]; 4174 VEXTOffsets[i] = 0; 4175 continue; 4176 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) { 4177 // We can pad out the smaller vector for free, so if it's part of a 4178 // shuffle... 4179 ShuffleSrcs[i] = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, SourceVecs[i], 4180 DAG.getUNDEF(SourceVecs[i].getValueType())); 4181 continue; 4182 } 4183 4184 // Don't attempt to extract subvectors from BUILD_VECTOR sources 4185 // that expand or trunc the original value. 4186 // TODO: We can try to bitcast and ANY_EXTEND the result but 4187 // we need to consider the cost of vector ANY_EXTEND, and the 4188 // legality of all the types. 4189 if (SourceVecs[i].getValueType().getVectorElementType() != 4190 VT.getVectorElementType()) 4191 return SDValue(); 4192 4193 // Since only 64-bit and 128-bit vectors are legal on ARM and 4194 // we've eliminated the other cases... 4195 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2 * NumElts && 4196 "unexpected vector sizes in ReconstructShuffle"); 4197 4198 if (MaxElts[i] - MinElts[i] >= NumElts) { 4199 // Span too large for a VEXT to cope 4200 return SDValue(); 4201 } 4202 4203 if (MinElts[i] >= NumElts) { 4204 // The extraction can just take the second half 4205 VEXTOffsets[i] = NumElts; 4206 ShuffleSrcs[i] = 4207 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SourceVecs[i], 4208 DAG.getIntPtrConstant(NumElts)); 4209 } else if (MaxElts[i] < NumElts) { 4210 // The extraction can just take the first half 4211 VEXTOffsets[i] = 0; 4212 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4213 SourceVecs[i], DAG.getIntPtrConstant(0)); 4214 } else { 4215 // An actual VEXT is needed 4216 VEXTOffsets[i] = MinElts[i]; 4217 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4218 SourceVecs[i], DAG.getIntPtrConstant(0)); 4219 SDValue VEXTSrc2 = 4220 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SourceVecs[i], 4221 DAG.getIntPtrConstant(NumElts)); 4222 unsigned Imm = VEXTOffsets[i] * getExtFactor(VEXTSrc1); 4223 ShuffleSrcs[i] = DAG.getNode(AArch64ISD::EXT, dl, VT, VEXTSrc1, VEXTSrc2, 4224 DAG.getConstant(Imm, MVT::i32)); 4225 } 4226 } 4227 4228 SmallVector<int, 8> Mask; 4229 4230 for (unsigned i = 0; i < NumElts; ++i) { 4231 SDValue Entry = Op.getOperand(i); 4232 if (Entry.getOpcode() == ISD::UNDEF) { 4233 Mask.push_back(-1); 4234 continue; 4235 } 4236 4237 SDValue ExtractVec = Entry.getOperand(0); 4238 int ExtractElt = 4239 cast<ConstantSDNode>(Op.getOperand(i).getOperand(1))->getSExtValue(); 4240 if (ExtractVec == SourceVecs[0]) { 4241 Mask.push_back(ExtractElt - VEXTOffsets[0]); 4242 } else { 4243 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]); 4244 } 4245 } 4246 4247 // Final check before we try to produce nonsense... 4248 if (isShuffleMaskLegal(Mask, VT)) 4249 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1], 4250 &Mask[0]); 4251 4252 return SDValue(); 4253} 4254 4255// check if an EXT instruction can handle the shuffle mask when the 4256// vector sources of the shuffle are the same. 4257static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) { 4258 unsigned NumElts = VT.getVectorNumElements(); 4259 4260 // Assume that the first shuffle index is not UNDEF. Fail if it is. 4261 if (M[0] < 0) 4262 return false; 4263 4264 Imm = M[0]; 4265 4266 // If this is a VEXT shuffle, the immediate value is the index of the first 4267 // element. The other shuffle indices must be the successive elements after 4268 // the first one. 4269 unsigned ExpectedElt = Imm; 4270 for (unsigned i = 1; i < NumElts; ++i) { 4271 // Increment the expected index. If it wraps around, just follow it 4272 // back to index zero and keep going. 4273 ++ExpectedElt; 4274 if (ExpectedElt == NumElts) 4275 ExpectedElt = 0; 4276 4277 if (M[i] < 0) 4278 continue; // ignore UNDEF indices 4279 if (ExpectedElt != static_cast<unsigned>(M[i])) 4280 return false; 4281 } 4282 4283 return true; 4284} 4285 4286// check if an EXT instruction can handle the shuffle mask when the 4287// vector sources of the shuffle are different. 4288static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT, 4289 unsigned &Imm) { 4290 // Look for the first non-undef element. 4291 const int *FirstRealElt = std::find_if(M.begin(), M.end(), 4292 [](int Elt) {return Elt >= 0;}); 4293 4294 // Benefit form APInt to handle overflow when calculating expected element. 4295 unsigned NumElts = VT.getVectorNumElements(); 4296 unsigned MaskBits = APInt(32, NumElts * 2).logBase2(); 4297 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1); 4298 // The following shuffle indices must be the successive elements after the 4299 // first real element. 4300 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(), 4301 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;}); 4302 if (FirstWrongElt != M.end()) 4303 return false; 4304 4305 // The index of an EXT is the first element if it is not UNDEF. 4306 // Watch out for the beginning UNDEFs. The EXT index should be the expected 4307 // value of the first element. E.g. 4308 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>. 4309 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>. 4310 // ExpectedElt is the last mask index plus 1. 4311 Imm = ExpectedElt.getZExtValue(); 4312 4313 // There are two difference cases requiring to reverse input vectors. 4314 // For example, for vector <4 x i32> we have the following cases, 4315 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>) 4316 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>) 4317 // For both cases, we finally use mask <5, 6, 7, 0>, which requires 4318 // to reverse two input vectors. 4319 if (Imm < NumElts) 4320 ReverseEXT = true; 4321 else 4322 Imm -= NumElts; 4323 4324 return true; 4325} 4326 4327/// isREVMask - Check if a vector shuffle corresponds to a REV 4328/// instruction with the specified blocksize. (The order of the elements 4329/// within each block of the vector is reversed.) 4330static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) { 4331 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) && 4332 "Only possible block sizes for REV are: 16, 32, 64"); 4333 4334 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 4335 if (EltSz == 64) 4336 return false; 4337 4338 unsigned NumElts = VT.getVectorNumElements(); 4339 unsigned BlockElts = M[0] + 1; 4340 // If the first shuffle index is UNDEF, be optimistic. 4341 if (M[0] < 0) 4342 BlockElts = BlockSize / EltSz; 4343 4344 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) 4345 return false; 4346 4347 for (unsigned i = 0; i < NumElts; ++i) { 4348 if (M[i] < 0) 4349 continue; // ignore UNDEF indices 4350 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts)) 4351 return false; 4352 } 4353 4354 return true; 4355} 4356 4357static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 4358 unsigned NumElts = VT.getVectorNumElements(); 4359 WhichResult = (M[0] == 0 ? 0 : 1); 4360 unsigned Idx = WhichResult * NumElts / 2; 4361 for (unsigned i = 0; i != NumElts; i += 2) { 4362 if ((M[i] >= 0 && (unsigned)M[i] != Idx) || 4363 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts)) 4364 return false; 4365 Idx += 1; 4366 } 4367 4368 return true; 4369} 4370 4371static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 4372 unsigned NumElts = VT.getVectorNumElements(); 4373 WhichResult = (M[0] == 0 ? 0 : 1); 4374 for (unsigned i = 0; i != NumElts; ++i) { 4375 if (M[i] < 0) 4376 continue; // ignore UNDEF indices 4377 if ((unsigned)M[i] != 2 * i + WhichResult) 4378 return false; 4379 } 4380 4381 return true; 4382} 4383 4384static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 4385 unsigned NumElts = VT.getVectorNumElements(); 4386 WhichResult = (M[0] == 0 ? 0 : 1); 4387 for (unsigned i = 0; i < NumElts; i += 2) { 4388 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) || 4389 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult)) 4390 return false; 4391 } 4392 return true; 4393} 4394 4395/// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of 4396/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 4397/// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>. 4398static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 4399 unsigned NumElts = VT.getVectorNumElements(); 4400 WhichResult = (M[0] == 0 ? 0 : 1); 4401 unsigned Idx = WhichResult * NumElts / 2; 4402 for (unsigned i = 0; i != NumElts; i += 2) { 4403 if ((M[i] >= 0 && (unsigned)M[i] != Idx) || 4404 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx)) 4405 return false; 4406 Idx += 1; 4407 } 4408 4409 return true; 4410} 4411 4412/// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of 4413/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 4414/// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>, 4415static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 4416 unsigned Half = VT.getVectorNumElements() / 2; 4417 WhichResult = (M[0] == 0 ? 0 : 1); 4418 for (unsigned j = 0; j != 2; ++j) { 4419 unsigned Idx = WhichResult; 4420 for (unsigned i = 0; i != Half; ++i) { 4421 int MIdx = M[i + j * Half]; 4422 if (MIdx >= 0 && (unsigned)MIdx != Idx) 4423 return false; 4424 Idx += 2; 4425 } 4426 } 4427 4428 return true; 4429} 4430 4431/// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of 4432/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 4433/// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>. 4434static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 4435 unsigned NumElts = VT.getVectorNumElements(); 4436 WhichResult = (M[0] == 0 ? 0 : 1); 4437 for (unsigned i = 0; i < NumElts; i += 2) { 4438 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) || 4439 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult)) 4440 return false; 4441 } 4442 return true; 4443} 4444 4445static bool isINSMask(ArrayRef<int> M, int NumInputElements, 4446 bool &DstIsLeft, int &Anomaly) { 4447 if (M.size() != static_cast<size_t>(NumInputElements)) 4448 return false; 4449 4450 int NumLHSMatch = 0, NumRHSMatch = 0; 4451 int LastLHSMismatch = -1, LastRHSMismatch = -1; 4452 4453 for (int i = 0; i < NumInputElements; ++i) { 4454 if (M[i] == -1) { 4455 ++NumLHSMatch; 4456 ++NumRHSMatch; 4457 continue; 4458 } 4459 4460 if (M[i] == i) 4461 ++NumLHSMatch; 4462 else 4463 LastLHSMismatch = i; 4464 4465 if (M[i] == i + NumInputElements) 4466 ++NumRHSMatch; 4467 else 4468 LastRHSMismatch = i; 4469 } 4470 4471 if (NumLHSMatch == NumInputElements - 1) { 4472 DstIsLeft = true; 4473 Anomaly = LastLHSMismatch; 4474 return true; 4475 } else if (NumRHSMatch == NumInputElements - 1) { 4476 DstIsLeft = false; 4477 Anomaly = LastRHSMismatch; 4478 return true; 4479 } 4480 4481 return false; 4482} 4483 4484static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) { 4485 if (VT.getSizeInBits() != 128) 4486 return false; 4487 4488 unsigned NumElts = VT.getVectorNumElements(); 4489 4490 for (int I = 0, E = NumElts / 2; I != E; I++) { 4491 if (Mask[I] != I) 4492 return false; 4493 } 4494 4495 int Offset = NumElts / 2; 4496 for (int I = NumElts / 2, E = NumElts; I != E; I++) { 4497 if (Mask[I] != I + SplitLHS * Offset) 4498 return false; 4499 } 4500 4501 return true; 4502} 4503 4504static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) { 4505 SDLoc DL(Op); 4506 EVT VT = Op.getValueType(); 4507 SDValue V0 = Op.getOperand(0); 4508 SDValue V1 = Op.getOperand(1); 4509 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask(); 4510 4511 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() || 4512 VT.getVectorElementType() != V1.getValueType().getVectorElementType()) 4513 return SDValue(); 4514 4515 bool SplitV0 = V0.getValueType().getSizeInBits() == 128; 4516 4517 if (!isConcatMask(Mask, VT, SplitV0)) 4518 return SDValue(); 4519 4520 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 4521 VT.getVectorNumElements() / 2); 4522 if (SplitV0) { 4523 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0, 4524 DAG.getConstant(0, MVT::i64)); 4525 } 4526 if (V1.getValueType().getSizeInBits() == 128) { 4527 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1, 4528 DAG.getConstant(0, MVT::i64)); 4529 } 4530 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1); 4531} 4532 4533/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 4534/// the specified operations to build the shuffle. 4535static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 4536 SDValue RHS, SelectionDAG &DAG, 4537 SDLoc dl) { 4538 unsigned OpNum = (PFEntry >> 26) & 0x0F; 4539 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1); 4540 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1); 4541 4542 enum { 4543 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 4544 OP_VREV, 4545 OP_VDUP0, 4546 OP_VDUP1, 4547 OP_VDUP2, 4548 OP_VDUP3, 4549 OP_VEXT1, 4550 OP_VEXT2, 4551 OP_VEXT3, 4552 OP_VUZPL, // VUZP, left result 4553 OP_VUZPR, // VUZP, right result 4554 OP_VZIPL, // VZIP, left result 4555 OP_VZIPR, // VZIP, right result 4556 OP_VTRNL, // VTRN, left result 4557 OP_VTRNR // VTRN, right result 4558 }; 4559 4560 if (OpNum == OP_COPY) { 4561 if (LHSID == (1 * 9 + 2) * 9 + 3) 4562 return LHS; 4563 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!"); 4564 return RHS; 4565 } 4566 4567 SDValue OpLHS, OpRHS; 4568 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4569 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4570 EVT VT = OpLHS.getValueType(); 4571 4572 switch (OpNum) { 4573 default: 4574 llvm_unreachable("Unknown shuffle opcode!"); 4575 case OP_VREV: 4576 // VREV divides the vector in half and swaps within the half. 4577 if (VT.getVectorElementType() == MVT::i32 || 4578 VT.getVectorElementType() == MVT::f32) 4579 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS); 4580 // vrev <4 x i16> -> REV32 4581 if (VT.getVectorElementType() == MVT::i16) 4582 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS); 4583 // vrev <4 x i8> -> REV16 4584 assert(VT.getVectorElementType() == MVT::i8); 4585 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS); 4586 case OP_VDUP0: 4587 case OP_VDUP1: 4588 case OP_VDUP2: 4589 case OP_VDUP3: { 4590 EVT EltTy = VT.getVectorElementType(); 4591 unsigned Opcode; 4592 if (EltTy == MVT::i8) 4593 Opcode = AArch64ISD::DUPLANE8; 4594 else if (EltTy == MVT::i16) 4595 Opcode = AArch64ISD::DUPLANE16; 4596 else if (EltTy == MVT::i32 || EltTy == MVT::f32) 4597 Opcode = AArch64ISD::DUPLANE32; 4598 else if (EltTy == MVT::i64 || EltTy == MVT::f64) 4599 Opcode = AArch64ISD::DUPLANE64; 4600 else 4601 llvm_unreachable("Invalid vector element type?"); 4602 4603 if (VT.getSizeInBits() == 64) 4604 OpLHS = WidenVector(OpLHS, DAG); 4605 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64); 4606 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane); 4607 } 4608 case OP_VEXT1: 4609 case OP_VEXT2: 4610 case OP_VEXT3: { 4611 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS); 4612 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS, 4613 DAG.getConstant(Imm, MVT::i32)); 4614 } 4615 case OP_VUZPL: 4616 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS, 4617 OpRHS); 4618 case OP_VUZPR: 4619 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS, 4620 OpRHS); 4621 case OP_VZIPL: 4622 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS, 4623 OpRHS); 4624 case OP_VZIPR: 4625 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS, 4626 OpRHS); 4627 case OP_VTRNL: 4628 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS, 4629 OpRHS); 4630 case OP_VTRNR: 4631 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS, 4632 OpRHS); 4633 } 4634} 4635 4636static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask, 4637 SelectionDAG &DAG) { 4638 // Check to see if we can use the TBL instruction. 4639 SDValue V1 = Op.getOperand(0); 4640 SDValue V2 = Op.getOperand(1); 4641 SDLoc DL(Op); 4642 4643 EVT EltVT = Op.getValueType().getVectorElementType(); 4644 unsigned BytesPerElt = EltVT.getSizeInBits() / 8; 4645 4646 SmallVector<SDValue, 8> TBLMask; 4647 for (int Val : ShuffleMask) { 4648 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) { 4649 unsigned Offset = Byte + Val * BytesPerElt; 4650 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32)); 4651 } 4652 } 4653 4654 MVT IndexVT = MVT::v8i8; 4655 unsigned IndexLen = 8; 4656 if (Op.getValueType().getSizeInBits() == 128) { 4657 IndexVT = MVT::v16i8; 4658 IndexLen = 16; 4659 } 4660 4661 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1); 4662 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2); 4663 4664 SDValue Shuffle; 4665 if (V2.getNode()->getOpcode() == ISD::UNDEF) { 4666 if (IndexLen == 8) 4667 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst); 4668 Shuffle = DAG.getNode( 4669 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT, 4670 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst, 4671 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, 4672 makeArrayRef(TBLMask.data(), IndexLen))); 4673 } else { 4674 if (IndexLen == 8) { 4675 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst); 4676 Shuffle = DAG.getNode( 4677 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT, 4678 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst, 4679 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, 4680 makeArrayRef(TBLMask.data(), IndexLen))); 4681 } else { 4682 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we 4683 // cannot currently represent the register constraints on the input 4684 // table registers. 4685 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst, 4686 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, 4687 // &TBLMask[0], IndexLen)); 4688 Shuffle = DAG.getNode( 4689 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT, 4690 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst, 4691 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT, 4692 makeArrayRef(TBLMask.data(), IndexLen))); 4693 } 4694 } 4695 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle); 4696} 4697 4698static unsigned getDUPLANEOp(EVT EltType) { 4699 if (EltType == MVT::i8) 4700 return AArch64ISD::DUPLANE8; 4701 if (EltType == MVT::i16) 4702 return AArch64ISD::DUPLANE16; 4703 if (EltType == MVT::i32 || EltType == MVT::f32) 4704 return AArch64ISD::DUPLANE32; 4705 if (EltType == MVT::i64 || EltType == MVT::f64) 4706 return AArch64ISD::DUPLANE64; 4707 4708 llvm_unreachable("Invalid vector element type?"); 4709} 4710 4711SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 4712 SelectionDAG &DAG) const { 4713 SDLoc dl(Op); 4714 EVT VT = Op.getValueType(); 4715 4716 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); 4717 4718 // Convert shuffles that are directly supported on NEON to target-specific 4719 // DAG nodes, instead of keeping them as shuffles and matching them again 4720 // during code selection. This is more efficient and avoids the possibility 4721 // of inconsistencies between legalization and selection. 4722 ArrayRef<int> ShuffleMask = SVN->getMask(); 4723 4724 SDValue V1 = Op.getOperand(0); 4725 SDValue V2 = Op.getOperand(1); 4726 4727 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], 4728 V1.getValueType().getSimpleVT())) { 4729 int Lane = SVN->getSplatIndex(); 4730 // If this is undef splat, generate it via "just" vdup, if possible. 4731 if (Lane == -1) 4732 Lane = 0; 4733 4734 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) 4735 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(), 4736 V1.getOperand(0)); 4737 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non- 4738 // constant. If so, we can just reference the lane's definition directly. 4739 if (V1.getOpcode() == ISD::BUILD_VECTOR && 4740 !isa<ConstantSDNode>(V1.getOperand(Lane))) 4741 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane)); 4742 4743 // Otherwise, duplicate from the lane of the input vector. 4744 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType()); 4745 4746 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated 4747 // to make a vector of the same size as this SHUFFLE. We can ignore the 4748 // extract entirely, and canonicalise the concat using WidenVector. 4749 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) { 4750 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue(); 4751 V1 = V1.getOperand(0); 4752 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) { 4753 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2; 4754 Lane -= Idx * VT.getVectorNumElements() / 2; 4755 V1 = WidenVector(V1.getOperand(Idx), DAG); 4756 } else if (VT.getSizeInBits() == 64) 4757 V1 = WidenVector(V1, DAG); 4758 4759 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64)); 4760 } 4761 4762 if (isREVMask(ShuffleMask, VT, 64)) 4763 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2); 4764 if (isREVMask(ShuffleMask, VT, 32)) 4765 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2); 4766 if (isREVMask(ShuffleMask, VT, 16)) 4767 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2); 4768 4769 bool ReverseEXT = false; 4770 unsigned Imm; 4771 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) { 4772 if (ReverseEXT) 4773 std::swap(V1, V2); 4774 Imm *= getExtFactor(V1); 4775 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2, 4776 DAG.getConstant(Imm, MVT::i32)); 4777 } else if (V2->getOpcode() == ISD::UNDEF && 4778 isSingletonEXTMask(ShuffleMask, VT, Imm)) { 4779 Imm *= getExtFactor(V1); 4780 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1, 4781 DAG.getConstant(Imm, MVT::i32)); 4782 } 4783 4784 unsigned WhichResult; 4785 if (isZIPMask(ShuffleMask, VT, WhichResult)) { 4786 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; 4787 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2); 4788 } 4789 if (isUZPMask(ShuffleMask, VT, WhichResult)) { 4790 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; 4791 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2); 4792 } 4793 if (isTRNMask(ShuffleMask, VT, WhichResult)) { 4794 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2; 4795 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2); 4796 } 4797 4798 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) { 4799 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; 4800 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1); 4801 } 4802 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) { 4803 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; 4804 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1); 4805 } 4806 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) { 4807 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2; 4808 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1); 4809 } 4810 4811 SDValue Concat = tryFormConcatFromShuffle(Op, DAG); 4812 if (Concat.getNode()) 4813 return Concat; 4814 4815 bool DstIsLeft; 4816 int Anomaly; 4817 int NumInputElements = V1.getValueType().getVectorNumElements(); 4818 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) { 4819 SDValue DstVec = DstIsLeft ? V1 : V2; 4820 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64); 4821 4822 SDValue SrcVec = V1; 4823 int SrcLane = ShuffleMask[Anomaly]; 4824 if (SrcLane >= NumInputElements) { 4825 SrcVec = V2; 4826 SrcLane -= VT.getVectorNumElements(); 4827 } 4828 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64); 4829 4830 EVT ScalarVT = VT.getVectorElementType(); 4831 if (ScalarVT.getSizeInBits() < 32) 4832 ScalarVT = MVT::i32; 4833 4834 return DAG.getNode( 4835 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, 4836 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV), 4837 DstLaneV); 4838 } 4839 4840 // If the shuffle is not directly supported and it has 4 elements, use 4841 // the PerfectShuffle-generated table to synthesize it from other shuffles. 4842 unsigned NumElts = VT.getVectorNumElements(); 4843 if (NumElts == 4) { 4844 unsigned PFIndexes[4]; 4845 for (unsigned i = 0; i != 4; ++i) { 4846 if (ShuffleMask[i] < 0) 4847 PFIndexes[i] = 8; 4848 else 4849 PFIndexes[i] = ShuffleMask[i]; 4850 } 4851 4852 // Compute the index in the perfect shuffle table. 4853 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 + 4854 PFIndexes[2] * 9 + PFIndexes[3]; 4855 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4856 unsigned Cost = (PFEntry >> 30); 4857 4858 if (Cost <= 4) 4859 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4860 } 4861 4862 return GenerateTBL(Op, ShuffleMask, DAG); 4863} 4864 4865static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits, 4866 APInt &UndefBits) { 4867 EVT VT = BVN->getValueType(0); 4868 APInt SplatBits, SplatUndef; 4869 unsigned SplatBitSize; 4870 bool HasAnyUndefs; 4871 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 4872 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize; 4873 4874 for (unsigned i = 0; i < NumSplats; ++i) { 4875 CnstBits <<= SplatBitSize; 4876 UndefBits <<= SplatBitSize; 4877 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits()); 4878 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits()); 4879 } 4880 4881 return true; 4882 } 4883 4884 return false; 4885} 4886 4887SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op, 4888 SelectionDAG &DAG) const { 4889 BuildVectorSDNode *BVN = 4890 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode()); 4891 SDValue LHS = Op.getOperand(0); 4892 SDLoc dl(Op); 4893 EVT VT = Op.getValueType(); 4894 4895 if (!BVN) 4896 return Op; 4897 4898 APInt CnstBits(VT.getSizeInBits(), 0); 4899 APInt UndefBits(VT.getSizeInBits(), 0); 4900 if (resolveBuildVector(BVN, CnstBits, UndefBits)) { 4901 // We only have BIC vector immediate instruction, which is and-not. 4902 CnstBits = ~CnstBits; 4903 4904 // We make use of a little bit of goto ickiness in order to avoid having to 4905 // duplicate the immediate matching logic for the undef toggled case. 4906 bool SecondTry = false; 4907 AttemptModImm: 4908 4909 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) { 4910 CnstBits = CnstBits.zextOrTrunc(64); 4911 uint64_t CnstVal = CnstBits.getZExtValue(); 4912 4913 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) { 4914 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal); 4915 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 4916 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS, 4917 DAG.getConstant(CnstVal, MVT::i32), 4918 DAG.getConstant(0, MVT::i32)); 4919 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 4920 } 4921 4922 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) { 4923 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal); 4924 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 4925 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS, 4926 DAG.getConstant(CnstVal, MVT::i32), 4927 DAG.getConstant(8, MVT::i32)); 4928 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 4929 } 4930 4931 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) { 4932 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal); 4933 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 4934 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS, 4935 DAG.getConstant(CnstVal, MVT::i32), 4936 DAG.getConstant(16, MVT::i32)); 4937 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 4938 } 4939 4940 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) { 4941 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal); 4942 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 4943 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS, 4944 DAG.getConstant(CnstVal, MVT::i32), 4945 DAG.getConstant(24, MVT::i32)); 4946 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 4947 } 4948 4949 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) { 4950 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal); 4951 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 4952 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS, 4953 DAG.getConstant(CnstVal, MVT::i32), 4954 DAG.getConstant(0, MVT::i32)); 4955 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 4956 } 4957 4958 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) { 4959 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal); 4960 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 4961 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS, 4962 DAG.getConstant(CnstVal, MVT::i32), 4963 DAG.getConstant(8, MVT::i32)); 4964 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 4965 } 4966 } 4967 4968 if (SecondTry) 4969 goto FailedModImm; 4970 SecondTry = true; 4971 CnstBits = ~UndefBits; 4972 goto AttemptModImm; 4973 } 4974 4975// We can always fall back to a non-immediate AND. 4976FailedModImm: 4977 return Op; 4978} 4979 4980// Specialized code to quickly find if PotentialBVec is a BuildVector that 4981// consists of only the same constant int value, returned in reference arg 4982// ConstVal 4983static bool isAllConstantBuildVector(const SDValue &PotentialBVec, 4984 uint64_t &ConstVal) { 4985 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec); 4986 if (!Bvec) 4987 return false; 4988 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0)); 4989 if (!FirstElt) 4990 return false; 4991 EVT VT = Bvec->getValueType(0); 4992 unsigned NumElts = VT.getVectorNumElements(); 4993 for (unsigned i = 1; i < NumElts; ++i) 4994 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt) 4995 return false; 4996 ConstVal = FirstElt->getZExtValue(); 4997 return true; 4998} 4999 5000static unsigned getIntrinsicID(const SDNode *N) { 5001 unsigned Opcode = N->getOpcode(); 5002 switch (Opcode) { 5003 default: 5004 return Intrinsic::not_intrinsic; 5005 case ISD::INTRINSIC_WO_CHAIN: { 5006 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 5007 if (IID < Intrinsic::num_intrinsics) 5008 return IID; 5009 return Intrinsic::not_intrinsic; 5010 } 5011 } 5012} 5013 5014// Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)), 5015// to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a 5016// BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2. 5017// Also, logical shift right -> sri, with the same structure. 5018static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) { 5019 EVT VT = N->getValueType(0); 5020 5021 if (!VT.isVector()) 5022 return SDValue(); 5023 5024 SDLoc DL(N); 5025 5026 // Is the first op an AND? 5027 const SDValue And = N->getOperand(0); 5028 if (And.getOpcode() != ISD::AND) 5029 return SDValue(); 5030 5031 // Is the second op an shl or lshr? 5032 SDValue Shift = N->getOperand(1); 5033 // This will have been turned into: AArch64ISD::VSHL vector, #shift 5034 // or AArch64ISD::VLSHR vector, #shift 5035 unsigned ShiftOpc = Shift.getOpcode(); 5036 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR)) 5037 return SDValue(); 5038 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR; 5039 5040 // Is the shift amount constant? 5041 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1)); 5042 if (!C2node) 5043 return SDValue(); 5044 5045 // Is the and mask vector all constant? 5046 uint64_t C1; 5047 if (!isAllConstantBuildVector(And.getOperand(1), C1)) 5048 return SDValue(); 5049 5050 // Is C1 == ~C2, taking into account how much one can shift elements of a 5051 // particular size? 5052 uint64_t C2 = C2node->getZExtValue(); 5053 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits(); 5054 if (C2 > ElemSizeInBits) 5055 return SDValue(); 5056 unsigned ElemMask = (1 << ElemSizeInBits) - 1; 5057 if ((C1 & ElemMask) != (~C2 & ElemMask)) 5058 return SDValue(); 5059 5060 SDValue X = And.getOperand(0); 5061 SDValue Y = Shift.getOperand(0); 5062 5063 unsigned Intrin = 5064 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli; 5065 SDValue ResultSLI = 5066 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 5067 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1)); 5068 5069 DEBUG(dbgs() << "aarch64-lower: transformed: \n"); 5070 DEBUG(N->dump(&DAG)); 5071 DEBUG(dbgs() << "into: \n"); 5072 DEBUG(ResultSLI->dump(&DAG)); 5073 5074 ++NumShiftInserts; 5075 return ResultSLI; 5076} 5077 5078SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op, 5079 SelectionDAG &DAG) const { 5080 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2)) 5081 if (EnableAArch64SlrGeneration) { 5082 SDValue Res = tryLowerToSLI(Op.getNode(), DAG); 5083 if (Res.getNode()) 5084 return Res; 5085 } 5086 5087 BuildVectorSDNode *BVN = 5088 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode()); 5089 SDValue LHS = Op.getOperand(1); 5090 SDLoc dl(Op); 5091 EVT VT = Op.getValueType(); 5092 5093 // OR commutes, so try swapping the operands. 5094 if (!BVN) { 5095 LHS = Op.getOperand(0); 5096 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode()); 5097 } 5098 if (!BVN) 5099 return Op; 5100 5101 APInt CnstBits(VT.getSizeInBits(), 0); 5102 APInt UndefBits(VT.getSizeInBits(), 0); 5103 if (resolveBuildVector(BVN, CnstBits, UndefBits)) { 5104 // We make use of a little bit of goto ickiness in order to avoid having to 5105 // duplicate the immediate matching logic for the undef toggled case. 5106 bool SecondTry = false; 5107 AttemptModImm: 5108 5109 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) { 5110 CnstBits = CnstBits.zextOrTrunc(64); 5111 uint64_t CnstVal = CnstBits.getZExtValue(); 5112 5113 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) { 5114 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal); 5115 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5116 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS, 5117 DAG.getConstant(CnstVal, MVT::i32), 5118 DAG.getConstant(0, MVT::i32)); 5119 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5120 } 5121 5122 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) { 5123 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal); 5124 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5125 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS, 5126 DAG.getConstant(CnstVal, MVT::i32), 5127 DAG.getConstant(8, MVT::i32)); 5128 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5129 } 5130 5131 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) { 5132 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal); 5133 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5134 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS, 5135 DAG.getConstant(CnstVal, MVT::i32), 5136 DAG.getConstant(16, MVT::i32)); 5137 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5138 } 5139 5140 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) { 5141 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal); 5142 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5143 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS, 5144 DAG.getConstant(CnstVal, MVT::i32), 5145 DAG.getConstant(24, MVT::i32)); 5146 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5147 } 5148 5149 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) { 5150 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal); 5151 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5152 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS, 5153 DAG.getConstant(CnstVal, MVT::i32), 5154 DAG.getConstant(0, MVT::i32)); 5155 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5156 } 5157 5158 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) { 5159 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal); 5160 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5161 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS, 5162 DAG.getConstant(CnstVal, MVT::i32), 5163 DAG.getConstant(8, MVT::i32)); 5164 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5165 } 5166 } 5167 5168 if (SecondTry) 5169 goto FailedModImm; 5170 SecondTry = true; 5171 CnstBits = UndefBits; 5172 goto AttemptModImm; 5173 } 5174 5175// We can always fall back to a non-immediate OR. 5176FailedModImm: 5177 return Op; 5178} 5179 5180SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, 5181 SelectionDAG &DAG) const { 5182 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); 5183 SDLoc dl(Op); 5184 EVT VT = Op.getValueType(); 5185 5186 APInt CnstBits(VT.getSizeInBits(), 0); 5187 APInt UndefBits(VT.getSizeInBits(), 0); 5188 if (resolveBuildVector(BVN, CnstBits, UndefBits)) { 5189 // We make use of a little bit of goto ickiness in order to avoid having to 5190 // duplicate the immediate matching logic for the undef toggled case. 5191 bool SecondTry = false; 5192 AttemptModImm: 5193 5194 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) { 5195 CnstBits = CnstBits.zextOrTrunc(64); 5196 uint64_t CnstVal = CnstBits.getZExtValue(); 5197 5198 // Certain magic vector constants (used to express things like NOT 5199 // and NEG) are passed through unmodified. This allows codegen patterns 5200 // for these operations to match. Special-purpose patterns will lower 5201 // these immediates to MOVIs if it proves necessary. 5202 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL)) 5203 return Op; 5204 5205 // The many faces of MOVI... 5206 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) { 5207 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal); 5208 if (VT.getSizeInBits() == 128) { 5209 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64, 5210 DAG.getConstant(CnstVal, MVT::i32)); 5211 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5212 } 5213 5214 // Support the V64 version via subregister insertion. 5215 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64, 5216 DAG.getConstant(CnstVal, MVT::i32)); 5217 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5218 } 5219 5220 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) { 5221 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal); 5222 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5223 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy, 5224 DAG.getConstant(CnstVal, MVT::i32), 5225 DAG.getConstant(0, MVT::i32)); 5226 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5227 } 5228 5229 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) { 5230 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal); 5231 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5232 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy, 5233 DAG.getConstant(CnstVal, MVT::i32), 5234 DAG.getConstant(8, MVT::i32)); 5235 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5236 } 5237 5238 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) { 5239 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal); 5240 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5241 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy, 5242 DAG.getConstant(CnstVal, MVT::i32), 5243 DAG.getConstant(16, MVT::i32)); 5244 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5245 } 5246 5247 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) { 5248 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal); 5249 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5250 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy, 5251 DAG.getConstant(CnstVal, MVT::i32), 5252 DAG.getConstant(24, MVT::i32)); 5253 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5254 } 5255 5256 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) { 5257 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal); 5258 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5259 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy, 5260 DAG.getConstant(CnstVal, MVT::i32), 5261 DAG.getConstant(0, MVT::i32)); 5262 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5263 } 5264 5265 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) { 5266 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal); 5267 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5268 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy, 5269 DAG.getConstant(CnstVal, MVT::i32), 5270 DAG.getConstant(8, MVT::i32)); 5271 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5272 } 5273 5274 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) { 5275 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal); 5276 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5277 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy, 5278 DAG.getConstant(CnstVal, MVT::i32), 5279 DAG.getConstant(264, MVT::i32)); 5280 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5281 } 5282 5283 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) { 5284 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal); 5285 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5286 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy, 5287 DAG.getConstant(CnstVal, MVT::i32), 5288 DAG.getConstant(272, MVT::i32)); 5289 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5290 } 5291 5292 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) { 5293 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal); 5294 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8; 5295 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy, 5296 DAG.getConstant(CnstVal, MVT::i32)); 5297 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5298 } 5299 5300 // The few faces of FMOV... 5301 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) { 5302 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal); 5303 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32; 5304 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy, 5305 DAG.getConstant(CnstVal, MVT::i32)); 5306 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5307 } 5308 5309 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) && 5310 VT.getSizeInBits() == 128) { 5311 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal); 5312 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64, 5313 DAG.getConstant(CnstVal, MVT::i32)); 5314 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5315 } 5316 5317 // The many faces of MVNI... 5318 CnstVal = ~CnstVal; 5319 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) { 5320 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal); 5321 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5322 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy, 5323 DAG.getConstant(CnstVal, MVT::i32), 5324 DAG.getConstant(0, MVT::i32)); 5325 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5326 } 5327 5328 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) { 5329 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal); 5330 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5331 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy, 5332 DAG.getConstant(CnstVal, MVT::i32), 5333 DAG.getConstant(8, MVT::i32)); 5334 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5335 } 5336 5337 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) { 5338 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal); 5339 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5340 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy, 5341 DAG.getConstant(CnstVal, MVT::i32), 5342 DAG.getConstant(16, MVT::i32)); 5343 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5344 } 5345 5346 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) { 5347 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal); 5348 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5349 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy, 5350 DAG.getConstant(CnstVal, MVT::i32), 5351 DAG.getConstant(24, MVT::i32)); 5352 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5353 } 5354 5355 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) { 5356 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal); 5357 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5358 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy, 5359 DAG.getConstant(CnstVal, MVT::i32), 5360 DAG.getConstant(0, MVT::i32)); 5361 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5362 } 5363 5364 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) { 5365 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal); 5366 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5367 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy, 5368 DAG.getConstant(CnstVal, MVT::i32), 5369 DAG.getConstant(8, MVT::i32)); 5370 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5371 } 5372 5373 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) { 5374 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal); 5375 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5376 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy, 5377 DAG.getConstant(CnstVal, MVT::i32), 5378 DAG.getConstant(264, MVT::i32)); 5379 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5380 } 5381 5382 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) { 5383 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal); 5384 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32; 5385 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy, 5386 DAG.getConstant(CnstVal, MVT::i32), 5387 DAG.getConstant(272, MVT::i32)); 5388 return DAG.getNode(ISD::BITCAST, dl, VT, Mov); 5389 } 5390 } 5391 5392 if (SecondTry) 5393 goto FailedModImm; 5394 SecondTry = true; 5395 CnstBits = UndefBits; 5396 goto AttemptModImm; 5397 } 5398FailedModImm: 5399 5400 // Scan through the operands to find some interesting properties we can 5401 // exploit: 5402 // 1) If only one value is used, we can use a DUP, or 5403 // 2) if only the low element is not undef, we can just insert that, or 5404 // 3) if only one constant value is used (w/ some non-constant lanes), 5405 // we can splat the constant value into the whole vector then fill 5406 // in the non-constant lanes. 5407 // 4) FIXME: If different constant values are used, but we can intelligently 5408 // select the values we'll be overwriting for the non-constant 5409 // lanes such that we can directly materialize the vector 5410 // some other way (MOVI, e.g.), we can be sneaky. 5411 unsigned NumElts = VT.getVectorNumElements(); 5412 bool isOnlyLowElement = true; 5413 bool usesOnlyOneValue = true; 5414 bool usesOnlyOneConstantValue = true; 5415 bool isConstant = true; 5416 unsigned NumConstantLanes = 0; 5417 SDValue Value; 5418 SDValue ConstantValue; 5419 for (unsigned i = 0; i < NumElts; ++i) { 5420 SDValue V = Op.getOperand(i); 5421 if (V.getOpcode() == ISD::UNDEF) 5422 continue; 5423 if (i > 0) 5424 isOnlyLowElement = false; 5425 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 5426 isConstant = false; 5427 5428 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) { 5429 ++NumConstantLanes; 5430 if (!ConstantValue.getNode()) 5431 ConstantValue = V; 5432 else if (ConstantValue != V) 5433 usesOnlyOneConstantValue = false; 5434 } 5435 5436 if (!Value.getNode()) 5437 Value = V; 5438 else if (V != Value) 5439 usesOnlyOneValue = false; 5440 } 5441 5442 if (!Value.getNode()) 5443 return DAG.getUNDEF(VT); 5444 5445 if (isOnlyLowElement) 5446 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); 5447 5448 // Use DUP for non-constant splats. For f32 constant splats, reduce to 5449 // i32 and try again. 5450 if (usesOnlyOneValue) { 5451 if (!isConstant) { 5452 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5453 Value.getValueType() != VT) 5454 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value); 5455 5456 // This is actually a DUPLANExx operation, which keeps everything vectory. 5457 5458 // DUPLANE works on 128-bit vectors, widen it if necessary. 5459 SDValue Lane = Value.getOperand(1); 5460 Value = Value.getOperand(0); 5461 if (Value.getValueType().getSizeInBits() == 64) 5462 Value = WidenVector(Value, DAG); 5463 5464 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType()); 5465 return DAG.getNode(Opcode, dl, VT, Value, Lane); 5466 } 5467 5468 if (VT.getVectorElementType().isFloatingPoint()) { 5469 SmallVector<SDValue, 8> Ops; 5470 MVT NewType = 5471 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 5472 for (unsigned i = 0; i < NumElts; ++i) 5473 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i))); 5474 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts); 5475 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops); 5476 Val = LowerBUILD_VECTOR(Val, DAG); 5477 if (Val.getNode()) 5478 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 5479 } 5480 } 5481 5482 // If there was only one constant value used and for more than one lane, 5483 // start by splatting that value, then replace the non-constant lanes. This 5484 // is better than the default, which will perform a separate initialization 5485 // for each lane. 5486 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) { 5487 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue); 5488 // Now insert the non-constant lanes. 5489 for (unsigned i = 0; i < NumElts; ++i) { 5490 SDValue V = Op.getOperand(i); 5491 SDValue LaneIdx = DAG.getConstant(i, MVT::i64); 5492 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) { 5493 // Note that type legalization likely mucked about with the VT of the 5494 // source operand, so we may have to convert it here before inserting. 5495 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); 5496 } 5497 } 5498 return Val; 5499 } 5500 5501 // If all elements are constants and the case above didn't get hit, fall back 5502 // to the default expansion, which will generate a load from the constant 5503 // pool. 5504 if (isConstant) 5505 return SDValue(); 5506 5507 // Empirical tests suggest this is rarely worth it for vectors of length <= 2. 5508 if (NumElts >= 4) { 5509 SDValue shuffle = ReconstructShuffle(Op, DAG); 5510 if (shuffle != SDValue()) 5511 return shuffle; 5512 } 5513 5514 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we 5515 // know the default expansion would otherwise fall back on something even 5516 // worse. For a vector with one or two non-undef values, that's 5517 // scalar_to_vector for the elements followed by a shuffle (provided the 5518 // shuffle is valid for the target) and materialization element by element 5519 // on the stack followed by a load for everything else. 5520 if (!isConstant && !usesOnlyOneValue) { 5521 SDValue Vec = DAG.getUNDEF(VT); 5522 SDValue Op0 = Op.getOperand(0); 5523 unsigned ElemSize = VT.getVectorElementType().getSizeInBits(); 5524 unsigned i = 0; 5525 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to 5526 // a) Avoid a RMW dependency on the full vector register, and 5527 // b) Allow the register coalescer to fold away the copy if the 5528 // value is already in an S or D register. 5529 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) { 5530 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub; 5531 MachineSDNode *N = 5532 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0, 5533 DAG.getTargetConstant(SubIdx, MVT::i32)); 5534 Vec = SDValue(N, 0); 5535 ++i; 5536 } 5537 for (; i < NumElts; ++i) { 5538 SDValue V = Op.getOperand(i); 5539 if (V.getOpcode() == ISD::UNDEF) 5540 continue; 5541 SDValue LaneIdx = DAG.getConstant(i, MVT::i64); 5542 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); 5543 } 5544 return Vec; 5545 } 5546 5547 // Just use the default expansion. We failed to find a better alternative. 5548 return SDValue(); 5549} 5550 5551SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, 5552 SelectionDAG &DAG) const { 5553 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!"); 5554 5555 // Check for non-constant lane. 5556 if (!isa<ConstantSDNode>(Op.getOperand(2))) 5557 return SDValue(); 5558 5559 EVT VT = Op.getOperand(0).getValueType(); 5560 5561 // Insertion/extraction are legal for V128 types. 5562 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 || 5563 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64) 5564 return Op; 5565 5566 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 && 5567 VT != MVT::v1i64 && VT != MVT::v2f32) 5568 return SDValue(); 5569 5570 // For V64 types, we perform insertion by expanding the value 5571 // to a V128 type and perform the insertion on that. 5572 SDLoc DL(Op); 5573 SDValue WideVec = WidenVector(Op.getOperand(0), DAG); 5574 EVT WideTy = WideVec.getValueType(); 5575 5576 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec, 5577 Op.getOperand(1), Op.getOperand(2)); 5578 // Re-narrow the resultant vector. 5579 return NarrowVector(Node, DAG); 5580} 5581 5582SDValue 5583AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 5584 SelectionDAG &DAG) const { 5585 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!"); 5586 5587 // Check for non-constant lane. 5588 if (!isa<ConstantSDNode>(Op.getOperand(1))) 5589 return SDValue(); 5590 5591 EVT VT = Op.getOperand(0).getValueType(); 5592 5593 // Insertion/extraction are legal for V128 types. 5594 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 || 5595 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64) 5596 return Op; 5597 5598 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 && 5599 VT != MVT::v1i64 && VT != MVT::v2f32) 5600 return SDValue(); 5601 5602 // For V64 types, we perform extraction by expanding the value 5603 // to a V128 type and perform the extraction on that. 5604 SDLoc DL(Op); 5605 SDValue WideVec = WidenVector(Op.getOperand(0), DAG); 5606 EVT WideTy = WideVec.getValueType(); 5607 5608 EVT ExtrTy = WideTy.getVectorElementType(); 5609 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8) 5610 ExtrTy = MVT::i32; 5611 5612 // For extractions, we just return the result directly. 5613 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec, 5614 Op.getOperand(1)); 5615} 5616 5617SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, 5618 SelectionDAG &DAG) const { 5619 EVT VT = Op.getOperand(0).getValueType(); 5620 SDLoc dl(Op); 5621 // Just in case... 5622 if (!VT.isVector()) 5623 return SDValue(); 5624 5625 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 5626 if (!Cst) 5627 return SDValue(); 5628 unsigned Val = Cst->getZExtValue(); 5629 5630 unsigned Size = Op.getValueType().getSizeInBits(); 5631 if (Val == 0) { 5632 switch (Size) { 5633 case 8: 5634 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(), 5635 Op.getOperand(0)); 5636 case 16: 5637 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(), 5638 Op.getOperand(0)); 5639 case 32: 5640 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(), 5641 Op.getOperand(0)); 5642 case 64: 5643 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(), 5644 Op.getOperand(0)); 5645 default: 5646 llvm_unreachable("Unexpected vector type in extract_subvector!"); 5647 } 5648 } 5649 // If this is extracting the upper 64-bits of a 128-bit vector, we match 5650 // that directly. 5651 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64) 5652 return Op; 5653 5654 return SDValue(); 5655} 5656 5657bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 5658 EVT VT) const { 5659 if (VT.getVectorNumElements() == 4 && 5660 (VT.is128BitVector() || VT.is64BitVector())) { 5661 unsigned PFIndexes[4]; 5662 for (unsigned i = 0; i != 4; ++i) { 5663 if (M[i] < 0) 5664 PFIndexes[i] = 8; 5665 else 5666 PFIndexes[i] = M[i]; 5667 } 5668 5669 // Compute the index in the perfect shuffle table. 5670 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 + 5671 PFIndexes[2] * 9 + PFIndexes[3]; 5672 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 5673 unsigned Cost = (PFEntry >> 30); 5674 5675 if (Cost <= 4) 5676 return true; 5677 } 5678 5679 bool DummyBool; 5680 int DummyInt; 5681 unsigned DummyUnsigned; 5682 5683 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) || 5684 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) || 5685 isEXTMask(M, VT, DummyBool, DummyUnsigned) || 5686 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM. 5687 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) || 5688 isZIPMask(M, VT, DummyUnsigned) || 5689 isTRN_v_undef_Mask(M, VT, DummyUnsigned) || 5690 isUZP_v_undef_Mask(M, VT, DummyUnsigned) || 5691 isZIP_v_undef_Mask(M, VT, DummyUnsigned) || 5692 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) || 5693 isConcatMask(M, VT, VT.getSizeInBits() == 128)); 5694} 5695 5696/// getVShiftImm - Check if this is a valid build_vector for the immediate 5697/// operand of a vector shift operation, where all the elements of the 5698/// build_vector must have the same constant integer value. 5699static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { 5700 // Ignore bit_converts. 5701 while (Op.getOpcode() == ISD::BITCAST) 5702 Op = Op.getOperand(0); 5703 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 5704 APInt SplatBits, SplatUndef; 5705 unsigned SplatBitSize; 5706 bool HasAnyUndefs; 5707 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 5708 HasAnyUndefs, ElementBits) || 5709 SplatBitSize > ElementBits) 5710 return false; 5711 Cnt = SplatBits.getSExtValue(); 5712 return true; 5713} 5714 5715/// isVShiftLImm - Check if this is a valid build_vector for the immediate 5716/// operand of a vector shift left operation. That value must be in the range: 5717/// 0 <= Value < ElementBits for a left shift; or 5718/// 0 <= Value <= ElementBits for a long left shift. 5719static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { 5720 assert(VT.isVector() && "vector shift count is not a vector type"); 5721 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 5722 if (!getVShiftImm(Op, ElementBits, Cnt)) 5723 return false; 5724 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits); 5725} 5726 5727/// isVShiftRImm - Check if this is a valid build_vector for the immediate 5728/// operand of a vector shift right operation. For a shift opcode, the value 5729/// is positive, but for an intrinsic the value count must be negative. The 5730/// absolute value must be in the range: 5731/// 1 <= |Value| <= ElementBits for a right shift; or 5732/// 1 <= |Value| <= ElementBits/2 for a narrow right shift. 5733static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, 5734 int64_t &Cnt) { 5735 assert(VT.isVector() && "vector shift count is not a vector type"); 5736 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 5737 if (!getVShiftImm(Op, ElementBits, Cnt)) 5738 return false; 5739 if (isIntrinsic) 5740 Cnt = -Cnt; 5741 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits)); 5742} 5743 5744SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op, 5745 SelectionDAG &DAG) const { 5746 EVT VT = Op.getValueType(); 5747 SDLoc DL(Op); 5748 int64_t Cnt; 5749 5750 if (!Op.getOperand(1).getValueType().isVector()) 5751 return Op; 5752 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 5753 5754 switch (Op.getOpcode()) { 5755 default: 5756 llvm_unreachable("unexpected shift opcode"); 5757 5758 case ISD::SHL: 5759 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) 5760 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0), 5761 DAG.getConstant(Cnt, MVT::i32)); 5762 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 5763 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32), 5764 Op.getOperand(0), Op.getOperand(1)); 5765 case ISD::SRA: 5766 case ISD::SRL: 5767 // Right shift immediate 5768 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) && 5769 Cnt < EltSize) { 5770 unsigned Opc = 5771 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR; 5772 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0), 5773 DAG.getConstant(Cnt, MVT::i32)); 5774 } 5775 5776 // Right shift register. Note, there is not a shift right register 5777 // instruction, but the shift left register instruction takes a signed 5778 // value, where negative numbers specify a right shift. 5779 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl 5780 : Intrinsic::aarch64_neon_ushl; 5781 // negate the shift amount 5782 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1)); 5783 SDValue NegShiftLeft = 5784 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 5785 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift); 5786 return NegShiftLeft; 5787 } 5788 5789 return SDValue(); 5790} 5791 5792static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS, 5793 AArch64CC::CondCode CC, bool NoNans, EVT VT, 5794 SDLoc dl, SelectionDAG &DAG) { 5795 EVT SrcVT = LHS.getValueType(); 5796 5797 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode()); 5798 APInt CnstBits(VT.getSizeInBits(), 0); 5799 APInt UndefBits(VT.getSizeInBits(), 0); 5800 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits); 5801 bool IsZero = IsCnst && (CnstBits == 0); 5802 5803 if (SrcVT.getVectorElementType().isFloatingPoint()) { 5804 switch (CC) { 5805 default: 5806 return SDValue(); 5807 case AArch64CC::NE: { 5808 SDValue Fcmeq; 5809 if (IsZero) 5810 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS); 5811 else 5812 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS); 5813 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq); 5814 } 5815 case AArch64CC::EQ: 5816 if (IsZero) 5817 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS); 5818 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS); 5819 case AArch64CC::GE: 5820 if (IsZero) 5821 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS); 5822 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS); 5823 case AArch64CC::GT: 5824 if (IsZero) 5825 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS); 5826 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS); 5827 case AArch64CC::LS: 5828 if (IsZero) 5829 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS); 5830 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS); 5831 case AArch64CC::LT: 5832 if (!NoNans) 5833 return SDValue(); 5834 // If we ignore NaNs then we can use to the MI implementation. 5835 // Fallthrough. 5836 case AArch64CC::MI: 5837 if (IsZero) 5838 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS); 5839 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS); 5840 } 5841 } 5842 5843 switch (CC) { 5844 default: 5845 return SDValue(); 5846 case AArch64CC::NE: { 5847 SDValue Cmeq; 5848 if (IsZero) 5849 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS); 5850 else 5851 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS); 5852 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq); 5853 } 5854 case AArch64CC::EQ: 5855 if (IsZero) 5856 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS); 5857 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS); 5858 case AArch64CC::GE: 5859 if (IsZero) 5860 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS); 5861 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS); 5862 case AArch64CC::GT: 5863 if (IsZero) 5864 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS); 5865 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS); 5866 case AArch64CC::LE: 5867 if (IsZero) 5868 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS); 5869 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS); 5870 case AArch64CC::LS: 5871 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS); 5872 case AArch64CC::LO: 5873 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS); 5874 case AArch64CC::LT: 5875 if (IsZero) 5876 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS); 5877 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS); 5878 case AArch64CC::HI: 5879 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS); 5880 case AArch64CC::HS: 5881 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS); 5882 } 5883} 5884 5885SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op, 5886 SelectionDAG &DAG) const { 5887 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 5888 SDValue LHS = Op.getOperand(0); 5889 SDValue RHS = Op.getOperand(1); 5890 SDLoc dl(Op); 5891 5892 if (LHS.getValueType().getVectorElementType().isInteger()) { 5893 assert(LHS.getValueType() == RHS.getValueType()); 5894 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC); 5895 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(), 5896 dl, DAG); 5897 } 5898 5899 assert(LHS.getValueType().getVectorElementType() == MVT::f32 || 5900 LHS.getValueType().getVectorElementType() == MVT::f64); 5901 5902 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally 5903 // clean. Some of them require two branches to implement. 5904 AArch64CC::CondCode CC1, CC2; 5905 bool ShouldInvert; 5906 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert); 5907 5908 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath; 5909 SDValue Cmp = 5910 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG); 5911 if (!Cmp.getNode()) 5912 return SDValue(); 5913 5914 if (CC2 != AArch64CC::AL) { 5915 SDValue Cmp2 = 5916 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG); 5917 if (!Cmp2.getNode()) 5918 return SDValue(); 5919 5920 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2); 5921 } 5922 5923 if (ShouldInvert) 5924 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType()); 5925 5926 return Cmp; 5927} 5928 5929/// getTgtMemIntrinsic - Represent NEON load and store intrinsics as 5930/// MemIntrinsicNodes. The associated MachineMemOperands record the alignment 5931/// specified in the intrinsic calls. 5932bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, 5933 const CallInst &I, 5934 unsigned Intrinsic) const { 5935 switch (Intrinsic) { 5936 case Intrinsic::aarch64_neon_ld2: 5937 case Intrinsic::aarch64_neon_ld3: 5938 case Intrinsic::aarch64_neon_ld4: 5939 case Intrinsic::aarch64_neon_ld1x2: 5940 case Intrinsic::aarch64_neon_ld1x3: 5941 case Intrinsic::aarch64_neon_ld1x4: 5942 case Intrinsic::aarch64_neon_ld2lane: 5943 case Intrinsic::aarch64_neon_ld3lane: 5944 case Intrinsic::aarch64_neon_ld4lane: 5945 case Intrinsic::aarch64_neon_ld2r: 5946 case Intrinsic::aarch64_neon_ld3r: 5947 case Intrinsic::aarch64_neon_ld4r: { 5948 Info.opc = ISD::INTRINSIC_W_CHAIN; 5949 // Conservatively set memVT to the entire set of vectors loaded. 5950 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8; 5951 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 5952 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1); 5953 Info.offset = 0; 5954 Info.align = 0; 5955 Info.vol = false; // volatile loads with NEON intrinsics not supported 5956 Info.readMem = true; 5957 Info.writeMem = false; 5958 return true; 5959 } 5960 case Intrinsic::aarch64_neon_st2: 5961 case Intrinsic::aarch64_neon_st3: 5962 case Intrinsic::aarch64_neon_st4: 5963 case Intrinsic::aarch64_neon_st1x2: 5964 case Intrinsic::aarch64_neon_st1x3: 5965 case Intrinsic::aarch64_neon_st1x4: 5966 case Intrinsic::aarch64_neon_st2lane: 5967 case Intrinsic::aarch64_neon_st3lane: 5968 case Intrinsic::aarch64_neon_st4lane: { 5969 Info.opc = ISD::INTRINSIC_VOID; 5970 // Conservatively set memVT to the entire set of vectors stored. 5971 unsigned NumElts = 0; 5972 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) { 5973 Type *ArgTy = I.getArgOperand(ArgI)->getType(); 5974 if (!ArgTy->isVectorTy()) 5975 break; 5976 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8; 5977 } 5978 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 5979 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1); 5980 Info.offset = 0; 5981 Info.align = 0; 5982 Info.vol = false; // volatile stores with NEON intrinsics not supported 5983 Info.readMem = false; 5984 Info.writeMem = true; 5985 return true; 5986 } 5987 case Intrinsic::aarch64_ldaxr: 5988 case Intrinsic::aarch64_ldxr: { 5989 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType()); 5990 Info.opc = ISD::INTRINSIC_W_CHAIN; 5991 Info.memVT = MVT::getVT(PtrTy->getElementType()); 5992 Info.ptrVal = I.getArgOperand(0); 5993 Info.offset = 0; 5994 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType()); 5995 Info.vol = true; 5996 Info.readMem = true; 5997 Info.writeMem = false; 5998 return true; 5999 } 6000 case Intrinsic::aarch64_stlxr: 6001 case Intrinsic::aarch64_stxr: { 6002 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType()); 6003 Info.opc = ISD::INTRINSIC_W_CHAIN; 6004 Info.memVT = MVT::getVT(PtrTy->getElementType()); 6005 Info.ptrVal = I.getArgOperand(1); 6006 Info.offset = 0; 6007 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType()); 6008 Info.vol = true; 6009 Info.readMem = false; 6010 Info.writeMem = true; 6011 return true; 6012 } 6013 case Intrinsic::aarch64_ldaxp: 6014 case Intrinsic::aarch64_ldxp: { 6015 Info.opc = ISD::INTRINSIC_W_CHAIN; 6016 Info.memVT = MVT::i128; 6017 Info.ptrVal = I.getArgOperand(0); 6018 Info.offset = 0; 6019 Info.align = 16; 6020 Info.vol = true; 6021 Info.readMem = true; 6022 Info.writeMem = false; 6023 return true; 6024 } 6025 case Intrinsic::aarch64_stlxp: 6026 case Intrinsic::aarch64_stxp: { 6027 Info.opc = ISD::INTRINSIC_W_CHAIN; 6028 Info.memVT = MVT::i128; 6029 Info.ptrVal = I.getArgOperand(2); 6030 Info.offset = 0; 6031 Info.align = 16; 6032 Info.vol = true; 6033 Info.readMem = false; 6034 Info.writeMem = true; 6035 return true; 6036 } 6037 default: 6038 break; 6039 } 6040 6041 return false; 6042} 6043 6044// Truncations from 64-bit GPR to 32-bit GPR is free. 6045bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 6046 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 6047 return false; 6048 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 6049 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 6050 if (NumBits1 <= NumBits2) 6051 return false; 6052 return true; 6053} 6054bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 6055 if (!VT1.isInteger() || !VT2.isInteger()) 6056 return false; 6057 unsigned NumBits1 = VT1.getSizeInBits(); 6058 unsigned NumBits2 = VT2.getSizeInBits(); 6059 if (NumBits1 <= NumBits2) 6060 return false; 6061 return true; 6062} 6063 6064// All 32-bit GPR operations implicitly zero the high-half of the corresponding 6065// 64-bit GPR. 6066bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 6067 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 6068 return false; 6069 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 6070 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 6071 if (NumBits1 == 32 && NumBits2 == 64) 6072 return true; 6073 return false; 6074} 6075bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 6076 if (!VT1.isInteger() || !VT2.isInteger()) 6077 return false; 6078 unsigned NumBits1 = VT1.getSizeInBits(); 6079 unsigned NumBits2 = VT2.getSizeInBits(); 6080 if (NumBits1 == 32 && NumBits2 == 64) 6081 return true; 6082 return false; 6083} 6084 6085bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 6086 EVT VT1 = Val.getValueType(); 6087 if (isZExtFree(VT1, VT2)) { 6088 return true; 6089 } 6090 6091 if (Val.getOpcode() != ISD::LOAD) 6092 return false; 6093 6094 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend. 6095 return (VT1.isSimple() && VT1.isInteger() && VT2.isSimple() && 6096 VT2.isInteger() && VT1.getSizeInBits() <= 32); 6097} 6098 6099bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType, 6100 unsigned &RequiredAligment) const { 6101 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy()) 6102 return false; 6103 // Cyclone supports unaligned accesses. 6104 RequiredAligment = 0; 6105 unsigned NumBits = LoadedType->getPrimitiveSizeInBits(); 6106 return NumBits == 32 || NumBits == 64; 6107} 6108 6109bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType, 6110 unsigned &RequiredAligment) const { 6111 if (!LoadedType.isSimple() || 6112 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint())) 6113 return false; 6114 // Cyclone supports unaligned accesses. 6115 RequiredAligment = 0; 6116 unsigned NumBits = LoadedType.getSizeInBits(); 6117 return NumBits == 32 || NumBits == 64; 6118} 6119 6120static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign, 6121 unsigned AlignCheck) { 6122 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) && 6123 (DstAlign == 0 || DstAlign % AlignCheck == 0)); 6124} 6125 6126EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 6127 unsigned SrcAlign, bool IsMemset, 6128 bool ZeroMemset, 6129 bool MemcpyStrSrc, 6130 MachineFunction &MF) const { 6131 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one 6132 // instruction to materialize the v2i64 zero and one store (with restrictive 6133 // addressing mode). Just do two i64 store of zero-registers. 6134 bool Fast; 6135 const Function *F = MF.getFunction(); 6136 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 && 6137 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 6138 Attribute::NoImplicitFloat) && 6139 (memOpAlign(SrcAlign, DstAlign, 16) || 6140 (allowsUnalignedMemoryAccesses(MVT::f128, 0, &Fast) && Fast))) 6141 return MVT::f128; 6142 6143 return Size >= 8 ? MVT::i64 : MVT::i32; 6144} 6145 6146// 12-bit optionally shifted immediates are legal for adds. 6147bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const { 6148 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0)) 6149 return true; 6150 return false; 6151} 6152 6153// Integer comparisons are implemented with ADDS/SUBS, so the range of valid 6154// immediates is the same as for an add or a sub. 6155bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const { 6156 if (Immed < 0) 6157 Immed *= -1; 6158 return isLegalAddImmediate(Immed); 6159} 6160 6161/// isLegalAddressingMode - Return true if the addressing mode represented 6162/// by AM is legal for this target, for a load/store of the specified type. 6163bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM, 6164 Type *Ty) const { 6165 // AArch64 has five basic addressing modes: 6166 // reg 6167 // reg + 9-bit signed offset 6168 // reg + SIZE_IN_BYTES * 12-bit unsigned offset 6169 // reg1 + reg2 6170 // reg + SIZE_IN_BYTES * reg 6171 6172 // No global is ever allowed as a base. 6173 if (AM.BaseGV) 6174 return false; 6175 6176 // No reg+reg+imm addressing. 6177 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) 6178 return false; 6179 6180 // check reg + imm case: 6181 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12 6182 uint64_t NumBytes = 0; 6183 if (Ty->isSized()) { 6184 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty); 6185 NumBytes = NumBits / 8; 6186 if (!isPowerOf2_64(NumBits)) 6187 NumBytes = 0; 6188 } 6189 6190 if (!AM.Scale) { 6191 int64_t Offset = AM.BaseOffs; 6192 6193 // 9-bit signed offset 6194 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1) 6195 return true; 6196 6197 // 12-bit unsigned offset 6198 unsigned shift = Log2_64(NumBytes); 6199 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 && 6200 // Must be a multiple of NumBytes (NumBytes is a power of 2) 6201 (Offset >> shift) << shift == Offset) 6202 return true; 6203 return false; 6204 } 6205 6206 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2 6207 6208 if (!AM.Scale || AM.Scale == 1 || 6209 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes)) 6210 return true; 6211 return false; 6212} 6213 6214int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM, 6215 Type *Ty) const { 6216 // Scaling factors are not free at all. 6217 // Operands | Rt Latency 6218 // ------------------------------------------- 6219 // Rt, [Xn, Xm] | 4 6220 // ------------------------------------------- 6221 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5 6222 // Rt, [Xn, Wm, <extend> #imm] | 6223 if (isLegalAddressingMode(AM, Ty)) 6224 // Scale represents reg2 * scale, thus account for 1 if 6225 // it is not equal to 0 or 1. 6226 return AM.Scale != 0 && AM.Scale != 1; 6227 return -1; 6228} 6229 6230bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const { 6231 VT = VT.getScalarType(); 6232 6233 if (!VT.isSimple()) 6234 return false; 6235 6236 switch (VT.getSimpleVT().SimpleTy) { 6237 case MVT::f32: 6238 case MVT::f64: 6239 return true; 6240 default: 6241 break; 6242 } 6243 6244 return false; 6245} 6246 6247const MCPhysReg * 6248AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const { 6249 // LR is a callee-save register, but we must treat it as clobbered by any call 6250 // site. Hence we include LR in the scratch registers, which are in turn added 6251 // as implicit-defs for stackmaps and patchpoints. 6252 static const MCPhysReg ScratchRegs[] = { 6253 AArch64::X16, AArch64::X17, AArch64::LR, 0 6254 }; 6255 return ScratchRegs; 6256} 6257 6258bool 6259AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const { 6260 EVT VT = N->getValueType(0); 6261 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine 6262 // it with shift to let it be lowered to UBFX. 6263 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) && 6264 isa<ConstantSDNode>(N->getOperand(1))) { 6265 uint64_t TruncMask = N->getConstantOperandVal(1); 6266 if (isMask_64(TruncMask) && 6267 N->getOperand(0).getOpcode() == ISD::SRL && 6268 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1))) 6269 return false; 6270 } 6271 return true; 6272} 6273 6274bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, 6275 Type *Ty) const { 6276 assert(Ty->isIntegerTy()); 6277 6278 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 6279 if (BitSize == 0) 6280 return false; 6281 6282 int64_t Val = Imm.getSExtValue(); 6283 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize)) 6284 return true; 6285 6286 if ((int64_t)Val < 0) 6287 Val = ~Val; 6288 if (BitSize == 32) 6289 Val &= (1LL << 32) - 1; 6290 6291 unsigned LZ = countLeadingZeros((uint64_t)Val); 6292 unsigned Shift = (63 - LZ) / 16; 6293 // MOVZ is free so return true for one or fewer MOVK. 6294 return (Shift < 3) ? true : false; 6295} 6296 6297// Generate SUBS and CSEL for integer abs. 6298static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) { 6299 EVT VT = N->getValueType(0); 6300 6301 SDValue N0 = N->getOperand(0); 6302 SDValue N1 = N->getOperand(1); 6303 SDLoc DL(N); 6304 6305 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1) 6306 // and change it to SUB and CSEL. 6307 if (VT.isInteger() && N->getOpcode() == ISD::XOR && 6308 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 && 6309 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0)) 6310 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 6311 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) { 6312 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), 6313 N0.getOperand(0)); 6314 // Generate SUBS & CSEL. 6315 SDValue Cmp = 6316 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32), 6317 N0.getOperand(0), DAG.getConstant(0, VT)); 6318 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg, 6319 DAG.getConstant(AArch64CC::PL, MVT::i32), 6320 SDValue(Cmp.getNode(), 1)); 6321 } 6322 return SDValue(); 6323} 6324 6325// performXorCombine - Attempts to handle integer ABS. 6326static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG, 6327 TargetLowering::DAGCombinerInfo &DCI, 6328 const AArch64Subtarget *Subtarget) { 6329 if (DCI.isBeforeLegalizeOps()) 6330 return SDValue(); 6331 6332 return performIntegerAbsCombine(N, DAG); 6333} 6334 6335static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG, 6336 TargetLowering::DAGCombinerInfo &DCI, 6337 const AArch64Subtarget *Subtarget) { 6338 if (DCI.isBeforeLegalizeOps()) 6339 return SDValue(); 6340 6341 // Multiplication of a power of two plus/minus one can be done more 6342 // cheaply as as shift+add/sub. For now, this is true unilaterally. If 6343 // future CPUs have a cheaper MADD instruction, this may need to be 6344 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and 6345 // 64-bit is 5 cycles, so this is always a win. 6346 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 6347 APInt Value = C->getAPIntValue(); 6348 EVT VT = N->getValueType(0); 6349 APInt VP1 = Value + 1; 6350 if (VP1.isPowerOf2()) { 6351 // Multiplying by one less than a power of two, replace with a shift 6352 // and a subtract. 6353 SDValue ShiftedVal = 6354 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0), 6355 DAG.getConstant(VP1.logBase2(), MVT::i64)); 6356 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal, N->getOperand(0)); 6357 } 6358 APInt VM1 = Value - 1; 6359 if (VM1.isPowerOf2()) { 6360 // Multiplying by one more than a power of two, replace with a shift 6361 // and an add. 6362 SDValue ShiftedVal = 6363 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0), 6364 DAG.getConstant(VM1.logBase2(), MVT::i64)); 6365 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0)); 6366 } 6367 } 6368 return SDValue(); 6369} 6370 6371static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) { 6372 EVT VT = N->getValueType(0); 6373 if (VT != MVT::f32 && VT != MVT::f64) 6374 return SDValue(); 6375 // Only optimize when the source and destination types have the same width. 6376 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits()) 6377 return SDValue(); 6378 6379 // If the result of an integer load is only used by an integer-to-float 6380 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead. 6381 // This eliminates an "integer-to-vector-move UOP and improve throughput. 6382 SDValue N0 = N->getOperand(0); 6383 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6384 // Do not change the width of a volatile load. 6385 !cast<LoadSDNode>(N0)->isVolatile()) { 6386 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6387 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(), 6388 LN0->getPointerInfo(), LN0->isVolatile(), 6389 LN0->isNonTemporal(), LN0->isInvariant(), 6390 LN0->getAlignment()); 6391 6392 // Make sure successors of the original load stay after it by updating them 6393 // to use the new Chain. 6394 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1)); 6395 6396 unsigned Opcode = 6397 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF; 6398 return DAG.getNode(Opcode, SDLoc(N), VT, Load); 6399 } 6400 6401 return SDValue(); 6402} 6403 6404/// An EXTR instruction is made up of two shifts, ORed together. This helper 6405/// searches for and classifies those shifts. 6406static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount, 6407 bool &FromHi) { 6408 if (N.getOpcode() == ISD::SHL) 6409 FromHi = false; 6410 else if (N.getOpcode() == ISD::SRL) 6411 FromHi = true; 6412 else 6413 return false; 6414 6415 if (!isa<ConstantSDNode>(N.getOperand(1))) 6416 return false; 6417 6418 ShiftAmount = N->getConstantOperandVal(1); 6419 Src = N->getOperand(0); 6420 return true; 6421} 6422 6423/// EXTR instruction extracts a contiguous chunk of bits from two existing 6424/// registers viewed as a high/low pair. This function looks for the pattern: 6425/// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an 6426/// EXTR. Can't quite be done in TableGen because the two immediates aren't 6427/// independent. 6428static SDValue tryCombineToEXTR(SDNode *N, 6429 TargetLowering::DAGCombinerInfo &DCI) { 6430 SelectionDAG &DAG = DCI.DAG; 6431 SDLoc DL(N); 6432 EVT VT = N->getValueType(0); 6433 6434 assert(N->getOpcode() == ISD::OR && "Unexpected root"); 6435 6436 if (VT != MVT::i32 && VT != MVT::i64) 6437 return SDValue(); 6438 6439 SDValue LHS; 6440 uint32_t ShiftLHS = 0; 6441 bool LHSFromHi = 0; 6442 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi)) 6443 return SDValue(); 6444 6445 SDValue RHS; 6446 uint32_t ShiftRHS = 0; 6447 bool RHSFromHi = 0; 6448 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi)) 6449 return SDValue(); 6450 6451 // If they're both trying to come from the high part of the register, they're 6452 // not really an EXTR. 6453 if (LHSFromHi == RHSFromHi) 6454 return SDValue(); 6455 6456 if (ShiftLHS + ShiftRHS != VT.getSizeInBits()) 6457 return SDValue(); 6458 6459 if (LHSFromHi) { 6460 std::swap(LHS, RHS); 6461 std::swap(ShiftLHS, ShiftRHS); 6462 } 6463 6464 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS, 6465 DAG.getConstant(ShiftRHS, MVT::i64)); 6466} 6467 6468static SDValue tryCombineToBSL(SDNode *N, 6469 TargetLowering::DAGCombinerInfo &DCI) { 6470 EVT VT = N->getValueType(0); 6471 SelectionDAG &DAG = DCI.DAG; 6472 SDLoc DL(N); 6473 6474 if (!VT.isVector()) 6475 return SDValue(); 6476 6477 SDValue N0 = N->getOperand(0); 6478 if (N0.getOpcode() != ISD::AND) 6479 return SDValue(); 6480 6481 SDValue N1 = N->getOperand(1); 6482 if (N1.getOpcode() != ISD::AND) 6483 return SDValue(); 6484 6485 // We only have to look for constant vectors here since the general, variable 6486 // case can be handled in TableGen. 6487 unsigned Bits = VT.getVectorElementType().getSizeInBits(); 6488 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1); 6489 for (int i = 1; i >= 0; --i) 6490 for (int j = 1; j >= 0; --j) { 6491 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i)); 6492 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j)); 6493 if (!BVN0 || !BVN1) 6494 continue; 6495 6496 bool FoundMatch = true; 6497 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) { 6498 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k)); 6499 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k)); 6500 if (!CN0 || !CN1 || 6501 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) { 6502 FoundMatch = false; 6503 break; 6504 } 6505 } 6506 6507 if (FoundMatch) 6508 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0), 6509 N0->getOperand(1 - i), N1->getOperand(1 - j)); 6510 } 6511 6512 return SDValue(); 6513} 6514 6515static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, 6516 const AArch64Subtarget *Subtarget) { 6517 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) 6518 if (!EnableAArch64ExtrGeneration) 6519 return SDValue(); 6520 SelectionDAG &DAG = DCI.DAG; 6521 EVT VT = N->getValueType(0); 6522 6523 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 6524 return SDValue(); 6525 6526 SDValue Res = tryCombineToEXTR(N, DCI); 6527 if (Res.getNode()) 6528 return Res; 6529 6530 Res = tryCombineToBSL(N, DCI); 6531 if (Res.getNode()) 6532 return Res; 6533 6534 return SDValue(); 6535} 6536 6537static SDValue performBitcastCombine(SDNode *N, 6538 TargetLowering::DAGCombinerInfo &DCI, 6539 SelectionDAG &DAG) { 6540 // Wait 'til after everything is legalized to try this. That way we have 6541 // legal vector types and such. 6542 if (DCI.isBeforeLegalizeOps()) 6543 return SDValue(); 6544 6545 // Remove extraneous bitcasts around an extract_subvector. 6546 // For example, 6547 // (v4i16 (bitconvert 6548 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1))))) 6549 // becomes 6550 // (extract_subvector ((v8i16 ...), (i64 4))) 6551 6552 // Only interested in 64-bit vectors as the ultimate result. 6553 EVT VT = N->getValueType(0); 6554 if (!VT.isVector()) 6555 return SDValue(); 6556 if (VT.getSimpleVT().getSizeInBits() != 64) 6557 return SDValue(); 6558 // Is the operand an extract_subvector starting at the beginning or halfway 6559 // point of the vector? A low half may also come through as an 6560 // EXTRACT_SUBREG, so look for that, too. 6561 SDValue Op0 = N->getOperand(0); 6562 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR && 6563 !(Op0->isMachineOpcode() && 6564 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG)) 6565 return SDValue(); 6566 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue(); 6567 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) { 6568 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0) 6569 return SDValue(); 6570 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) { 6571 if (idx != AArch64::dsub) 6572 return SDValue(); 6573 // The dsub reference is equivalent to a lane zero subvector reference. 6574 idx = 0; 6575 } 6576 // Look through the bitcast of the input to the extract. 6577 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST) 6578 return SDValue(); 6579 SDValue Source = Op0->getOperand(0)->getOperand(0); 6580 // If the source type has twice the number of elements as our destination 6581 // type, we know this is an extract of the high or low half of the vector. 6582 EVT SVT = Source->getValueType(0); 6583 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2) 6584 return SDValue(); 6585 6586 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n"); 6587 6588 // Create the simplified form to just extract the low or high half of the 6589 // vector directly rather than bothering with the bitcasts. 6590 SDLoc dl(N); 6591 unsigned NumElements = VT.getVectorNumElements(); 6592 if (idx) { 6593 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64); 6594 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx); 6595 } else { 6596 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32); 6597 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT, 6598 Source, SubReg), 6599 0); 6600 } 6601} 6602 6603static SDValue performConcatVectorsCombine(SDNode *N, 6604 TargetLowering::DAGCombinerInfo &DCI, 6605 SelectionDAG &DAG) { 6606 // Wait 'til after everything is legalized to try this. That way we have 6607 // legal vector types and such. 6608 if (DCI.isBeforeLegalizeOps()) 6609 return SDValue(); 6610 6611 SDLoc dl(N); 6612 EVT VT = N->getValueType(0); 6613 6614 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector 6615 // splat. The indexed instructions are going to be expecting a DUPLANE64, so 6616 // canonicalise to that. 6617 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) { 6618 assert(VT.getVectorElementType().getSizeInBits() == 64); 6619 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, 6620 WidenVector(N->getOperand(0), DAG), 6621 DAG.getConstant(0, MVT::i64)); 6622 } 6623 6624 // Canonicalise concat_vectors so that the right-hand vector has as few 6625 // bit-casts as possible before its real operation. The primary matching 6626 // destination for these operations will be the narrowing "2" instructions, 6627 // which depend on the operation being performed on this right-hand vector. 6628 // For example, 6629 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS)))) 6630 // becomes 6631 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS)) 6632 6633 SDValue Op1 = N->getOperand(1); 6634 if (Op1->getOpcode() != ISD::BITCAST) 6635 return SDValue(); 6636 SDValue RHS = Op1->getOperand(0); 6637 MVT RHSTy = RHS.getValueType().getSimpleVT(); 6638 // If the RHS is not a vector, this is not the pattern we're looking for. 6639 if (!RHSTy.isVector()) 6640 return SDValue(); 6641 6642 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n"); 6643 6644 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(), 6645 RHSTy.getVectorNumElements() * 2); 6646 return DAG.getNode( 6647 ISD::BITCAST, dl, VT, 6648 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy, 6649 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS)); 6650} 6651 6652static SDValue tryCombineFixedPointConvert(SDNode *N, 6653 TargetLowering::DAGCombinerInfo &DCI, 6654 SelectionDAG &DAG) { 6655 // Wait 'til after everything is legalized to try this. That way we have 6656 // legal vector types and such. 6657 if (DCI.isBeforeLegalizeOps()) 6658 return SDValue(); 6659 // Transform a scalar conversion of a value from a lane extract into a 6660 // lane extract of a vector conversion. E.g., from foo1 to foo2: 6661 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); } 6662 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; } 6663 // 6664 // The second form interacts better with instruction selection and the 6665 // register allocator to avoid cross-class register copies that aren't 6666 // coalescable due to a lane reference. 6667 6668 // Check the operand and see if it originates from a lane extract. 6669 SDValue Op1 = N->getOperand(1); 6670 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 6671 // Yep, no additional predication needed. Perform the transform. 6672 SDValue IID = N->getOperand(0); 6673 SDValue Shift = N->getOperand(2); 6674 SDValue Vec = Op1.getOperand(0); 6675 SDValue Lane = Op1.getOperand(1); 6676 EVT ResTy = N->getValueType(0); 6677 EVT VecResTy; 6678 SDLoc DL(N); 6679 6680 // The vector width should be 128 bits by the time we get here, even 6681 // if it started as 64 bits (the extract_vector handling will have 6682 // done so). 6683 assert(Vec.getValueType().getSizeInBits() == 128 && 6684 "unexpected vector size on extract_vector_elt!"); 6685 if (Vec.getValueType() == MVT::v4i32) 6686 VecResTy = MVT::v4f32; 6687 else if (Vec.getValueType() == MVT::v2i64) 6688 VecResTy = MVT::v2f64; 6689 else 6690 assert(0 && "unexpected vector type!"); 6691 6692 SDValue Convert = 6693 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift); 6694 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane); 6695 } 6696 return SDValue(); 6697} 6698 6699// AArch64 high-vector "long" operations are formed by performing the non-high 6700// version on an extract_subvector of each operand which gets the high half: 6701// 6702// (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS)) 6703// 6704// However, there are cases which don't have an extract_high explicitly, but 6705// have another operation that can be made compatible with one for free. For 6706// example: 6707// 6708// (dupv64 scalar) --> (extract_high (dup128 scalar)) 6709// 6710// This routine does the actual conversion of such DUPs, once outer routines 6711// have determined that everything else is in order. 6712static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) { 6713 // We can handle most types of duplicate, but the lane ones have an extra 6714 // operand saying *which* lane, so we need to know. 6715 bool IsDUPLANE; 6716 switch (N.getOpcode()) { 6717 case AArch64ISD::DUP: 6718 IsDUPLANE = false; 6719 break; 6720 case AArch64ISD::DUPLANE8: 6721 case AArch64ISD::DUPLANE16: 6722 case AArch64ISD::DUPLANE32: 6723 case AArch64ISD::DUPLANE64: 6724 IsDUPLANE = true; 6725 break; 6726 default: 6727 return SDValue(); 6728 } 6729 6730 MVT NarrowTy = N.getSimpleValueType(); 6731 if (!NarrowTy.is64BitVector()) 6732 return SDValue(); 6733 6734 MVT ElementTy = NarrowTy.getVectorElementType(); 6735 unsigned NumElems = NarrowTy.getVectorNumElements(); 6736 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2); 6737 6738 SDValue NewDUP; 6739 if (IsDUPLANE) 6740 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0), 6741 N.getOperand(1)); 6742 else 6743 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0)); 6744 6745 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy, 6746 NewDUP, DAG.getConstant(NumElems, MVT::i64)); 6747} 6748 6749static bool isEssentiallyExtractSubvector(SDValue N) { 6750 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR) 6751 return true; 6752 6753 return N.getOpcode() == ISD::BITCAST && 6754 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR; 6755} 6756 6757/// \brief Helper structure to keep track of ISD::SET_CC operands. 6758struct GenericSetCCInfo { 6759 const SDValue *Opnd0; 6760 const SDValue *Opnd1; 6761 ISD::CondCode CC; 6762}; 6763 6764/// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code. 6765struct AArch64SetCCInfo { 6766 const SDValue *Cmp; 6767 AArch64CC::CondCode CC; 6768}; 6769 6770/// \brief Helper structure to keep track of SetCC information. 6771union SetCCInfo { 6772 GenericSetCCInfo Generic; 6773 AArch64SetCCInfo AArch64; 6774}; 6775 6776/// \brief Helper structure to be able to read SetCC information. If set to 6777/// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a 6778/// GenericSetCCInfo. 6779struct SetCCInfoAndKind { 6780 SetCCInfo Info; 6781 bool IsAArch64; 6782}; 6783 6784/// \brief Check whether or not \p Op is a SET_CC operation, either a generic or 6785/// an 6786/// AArch64 lowered one. 6787/// \p SetCCInfo is filled accordingly. 6788/// \post SetCCInfo is meanginfull only when this function returns true. 6789/// \return True when Op is a kind of SET_CC operation. 6790static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) { 6791 // If this is a setcc, this is straight forward. 6792 if (Op.getOpcode() == ISD::SETCC) { 6793 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0); 6794 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1); 6795 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 6796 SetCCInfo.IsAArch64 = false; 6797 return true; 6798 } 6799 // Otherwise, check if this is a matching csel instruction. 6800 // In other words: 6801 // - csel 1, 0, cc 6802 // - csel 0, 1, !cc 6803 if (Op.getOpcode() != AArch64ISD::CSEL) 6804 return false; 6805 // Set the information about the operands. 6806 // TODO: we want the operands of the Cmp not the csel 6807 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3); 6808 SetCCInfo.IsAArch64 = true; 6809 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>( 6810 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 6811 6812 // Check that the operands matches the constraints: 6813 // (1) Both operands must be constants. 6814 // (2) One must be 1 and the other must be 0. 6815 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 6816 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 6817 6818 // Check (1). 6819 if (!TValue || !FValue) 6820 return false; 6821 6822 // Check (2). 6823 if (!TValue->isOne()) { 6824 // Update the comparison when we are interested in !cc. 6825 std::swap(TValue, FValue); 6826 SetCCInfo.Info.AArch64.CC = 6827 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC); 6828 } 6829 return TValue->isOne() && FValue->isNullValue(); 6830} 6831 6832// Returns true if Op is setcc or zext of setcc. 6833static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) { 6834 if (isSetCC(Op, Info)) 6835 return true; 6836 return ((Op.getOpcode() == ISD::ZERO_EXTEND) && 6837 isSetCC(Op->getOperand(0), Info)); 6838} 6839 6840// The folding we want to perform is: 6841// (add x, [zext] (setcc cc ...) ) 6842// --> 6843// (csel x, (add x, 1), !cc ...) 6844// 6845// The latter will get matched to a CSINC instruction. 6846static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) { 6847 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!"); 6848 SDValue LHS = Op->getOperand(0); 6849 SDValue RHS = Op->getOperand(1); 6850 SetCCInfoAndKind InfoAndKind; 6851 6852 // If neither operand is a SET_CC, give up. 6853 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) { 6854 std::swap(LHS, RHS); 6855 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) 6856 return SDValue(); 6857 } 6858 6859 // FIXME: This could be generatized to work for FP comparisons. 6860 EVT CmpVT = InfoAndKind.IsAArch64 6861 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType() 6862 : InfoAndKind.Info.Generic.Opnd0->getValueType(); 6863 if (CmpVT != MVT::i32 && CmpVT != MVT::i64) 6864 return SDValue(); 6865 6866 SDValue CCVal; 6867 SDValue Cmp; 6868 SDLoc dl(Op); 6869 if (InfoAndKind.IsAArch64) { 6870 CCVal = DAG.getConstant( 6871 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32); 6872 Cmp = *InfoAndKind.Info.AArch64.Cmp; 6873 } else 6874 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0, 6875 *InfoAndKind.Info.Generic.Opnd1, 6876 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true), 6877 CCVal, DAG, dl); 6878 6879 EVT VT = Op->getValueType(0); 6880 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT)); 6881 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp); 6882} 6883 6884// The basic add/sub long vector instructions have variants with "2" on the end 6885// which act on the high-half of their inputs. They are normally matched by 6886// patterns like: 6887// 6888// (add (zeroext (extract_high LHS)), 6889// (zeroext (extract_high RHS))) 6890// -> uaddl2 vD, vN, vM 6891// 6892// However, if one of the extracts is something like a duplicate, this 6893// instruction can still be used profitably. This function puts the DAG into a 6894// more appropriate form for those patterns to trigger. 6895static SDValue performAddSubLongCombine(SDNode *N, 6896 TargetLowering::DAGCombinerInfo &DCI, 6897 SelectionDAG &DAG) { 6898 if (DCI.isBeforeLegalizeOps()) 6899 return SDValue(); 6900 6901 MVT VT = N->getSimpleValueType(0); 6902 if (!VT.is128BitVector()) { 6903 if (N->getOpcode() == ISD::ADD) 6904 return performSetccAddFolding(N, DAG); 6905 return SDValue(); 6906 } 6907 6908 // Make sure both branches are extended in the same way. 6909 SDValue LHS = N->getOperand(0); 6910 SDValue RHS = N->getOperand(1); 6911 if ((LHS.getOpcode() != ISD::ZERO_EXTEND && 6912 LHS.getOpcode() != ISD::SIGN_EXTEND) || 6913 LHS.getOpcode() != RHS.getOpcode()) 6914 return SDValue(); 6915 6916 unsigned ExtType = LHS.getOpcode(); 6917 6918 // It's not worth doing if at least one of the inputs isn't already an 6919 // extract, but we don't know which it'll be so we have to try both. 6920 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) { 6921 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG); 6922 if (!RHS.getNode()) 6923 return SDValue(); 6924 6925 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS); 6926 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) { 6927 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG); 6928 if (!LHS.getNode()) 6929 return SDValue(); 6930 6931 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS); 6932 } 6933 6934 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS); 6935} 6936 6937// Massage DAGs which we can use the high-half "long" operations on into 6938// something isel will recognize better. E.g. 6939// 6940// (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) --> 6941// (aarch64_neon_umull (extract_high (v2i64 vec))) 6942// (extract_high (v2i64 (dup128 scalar))))) 6943// 6944static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N, 6945 TargetLowering::DAGCombinerInfo &DCI, 6946 SelectionDAG &DAG) { 6947 if (DCI.isBeforeLegalizeOps()) 6948 return SDValue(); 6949 6950 SDValue LHS = N->getOperand(1); 6951 SDValue RHS = N->getOperand(2); 6952 assert(LHS.getValueType().is64BitVector() && 6953 RHS.getValueType().is64BitVector() && 6954 "unexpected shape for long operation"); 6955 6956 // Either node could be a DUP, but it's not worth doing both of them (you'd 6957 // just as well use the non-high version) so look for a corresponding extract 6958 // operation on the other "wing". 6959 if (isEssentiallyExtractSubvector(LHS)) { 6960 RHS = tryExtendDUPToExtractHigh(RHS, DAG); 6961 if (!RHS.getNode()) 6962 return SDValue(); 6963 } else if (isEssentiallyExtractSubvector(RHS)) { 6964 LHS = tryExtendDUPToExtractHigh(LHS, DAG); 6965 if (!LHS.getNode()) 6966 return SDValue(); 6967 } 6968 6969 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0), 6970 N->getOperand(0), LHS, RHS); 6971} 6972 6973static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) { 6974 MVT ElemTy = N->getSimpleValueType(0).getScalarType(); 6975 unsigned ElemBits = ElemTy.getSizeInBits(); 6976 6977 int64_t ShiftAmount; 6978 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) { 6979 APInt SplatValue, SplatUndef; 6980 unsigned SplatBitSize; 6981 bool HasAnyUndefs; 6982 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 6983 HasAnyUndefs, ElemBits) || 6984 SplatBitSize != ElemBits) 6985 return SDValue(); 6986 6987 ShiftAmount = SplatValue.getSExtValue(); 6988 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) { 6989 ShiftAmount = CVN->getSExtValue(); 6990 } else 6991 return SDValue(); 6992 6993 unsigned Opcode; 6994 bool IsRightShift; 6995 switch (IID) { 6996 default: 6997 llvm_unreachable("Unknown shift intrinsic"); 6998 case Intrinsic::aarch64_neon_sqshl: 6999 Opcode = AArch64ISD::SQSHL_I; 7000 IsRightShift = false; 7001 break; 7002 case Intrinsic::aarch64_neon_uqshl: 7003 Opcode = AArch64ISD::UQSHL_I; 7004 IsRightShift = false; 7005 break; 7006 case Intrinsic::aarch64_neon_srshl: 7007 Opcode = AArch64ISD::SRSHR_I; 7008 IsRightShift = true; 7009 break; 7010 case Intrinsic::aarch64_neon_urshl: 7011 Opcode = AArch64ISD::URSHR_I; 7012 IsRightShift = true; 7013 break; 7014 case Intrinsic::aarch64_neon_sqshlu: 7015 Opcode = AArch64ISD::SQSHLU_I; 7016 IsRightShift = false; 7017 break; 7018 } 7019 7020 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) 7021 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1), 7022 DAG.getConstant(-ShiftAmount, MVT::i32)); 7023 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount <= ElemBits) 7024 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1), 7025 DAG.getConstant(ShiftAmount, MVT::i32)); 7026 7027 return SDValue(); 7028} 7029 7030// The CRC32[BH] instructions ignore the high bits of their data operand. Since 7031// the intrinsics must be legal and take an i32, this means there's almost 7032// certainly going to be a zext in the DAG which we can eliminate. 7033static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) { 7034 SDValue AndN = N->getOperand(2); 7035 if (AndN.getOpcode() != ISD::AND) 7036 return SDValue(); 7037 7038 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1)); 7039 if (!CMask || CMask->getZExtValue() != Mask) 7040 return SDValue(); 7041 7042 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32, 7043 N->getOperand(0), N->getOperand(1), AndN.getOperand(0)); 7044} 7045 7046static SDValue performIntrinsicCombine(SDNode *N, 7047 TargetLowering::DAGCombinerInfo &DCI, 7048 const AArch64Subtarget *Subtarget) { 7049 SelectionDAG &DAG = DCI.DAG; 7050 unsigned IID = getIntrinsicID(N); 7051 switch (IID) { 7052 default: 7053 break; 7054 case Intrinsic::aarch64_neon_vcvtfxs2fp: 7055 case Intrinsic::aarch64_neon_vcvtfxu2fp: 7056 return tryCombineFixedPointConvert(N, DCI, DAG); 7057 break; 7058 case Intrinsic::aarch64_neon_fmax: 7059 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0), 7060 N->getOperand(1), N->getOperand(2)); 7061 case Intrinsic::aarch64_neon_fmin: 7062 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0), 7063 N->getOperand(1), N->getOperand(2)); 7064 case Intrinsic::aarch64_neon_smull: 7065 case Intrinsic::aarch64_neon_umull: 7066 case Intrinsic::aarch64_neon_pmull: 7067 case Intrinsic::aarch64_neon_sqdmull: 7068 return tryCombineLongOpWithDup(IID, N, DCI, DAG); 7069 case Intrinsic::aarch64_neon_sqshl: 7070 case Intrinsic::aarch64_neon_uqshl: 7071 case Intrinsic::aarch64_neon_sqshlu: 7072 case Intrinsic::aarch64_neon_srshl: 7073 case Intrinsic::aarch64_neon_urshl: 7074 return tryCombineShiftImm(IID, N, DAG); 7075 case Intrinsic::aarch64_crc32b: 7076 case Intrinsic::aarch64_crc32cb: 7077 return tryCombineCRC32(0xff, N, DAG); 7078 case Intrinsic::aarch64_crc32h: 7079 case Intrinsic::aarch64_crc32ch: 7080 return tryCombineCRC32(0xffff, N, DAG); 7081 } 7082 return SDValue(); 7083} 7084 7085static SDValue performExtendCombine(SDNode *N, 7086 TargetLowering::DAGCombinerInfo &DCI, 7087 SelectionDAG &DAG) { 7088 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then 7089 // we can convert that DUP into another extract_high (of a bigger DUP), which 7090 // helps the backend to decide that an sabdl2 would be useful, saving a real 7091 // extract_high operation. 7092 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND && 7093 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) { 7094 SDNode *ABDNode = N->getOperand(0).getNode(); 7095 unsigned IID = getIntrinsicID(ABDNode); 7096 if (IID == Intrinsic::aarch64_neon_sabd || 7097 IID == Intrinsic::aarch64_neon_uabd) { 7098 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG); 7099 if (!NewABD.getNode()) 7100 return SDValue(); 7101 7102 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0), 7103 NewABD); 7104 } 7105 } 7106 7107 // This is effectively a custom type legalization for AArch64. 7108 // 7109 // Type legalization will split an extend of a small, legal, type to a larger 7110 // illegal type by first splitting the destination type, often creating 7111 // illegal source types, which then get legalized in isel-confusing ways, 7112 // leading to really terrible codegen. E.g., 7113 // %result = v8i32 sext v8i8 %value 7114 // becomes 7115 // %losrc = extract_subreg %value, ... 7116 // %hisrc = extract_subreg %value, ... 7117 // %lo = v4i32 sext v4i8 %losrc 7118 // %hi = v4i32 sext v4i8 %hisrc 7119 // Things go rapidly downhill from there. 7120 // 7121 // For AArch64, the [sz]ext vector instructions can only go up one element 7122 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32 7123 // take two instructions. 7124 // 7125 // This implies that the most efficient way to do the extend from v8i8 7126 // to two v4i32 values is to first extend the v8i8 to v8i16, then do 7127 // the normal splitting to happen for the v8i16->v8i32. 7128 7129 // This is pre-legalization to catch some cases where the default 7130 // type legalization will create ill-tempered code. 7131 if (!DCI.isBeforeLegalizeOps()) 7132 return SDValue(); 7133 7134 // We're only interested in cleaning things up for non-legal vector types 7135 // here. If both the source and destination are legal, things will just 7136 // work naturally without any fiddling. 7137 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7138 EVT ResVT = N->getValueType(0); 7139 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT)) 7140 return SDValue(); 7141 // If the vector type isn't a simple VT, it's beyond the scope of what 7142 // we're worried about here. Let legalization do its thing and hope for 7143 // the best. 7144 if (!ResVT.isSimple()) 7145 return SDValue(); 7146 7147 SDValue Src = N->getOperand(0); 7148 MVT SrcVT = Src->getValueType(0).getSimpleVT(); 7149 // If the source VT is a 64-bit vector, we can play games and get the 7150 // better results we want. 7151 if (SrcVT.getSizeInBits() != 64) 7152 return SDValue(); 7153 7154 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits(); 7155 unsigned ElementCount = SrcVT.getVectorNumElements(); 7156 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount); 7157 SDLoc DL(N); 7158 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src); 7159 7160 // Now split the rest of the operation into two halves, each with a 64 7161 // bit source. 7162 EVT LoVT, HiVT; 7163 SDValue Lo, Hi; 7164 unsigned NumElements = ResVT.getVectorNumElements(); 7165 assert(!(NumElements & 1) && "Splitting vector, but not in half!"); 7166 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(), 7167 ResVT.getVectorElementType(), NumElements / 2); 7168 7169 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(), 7170 LoVT.getVectorNumElements()); 7171 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src, 7172 DAG.getIntPtrConstant(0)); 7173 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src, 7174 DAG.getIntPtrConstant(InNVT.getVectorNumElements())); 7175 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo); 7176 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi); 7177 7178 // Now combine the parts back together so we still have a single result 7179 // like the combiner expects. 7180 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); 7181} 7182 7183/// Replace a splat of a scalar to a vector store by scalar stores of the scalar 7184/// value. The load store optimizer pass will merge them to store pair stores. 7185/// This has better performance than a splat of the scalar followed by a split 7186/// vector store. Even if the stores are not merged it is four stores vs a dup, 7187/// followed by an ext.b and two stores. 7188static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) { 7189 SDValue StVal = St->getValue(); 7190 EVT VT = StVal.getValueType(); 7191 7192 // Don't replace floating point stores, they possibly won't be transformed to 7193 // stp because of the store pair suppress pass. 7194 if (VT.isFloatingPoint()) 7195 return SDValue(); 7196 7197 // Check for insert vector elements. 7198 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT) 7199 return SDValue(); 7200 7201 // We can express a splat as store pair(s) for 2 or 4 elements. 7202 unsigned NumVecElts = VT.getVectorNumElements(); 7203 if (NumVecElts != 4 && NumVecElts != 2) 7204 return SDValue(); 7205 SDValue SplatVal = StVal.getOperand(1); 7206 unsigned RemainInsertElts = NumVecElts - 1; 7207 7208 // Check that this is a splat. 7209 while (--RemainInsertElts) { 7210 SDValue NextInsertElt = StVal.getOperand(0); 7211 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT) 7212 return SDValue(); 7213 if (NextInsertElt.getOperand(1) != SplatVal) 7214 return SDValue(); 7215 StVal = NextInsertElt; 7216 } 7217 unsigned OrigAlignment = St->getAlignment(); 7218 unsigned EltOffset = NumVecElts == 4 ? 4 : 8; 7219 unsigned Alignment = std::min(OrigAlignment, EltOffset); 7220 7221 // Create scalar stores. This is at least as good as the code sequence for a 7222 // split unaligned store wich is a dup.s, ext.b, and two stores. 7223 // Most of the time the three stores should be replaced by store pair 7224 // instructions (stp). 7225 SDLoc DL(St); 7226 SDValue BasePtr = St->getBasePtr(); 7227 SDValue NewST1 = 7228 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(), 7229 St->isVolatile(), St->isNonTemporal(), St->getAlignment()); 7230 7231 unsigned Offset = EltOffset; 7232 while (--NumVecElts) { 7233 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr, 7234 DAG.getConstant(Offset, MVT::i64)); 7235 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr, 7236 St->getPointerInfo(), St->isVolatile(), 7237 St->isNonTemporal(), Alignment); 7238 Offset += EltOffset; 7239 } 7240 return NewST1; 7241} 7242 7243static SDValue performSTORECombine(SDNode *N, 7244 TargetLowering::DAGCombinerInfo &DCI, 7245 SelectionDAG &DAG, 7246 const AArch64Subtarget *Subtarget) { 7247 if (!DCI.isBeforeLegalize()) 7248 return SDValue(); 7249 7250 StoreSDNode *S = cast<StoreSDNode>(N); 7251 if (S->isVolatile()) 7252 return SDValue(); 7253 7254 // Cyclone has bad performance on unaligned 16B stores when crossing line and 7255 // page boundries. We want to split such stores. 7256 if (!Subtarget->isCyclone()) 7257 return SDValue(); 7258 7259 // Don't split at Oz. 7260 MachineFunction &MF = DAG.getMachineFunction(); 7261 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute( 7262 AttributeSet::FunctionIndex, Attribute::MinSize); 7263 if (IsMinSize) 7264 return SDValue(); 7265 7266 SDValue StVal = S->getValue(); 7267 EVT VT = StVal.getValueType(); 7268 7269 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting 7270 // those up regresses performance on micro-benchmarks and olden/bh. 7271 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64) 7272 return SDValue(); 7273 7274 // Split unaligned 16B stores. They are terrible for performance. 7275 // Don't split stores with alignment of 1 or 2. Code that uses clang vector 7276 // extensions can use this to mark that it does not want splitting to happen 7277 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of 7278 // eliminating alignment hazards is only 1 in 8 for alignment of 2. 7279 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 || 7280 S->getAlignment() <= 2) 7281 return SDValue(); 7282 7283 // If we get a splat of a scalar convert this vector store to a store of 7284 // scalars. They will be merged into store pairs thereby removing two 7285 // instructions. 7286 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S); 7287 if (ReplacedSplat != SDValue()) 7288 return ReplacedSplat; 7289 7290 SDLoc DL(S); 7291 unsigned NumElts = VT.getVectorNumElements() / 2; 7292 // Split VT into two. 7293 EVT HalfVT = 7294 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts); 7295 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, 7296 DAG.getIntPtrConstant(0)); 7297 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, 7298 DAG.getIntPtrConstant(NumElts)); 7299 SDValue BasePtr = S->getBasePtr(); 7300 SDValue NewST1 = 7301 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(), 7302 S->isVolatile(), S->isNonTemporal(), S->getAlignment()); 7303 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr, 7304 DAG.getConstant(8, MVT::i64)); 7305 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr, 7306 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(), 7307 S->getAlignment()); 7308} 7309 7310/// Target-specific DAG combine function for post-increment LD1 (lane) and 7311/// post-increment LD1R. 7312static SDValue performPostLD1Combine(SDNode *N, 7313 TargetLowering::DAGCombinerInfo &DCI, 7314 bool IsLaneOp) { 7315 if (DCI.isBeforeLegalizeOps()) 7316 return SDValue(); 7317 7318 SelectionDAG &DAG = DCI.DAG; 7319 EVT VT = N->getValueType(0); 7320 7321 unsigned LoadIdx = IsLaneOp ? 1 : 0; 7322 SDNode *LD = N->getOperand(LoadIdx).getNode(); 7323 // If it is not LOAD, can not do such combine. 7324 if (LD->getOpcode() != ISD::LOAD) 7325 return SDValue(); 7326 7327 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD); 7328 EVT MemVT = LoadSDN->getMemoryVT(); 7329 // Check if memory operand is the same type as the vector element. 7330 if (MemVT != VT.getVectorElementType()) 7331 return SDValue(); 7332 7333 // Check if there are other uses. If so, do not combine as it will introduce 7334 // an extra load. 7335 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE; 7336 ++UI) { 7337 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result. 7338 continue; 7339 if (*UI != N) 7340 return SDValue(); 7341 } 7342 7343 SDValue Addr = LD->getOperand(1); 7344 SDValue Vector = N->getOperand(0); 7345 // Search for a use of the address operand that is an increment. 7346 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE = 7347 Addr.getNode()->use_end(); UI != UE; ++UI) { 7348 SDNode *User = *UI; 7349 if (User->getOpcode() != ISD::ADD 7350 || UI.getUse().getResNo() != Addr.getResNo()) 7351 continue; 7352 7353 // Check that the add is independent of the load. Otherwise, folding it 7354 // would create a cycle. 7355 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User)) 7356 continue; 7357 // Also check that add is not used in the vector operand. This would also 7358 // create a cycle. 7359 if (User->isPredecessorOf(Vector.getNode())) 7360 continue; 7361 7362 // If the increment is a constant, it must match the memory ref size. 7363 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0); 7364 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) { 7365 uint32_t IncVal = CInc->getZExtValue(); 7366 unsigned NumBytes = VT.getScalarSizeInBits() / 8; 7367 if (IncVal != NumBytes) 7368 continue; 7369 Inc = DAG.getRegister(AArch64::XZR, MVT::i64); 7370 } 7371 7372 SmallVector<SDValue, 8> Ops; 7373 Ops.push_back(LD->getOperand(0)); // Chain 7374 if (IsLaneOp) { 7375 Ops.push_back(Vector); // The vector to be inserted 7376 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector 7377 } 7378 Ops.push_back(Addr); 7379 Ops.push_back(Inc); 7380 7381 EVT Tys[3] = { VT, MVT::i64, MVT::Other }; 7382 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, 3)); 7383 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost; 7384 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops, 7385 MemVT, 7386 LoadSDN->getMemOperand()); 7387 7388 // Update the uses. 7389 std::vector<SDValue> NewResults; 7390 NewResults.push_back(SDValue(LD, 0)); // The result of load 7391 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain 7392 DCI.CombineTo(LD, NewResults); 7393 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result 7394 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register 7395 7396 break; 7397 } 7398 return SDValue(); 7399} 7400 7401/// Target-specific DAG combine function for NEON load/store intrinsics 7402/// to merge base address updates. 7403static SDValue performNEONPostLDSTCombine(SDNode *N, 7404 TargetLowering::DAGCombinerInfo &DCI, 7405 SelectionDAG &DAG) { 7406 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 7407 return SDValue(); 7408 7409 unsigned AddrOpIdx = N->getNumOperands() - 1; 7410 SDValue Addr = N->getOperand(AddrOpIdx); 7411 7412 // Search for a use of the address operand that is an increment. 7413 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 7414 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 7415 SDNode *User = *UI; 7416 if (User->getOpcode() != ISD::ADD || 7417 UI.getUse().getResNo() != Addr.getResNo()) 7418 continue; 7419 7420 // Check that the add is independent of the load/store. Otherwise, folding 7421 // it would create a cycle. 7422 if (User->isPredecessorOf(N) || N->isPredecessorOf(User)) 7423 continue; 7424 7425 // Find the new opcode for the updating load/store. 7426 bool IsStore = false; 7427 bool IsLaneOp = false; 7428 bool IsDupOp = false; 7429 unsigned NewOpc = 0; 7430 unsigned NumVecs = 0; 7431 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 7432 switch (IntNo) { 7433 default: llvm_unreachable("unexpected intrinsic for Neon base update"); 7434 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post; 7435 NumVecs = 2; break; 7436 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post; 7437 NumVecs = 3; break; 7438 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post; 7439 NumVecs = 4; break; 7440 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post; 7441 NumVecs = 2; IsStore = true; break; 7442 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post; 7443 NumVecs = 3; IsStore = true; break; 7444 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post; 7445 NumVecs = 4; IsStore = true; break; 7446 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post; 7447 NumVecs = 2; break; 7448 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post; 7449 NumVecs = 3; break; 7450 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post; 7451 NumVecs = 4; break; 7452 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post; 7453 NumVecs = 2; IsStore = true; break; 7454 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post; 7455 NumVecs = 3; IsStore = true; break; 7456 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post; 7457 NumVecs = 4; IsStore = true; break; 7458 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost; 7459 NumVecs = 2; IsDupOp = true; break; 7460 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost; 7461 NumVecs = 3; IsDupOp = true; break; 7462 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost; 7463 NumVecs = 4; IsDupOp = true; break; 7464 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost; 7465 NumVecs = 2; IsLaneOp = true; break; 7466 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost; 7467 NumVecs = 3; IsLaneOp = true; break; 7468 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost; 7469 NumVecs = 4; IsLaneOp = true; break; 7470 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost; 7471 NumVecs = 2; IsStore = true; IsLaneOp = true; break; 7472 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost; 7473 NumVecs = 3; IsStore = true; IsLaneOp = true; break; 7474 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost; 7475 NumVecs = 4; IsStore = true; IsLaneOp = true; break; 7476 } 7477 7478 EVT VecTy; 7479 if (IsStore) 7480 VecTy = N->getOperand(2).getValueType(); 7481 else 7482 VecTy = N->getValueType(0); 7483 7484 // If the increment is a constant, it must match the memory ref size. 7485 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0); 7486 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) { 7487 uint32_t IncVal = CInc->getZExtValue(); 7488 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8; 7489 if (IsLaneOp || IsDupOp) 7490 NumBytes /= VecTy.getVectorNumElements(); 7491 if (IncVal != NumBytes) 7492 continue; 7493 Inc = DAG.getRegister(AArch64::XZR, MVT::i64); 7494 } 7495 SmallVector<SDValue, 8> Ops; 7496 Ops.push_back(N->getOperand(0)); // Incoming chain 7497 // Load lane and store have vector list as input. 7498 if (IsLaneOp || IsStore) 7499 for (unsigned i = 2; i < AddrOpIdx; ++i) 7500 Ops.push_back(N->getOperand(i)); 7501 Ops.push_back(Addr); // Base register 7502 Ops.push_back(Inc); 7503 7504 // Return Types. 7505 EVT Tys[6]; 7506 unsigned NumResultVecs = (IsStore ? 0 : NumVecs); 7507 unsigned n; 7508 for (n = 0; n < NumResultVecs; ++n) 7509 Tys[n] = VecTy; 7510 Tys[n++] = MVT::i64; // Type of write back register 7511 Tys[n] = MVT::Other; // Type of the chain 7512 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, NumResultVecs + 2)); 7513 7514 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N); 7515 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops, 7516 MemInt->getMemoryVT(), 7517 MemInt->getMemOperand()); 7518 7519 // Update the uses. 7520 std::vector<SDValue> NewResults; 7521 for (unsigned i = 0; i < NumResultVecs; ++i) { 7522 NewResults.push_back(SDValue(UpdN.getNode(), i)); 7523 } 7524 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1)); 7525 DCI.CombineTo(N, NewResults); 7526 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); 7527 7528 break; 7529 } 7530 return SDValue(); 7531} 7532 7533// Optimize compare with zero and branch. 7534static SDValue performBRCONDCombine(SDNode *N, 7535 TargetLowering::DAGCombinerInfo &DCI, 7536 SelectionDAG &DAG) { 7537 SDValue Chain = N->getOperand(0); 7538 SDValue Dest = N->getOperand(1); 7539 SDValue CCVal = N->getOperand(2); 7540 SDValue Cmp = N->getOperand(3); 7541 7542 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!"); 7543 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue(); 7544 if (CC != AArch64CC::EQ && CC != AArch64CC::NE) 7545 return SDValue(); 7546 7547 unsigned CmpOpc = Cmp.getOpcode(); 7548 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS) 7549 return SDValue(); 7550 7551 // Only attempt folding if there is only one use of the flag and no use of the 7552 // value. 7553 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1)) 7554 return SDValue(); 7555 7556 SDValue LHS = Cmp.getOperand(0); 7557 SDValue RHS = Cmp.getOperand(1); 7558 7559 assert(LHS.getValueType() == RHS.getValueType() && 7560 "Expected the value type to be the same for both operands!"); 7561 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64) 7562 return SDValue(); 7563 7564 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue()) 7565 std::swap(LHS, RHS); 7566 7567 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue()) 7568 return SDValue(); 7569 7570 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA || 7571 LHS.getOpcode() == ISD::SRL) 7572 return SDValue(); 7573 7574 // Fold the compare into the branch instruction. 7575 SDValue BR; 7576 if (CC == AArch64CC::EQ) 7577 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest); 7578 else 7579 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest); 7580 7581 // Do not add new nodes to DAG combiner worklist. 7582 DCI.CombineTo(N, BR, false); 7583 7584 return SDValue(); 7585} 7586 7587// vselect (v1i1 setcc) -> 7588// vselect (v1iXX setcc) (XX is the size of the compared operand type) 7589// FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as 7590// condition. If it can legalize "VSELECT v1i1" correctly, no need to combine 7591// such VSELECT. 7592static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) { 7593 SDValue N0 = N->getOperand(0); 7594 EVT CCVT = N0.getValueType(); 7595 7596 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 || 7597 CCVT.getVectorElementType() != MVT::i1) 7598 return SDValue(); 7599 7600 EVT ResVT = N->getValueType(0); 7601 EVT CmpVT = N0.getOperand(0).getValueType(); 7602 // Only combine when the result type is of the same size as the compared 7603 // operands. 7604 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits()) 7605 return SDValue(); 7606 7607 SDValue IfTrue = N->getOperand(1); 7608 SDValue IfFalse = N->getOperand(2); 7609 SDValue SetCC = 7610 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(), 7611 N0.getOperand(0), N0.getOperand(1), 7612 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 7613 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, 7614 IfTrue, IfFalse); 7615} 7616 7617/// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with 7618/// the compare-mask instructions rather than going via NZCV, even if LHS and 7619/// RHS are really scalar. This replaces any scalar setcc in the above pattern 7620/// with a vector one followed by a DUP shuffle on the result. 7621static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) { 7622 SDValue N0 = N->getOperand(0); 7623 EVT ResVT = N->getValueType(0); 7624 7625 if (!N->getOperand(1).getValueType().isVector()) 7626 return SDValue(); 7627 7628 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1) 7629 return SDValue(); 7630 7631 SDLoc DL(N0); 7632 7633 EVT SrcVT = N0.getOperand(0).getValueType(); 7634 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, 7635 ResVT.getSizeInBits() / SrcVT.getSizeInBits()); 7636 EVT CCVT = SrcVT.changeVectorElementTypeToInteger(); 7637 7638 // First perform a vector comparison, where lane 0 is the one we're interested 7639 // in. 7640 SDValue LHS = 7641 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0)); 7642 SDValue RHS = 7643 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1)); 7644 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2)); 7645 7646 // Now duplicate the comparison mask we want across all other lanes. 7647 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0); 7648 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data()); 7649 Mask = DAG.getNode(ISD::BITCAST, DL, ResVT.changeVectorElementTypeToInteger(), 7650 Mask); 7651 7652 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2)); 7653} 7654 7655SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N, 7656 DAGCombinerInfo &DCI) const { 7657 SelectionDAG &DAG = DCI.DAG; 7658 switch (N->getOpcode()) { 7659 default: 7660 break; 7661 case ISD::ADD: 7662 case ISD::SUB: 7663 return performAddSubLongCombine(N, DCI, DAG); 7664 case ISD::XOR: 7665 return performXorCombine(N, DAG, DCI, Subtarget); 7666 case ISD::MUL: 7667 return performMulCombine(N, DAG, DCI, Subtarget); 7668 case ISD::SINT_TO_FP: 7669 case ISD::UINT_TO_FP: 7670 return performIntToFpCombine(N, DAG); 7671 case ISD::OR: 7672 return performORCombine(N, DCI, Subtarget); 7673 case ISD::INTRINSIC_WO_CHAIN: 7674 return performIntrinsicCombine(N, DCI, Subtarget); 7675 case ISD::ANY_EXTEND: 7676 case ISD::ZERO_EXTEND: 7677 case ISD::SIGN_EXTEND: 7678 return performExtendCombine(N, DCI, DAG); 7679 case ISD::BITCAST: 7680 return performBitcastCombine(N, DCI, DAG); 7681 case ISD::CONCAT_VECTORS: 7682 return performConcatVectorsCombine(N, DCI, DAG); 7683 case ISD::SELECT: 7684 return performSelectCombine(N, DAG); 7685 case ISD::VSELECT: 7686 return performVSelectCombine(N, DCI.DAG); 7687 case ISD::STORE: 7688 return performSTORECombine(N, DCI, DAG, Subtarget); 7689 case AArch64ISD::BRCOND: 7690 return performBRCONDCombine(N, DCI, DAG); 7691 case AArch64ISD::DUP: 7692 return performPostLD1Combine(N, DCI, false); 7693 case ISD::INSERT_VECTOR_ELT: 7694 return performPostLD1Combine(N, DCI, true); 7695 case ISD::INTRINSIC_VOID: 7696 case ISD::INTRINSIC_W_CHAIN: 7697 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 7698 case Intrinsic::aarch64_neon_ld2: 7699 case Intrinsic::aarch64_neon_ld3: 7700 case Intrinsic::aarch64_neon_ld4: 7701 case Intrinsic::aarch64_neon_ld1x2: 7702 case Intrinsic::aarch64_neon_ld1x3: 7703 case Intrinsic::aarch64_neon_ld1x4: 7704 case Intrinsic::aarch64_neon_ld2lane: 7705 case Intrinsic::aarch64_neon_ld3lane: 7706 case Intrinsic::aarch64_neon_ld4lane: 7707 case Intrinsic::aarch64_neon_ld2r: 7708 case Intrinsic::aarch64_neon_ld3r: 7709 case Intrinsic::aarch64_neon_ld4r: 7710 case Intrinsic::aarch64_neon_st2: 7711 case Intrinsic::aarch64_neon_st3: 7712 case Intrinsic::aarch64_neon_st4: 7713 case Intrinsic::aarch64_neon_st1x2: 7714 case Intrinsic::aarch64_neon_st1x3: 7715 case Intrinsic::aarch64_neon_st1x4: 7716 case Intrinsic::aarch64_neon_st2lane: 7717 case Intrinsic::aarch64_neon_st3lane: 7718 case Intrinsic::aarch64_neon_st4lane: 7719 return performNEONPostLDSTCombine(N, DCI, DAG); 7720 default: 7721 break; 7722 } 7723 } 7724 return SDValue(); 7725} 7726 7727// Check if the return value is used as only a return value, as otherwise 7728// we can't perform a tail-call. In particular, we need to check for 7729// target ISD nodes that are returns and any other "odd" constructs 7730// that the generic analysis code won't necessarily catch. 7731bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N, 7732 SDValue &Chain) const { 7733 if (N->getNumValues() != 1) 7734 return false; 7735 if (!N->hasNUsesOfValue(1, 0)) 7736 return false; 7737 7738 SDValue TCChain = Chain; 7739 SDNode *Copy = *N->use_begin(); 7740 if (Copy->getOpcode() == ISD::CopyToReg) { 7741 // If the copy has a glue operand, we conservatively assume it isn't safe to 7742 // perform a tail call. 7743 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() == 7744 MVT::Glue) 7745 return false; 7746 TCChain = Copy->getOperand(0); 7747 } else if (Copy->getOpcode() != ISD::FP_EXTEND) 7748 return false; 7749 7750 bool HasRet = false; 7751 for (SDNode *Node : Copy->uses()) { 7752 if (Node->getOpcode() != AArch64ISD::RET_FLAG) 7753 return false; 7754 HasRet = true; 7755 } 7756 7757 if (!HasRet) 7758 return false; 7759 7760 Chain = TCChain; 7761 return true; 7762} 7763 7764// Return whether the an instruction can potentially be optimized to a tail 7765// call. This will cause the optimizers to attempt to move, or duplicate, 7766// return instructions to help enable tail call optimizations for this 7767// instruction. 7768bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 7769 if (!CI->isTailCall()) 7770 return false; 7771 7772 return true; 7773} 7774 7775bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base, 7776 SDValue &Offset, 7777 ISD::MemIndexedMode &AM, 7778 bool &IsInc, 7779 SelectionDAG &DAG) const { 7780 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) 7781 return false; 7782 7783 Base = Op->getOperand(0); 7784 // All of the indexed addressing mode instructions take a signed 7785 // 9 bit immediate offset. 7786 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { 7787 int64_t RHSC = (int64_t)RHS->getZExtValue(); 7788 if (RHSC >= 256 || RHSC <= -256) 7789 return false; 7790 IsInc = (Op->getOpcode() == ISD::ADD); 7791 Offset = Op->getOperand(1); 7792 return true; 7793 } 7794 return false; 7795} 7796 7797bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 7798 SDValue &Offset, 7799 ISD::MemIndexedMode &AM, 7800 SelectionDAG &DAG) const { 7801 EVT VT; 7802 SDValue Ptr; 7803 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7804 VT = LD->getMemoryVT(); 7805 Ptr = LD->getBasePtr(); 7806 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7807 VT = ST->getMemoryVT(); 7808 Ptr = ST->getBasePtr(); 7809 } else 7810 return false; 7811 7812 bool IsInc; 7813 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG)) 7814 return false; 7815 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC; 7816 return true; 7817} 7818 7819bool AArch64TargetLowering::getPostIndexedAddressParts( 7820 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, 7821 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const { 7822 EVT VT; 7823 SDValue Ptr; 7824 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7825 VT = LD->getMemoryVT(); 7826 Ptr = LD->getBasePtr(); 7827 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7828 VT = ST->getMemoryVT(); 7829 Ptr = ST->getBasePtr(); 7830 } else 7831 return false; 7832 7833 bool IsInc; 7834 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG)) 7835 return false; 7836 // Post-indexing updates the base, so it's not a valid transform 7837 // if that's not the same as the load's pointer. 7838 if (Ptr != Base) 7839 return false; 7840 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC; 7841 return true; 7842} 7843 7844void AArch64TargetLowering::ReplaceNodeResults( 7845 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const { 7846 switch (N->getOpcode()) { 7847 default: 7848 llvm_unreachable("Don't know how to custom expand this"); 7849 case ISD::FP_TO_UINT: 7850 case ISD::FP_TO_SINT: 7851 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion"); 7852 // Let normal code take care of it by not adding anything to Results. 7853 return; 7854 } 7855} 7856 7857bool AArch64TargetLowering::shouldExpandAtomicInIR(Instruction *Inst) const { 7858 // Loads and stores less than 128-bits are already atomic; ones above that 7859 // are doomed anyway, so defer to the default libcall and blame the OS when 7860 // things go wrong: 7861 if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) 7862 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() == 128; 7863 else if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) 7864 return LI->getType()->getPrimitiveSizeInBits() == 128; 7865 7866 // For the real atomic operations, we have ldxr/stxr up to 128 bits. 7867 return Inst->getType()->getPrimitiveSizeInBits() <= 128; 7868} 7869 7870Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr, 7871 AtomicOrdering Ord) const { 7872 Module *M = Builder.GetInsertBlock()->getParent()->getParent(); 7873 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType(); 7874 bool IsAcquire = 7875 Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent; 7876 7877 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd 7878 // intrinsic must return {i64, i64} and we have to recombine them into a 7879 // single i128 here. 7880 if (ValTy->getPrimitiveSizeInBits() == 128) { 7881 Intrinsic::ID Int = 7882 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp; 7883 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int); 7884 7885 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext())); 7886 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi"); 7887 7888 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo"); 7889 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi"); 7890 Lo = Builder.CreateZExt(Lo, ValTy, "lo64"); 7891 Hi = Builder.CreateZExt(Hi, ValTy, "hi64"); 7892 return Builder.CreateOr( 7893 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64"); 7894 } 7895 7896 Type *Tys[] = { Addr->getType() }; 7897 Intrinsic::ID Int = 7898 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr; 7899 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys); 7900 7901 return Builder.CreateTruncOrBitCast( 7902 Builder.CreateCall(Ldxr, Addr), 7903 cast<PointerType>(Addr->getType())->getElementType()); 7904} 7905 7906Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder, 7907 Value *Val, Value *Addr, 7908 AtomicOrdering Ord) const { 7909 Module *M = Builder.GetInsertBlock()->getParent()->getParent(); 7910 bool IsRelease = 7911 Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent; 7912 7913 // Since the intrinsics must have legal type, the i128 intrinsics take two 7914 // parameters: "i64, i64". We must marshal Val into the appropriate form 7915 // before the call. 7916 if (Val->getType()->getPrimitiveSizeInBits() == 128) { 7917 Intrinsic::ID Int = 7918 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp; 7919 Function *Stxr = Intrinsic::getDeclaration(M, Int); 7920 Type *Int64Ty = Type::getInt64Ty(M->getContext()); 7921 7922 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo"); 7923 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi"); 7924 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext())); 7925 return Builder.CreateCall3(Stxr, Lo, Hi, Addr); 7926 } 7927 7928 Intrinsic::ID Int = 7929 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr; 7930 Type *Tys[] = { Addr->getType() }; 7931 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys); 7932 7933 return Builder.CreateCall2( 7934 Stxr, Builder.CreateZExtOrBitCast( 7935 Val, Stxr->getFunctionType()->getParamType(0)), 7936 Addr); 7937} 7938