AArch64InstrInfo.h revision 22c310d78ce9630af15b0de94c18a409705b7496 
1//===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the AArch64 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_AArch64INSTRINFO_H
15#define LLVM_TARGET_AArch64INSTRINFO_H
16
17#include "AArch64.h"
18#include "AArch64RegisterInfo.h"
19#include "llvm/Target/TargetInstrInfo.h"
20
21#define GET_INSTRINFO_HEADER
22#include "AArch64GenInstrInfo.inc"
23
24namespace llvm {
25
26class AArch64Subtarget;
27class AArch64TargetMachine;
28
29class AArch64InstrInfo : public AArch64GenInstrInfo {
30  // Reserve bits in the MachineMemOperand target hint flags, starting at 1.
31  // They will be shifted into MOTargetHintStart when accessed.
32  enum TargetMemOperandFlags {
33    MOSuppressPair = 1
34  };
35
36  const AArch64RegisterInfo RI;
37  const AArch64Subtarget &Subtarget;
38
39public:
40  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
41
42  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
43  /// such, whenever a client has an instance of instruction info, it should
44  /// always be able to get register info as well (through this method).
45  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
46
47  unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
48
49  bool isAsCheapAsAMove(const MachineInstr *MI) const override;
50
51  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
52                             unsigned &DstReg, unsigned &SubIdx) const override;
53
54  unsigned isLoadFromStackSlot(const MachineInstr *MI,
55                               int &FrameIndex) const override;
56  unsigned isStoreToStackSlot(const MachineInstr *MI,
57                              int &FrameIndex) const override;
58
59  /// Returns true if there is a shiftable register and that the shift value
60  /// is non-zero.
61  bool hasShiftedReg(const MachineInstr *MI) const;
62
63  /// Returns true if there is an extendable register and that the extending
64  /// value is non-zero.
65  bool hasExtendedReg(const MachineInstr *MI) const;
66
67  /// \brief Does this instruction set its full destination register to zero?
68  bool isGPRZero(const MachineInstr *MI) const;
69
70  /// \brief Does this instruction rename a GPR without modifying bits?
71  bool isGPRCopy(const MachineInstr *MI) const;
72
73  /// \brief Does this instruction rename an FPR without modifying bits?
74  bool isFPRCopy(const MachineInstr *MI) const;
75
76  /// Return true if this is load/store scales or extends its register offset.
77  /// This refers to scaling a dynamic index as opposed to scaled immediates.
78  /// MI should be a memory op that allows scaled addressing.
79  bool isScaledAddr(const MachineInstr *MI) const;
80
81  /// Return true if pairing the given load or store is hinted to be
82  /// unprofitable.
83  bool isLdStPairSuppressed(const MachineInstr *MI) const;
84
85  /// Hint that pairing the given load or store is unprofitable.
86  void suppressLdStPair(MachineInstr *MI) const;
87
88  bool getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
89                            unsigned &Offset,
90                            const TargetRegisterInfo *TRI) const override;
91
92  bool enableClusterLoads() const override { return true; }
93
94  bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt,
95                          unsigned NumLoads) const override;
96
97  bool shouldScheduleAdjacent(MachineInstr *First,
98                              MachineInstr *Second) const override;
99
100  MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
101                                         uint64_t Offset, const MDNode *MDPtr,
102                                         DebugLoc DL) const;
103  void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
104                        DebugLoc DL, unsigned DestReg, unsigned SrcReg,
105                        bool KillSrc, unsigned Opcode,
106                        llvm::ArrayRef<unsigned> Indices) const;
107  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
108                   DebugLoc DL, unsigned DestReg, unsigned SrcReg,
109                   bool KillSrc) const override;
110
111  void storeRegToStackSlot(MachineBasicBlock &MBB,
112                           MachineBasicBlock::iterator MBBI, unsigned SrcReg,
113                           bool isKill, int FrameIndex,
114                           const TargetRegisterClass *RC,
115                           const TargetRegisterInfo *TRI) const override;
116
117  void loadRegFromStackSlot(MachineBasicBlock &MBB,
118                            MachineBasicBlock::iterator MBBI, unsigned DestReg,
119                            int FrameIndex, const TargetRegisterClass *RC,
120                            const TargetRegisterInfo *TRI) const override;
121
122  MachineInstr *
123  foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
124                        const SmallVectorImpl<unsigned> &Ops,
125                        int FrameIndex) const override;
126
127  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
128                     MachineBasicBlock *&FBB,
129                     SmallVectorImpl<MachineOperand> &Cond,
130                     bool AllowModify = false) const override;
131  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
132  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
133                        MachineBasicBlock *FBB,
134                        const SmallVectorImpl<MachineOperand> &Cond,
135                        DebugLoc DL) const override;
136  bool
137  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
138  bool canInsertSelect(const MachineBasicBlock &,
139                       const SmallVectorImpl<MachineOperand> &Cond, unsigned,
140                       unsigned, int &, int &, int &) const override;
141  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
142                    DebugLoc DL, unsigned DstReg,
143                    const SmallVectorImpl<MachineOperand> &Cond,
144                    unsigned TrueReg, unsigned FalseReg) const override;
145  void getNoopForMachoTarget(MCInst &NopInst) const override;
146
147  /// analyzeCompare - For a comparison instruction, return the source registers
148  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
149  /// Return true if the comparison instruction can be analyzed.
150  bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
151                      unsigned &SrcReg2, int &CmpMask,
152                      int &CmpValue) const override;
153  /// optimizeCompareInstr - Convert the instruction supplying the argument to
154  /// the comparison into one that sets the zero bit in the flags register.
155  bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
156                            unsigned SrcReg2, int CmpMask, int CmpValue,
157                            const MachineRegisterInfo *MRI) const override;
158
159private:
160  void instantiateCondBranch(MachineBasicBlock &MBB, DebugLoc DL,
161                             MachineBasicBlock *TBB,
162                             const SmallVectorImpl<MachineOperand> &Cond) const;
163};
164
165/// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
166/// plus Offset.  This is intended to be used from within the prolog/epilog
167/// insertion (PEI) pass, where a virtual scratch register may be allocated
168/// if necessary, to be replaced by the scavenger at the end of PEI.
169void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
170                     DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
171                     const TargetInstrInfo *TII,
172                     MachineInstr::MIFlag = MachineInstr::NoFlags,
173                     bool SetNZCV = false);
174
175/// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
176/// FP. Return false if the offset could not be handled directly in MI, and
177/// return the left-over portion by reference.
178bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
179                            unsigned FrameReg, int &Offset,
180                            const AArch64InstrInfo *TII);
181
182/// \brief Use to report the frame offset status in isAArch64FrameOffsetLegal.
183enum AArch64FrameOffsetStatus {
184  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
185  AArch64FrameOffsetIsLegal = 0x1,      ///< Offset is legal.
186  AArch64FrameOffsetCanUpdate = 0x2     ///< Offset can apply, at least partly.
187};
188
189/// \brief Check if the @p Offset is a valid frame offset for @p MI.
190/// The returned value reports the validity of the frame offset for @p MI.
191/// It uses the values defined by AArch64FrameOffsetStatus for that.
192/// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
193/// use an offset.eq
194/// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
195/// rewriten in @p MI.
196/// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
197/// amount that is off the limit of the legal offset.
198/// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
199/// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
200/// If set, @p EmittableOffset contains the amount that can be set in @p MI
201/// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
202/// is a legal offset.
203int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
204                            bool *OutUseUnscaledOp = nullptr,
205                            unsigned *OutUnscaledOp = nullptr,
206                            int *EmittableOffset = nullptr);
207
208static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
209
210static inline bool isCondBranchOpcode(int Opc) {
211  switch (Opc) {
212  case AArch64::Bcc:
213  case AArch64::CBZW:
214  case AArch64::CBZX:
215  case AArch64::CBNZW:
216  case AArch64::CBNZX:
217  case AArch64::TBZW:
218  case AArch64::TBZX:
219  case AArch64::TBNZW:
220  case AArch64::TBNZX:
221    return true;
222  default:
223    return false;
224  }
225}
226
227static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; }
228
229} // end namespace llvm
230
231#endif
232