AArch64InstrInfo.h revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the AArch64 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_AARCH64INSTRINFO_H
15#define LLVM_TARGET_AARCH64INSTRINFO_H
16
17#include "AArch64RegisterInfo.h"
18#include "llvm/Target/TargetInstrInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#include "AArch64GenInstrInfo.inc"
22
23namespace llvm {
24
25class AArch64Subtarget;
26
27class AArch64InstrInfo : public AArch64GenInstrInfo {
28  const AArch64RegisterInfo RI;
29  const AArch64Subtarget &Subtarget;
30public:
31  explicit AArch64InstrInfo(const AArch64Subtarget &TM);
32
33  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
34  /// such, whenever a client has an instance of instruction info, it should
35  /// always be able to get register info as well (through this method).
36  ///
37  const TargetRegisterInfo &getRegisterInfo() const { return RI; }
38
39  const AArch64Subtarget &getSubTarget() const { return Subtarget; }
40
41  void copyPhysReg(MachineBasicBlock &MBB,
42                   MachineBasicBlock::iterator I, DebugLoc DL,
43                   unsigned DestReg, unsigned SrcReg,
44                   bool KillSrc) const;
45  void CopyPhysRegTuple(MachineBasicBlock &MBB,
46                        MachineBasicBlock::iterator I, DebugLoc DL,
47                        unsigned DestReg, unsigned SrcReg) const;
48
49  void storeRegToStackSlot(MachineBasicBlock &MBB,
50                           MachineBasicBlock::iterator MI,
51                           unsigned SrcReg, bool isKill, int FrameIndex,
52                           const TargetRegisterClass *RC,
53                           const TargetRegisterInfo *TRI) const;
54  void loadRegFromStackSlot(MachineBasicBlock &MBB,
55                            MachineBasicBlock::iterator MBBI,
56                            unsigned DestReg, int FrameIdx,
57                            const TargetRegisterClass *RC,
58                            const TargetRegisterInfo *TRI) const;
59
60  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
61                     MachineBasicBlock *&FBB,
62                     SmallVectorImpl<MachineOperand> &Cond,
63                     bool AllowModify = false) const;
64  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
65                        MachineBasicBlock *FBB,
66                        const SmallVectorImpl<MachineOperand> &Cond,
67                        DebugLoc DL) const;
68  unsigned RemoveBranch(MachineBasicBlock &MBB) const;
69  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
70
71  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
72
73  /// Look through the instructions in this function and work out the largest
74  /// the stack frame can be while maintaining the ability to address local
75  /// slots with no complexities.
76  unsigned estimateRSStackLimit(MachineFunction &MF) const;
77
78  /// getAddressConstraints - For loads and stores (and PRFMs) taking an
79  /// immediate offset, this function determines the constraints required for
80  /// the immediate. It must satisfy:
81  ///    + MinOffset <= imm <= MaxOffset
82  ///    + imm % OffsetScale == 0
83  void getAddressConstraints(const MachineInstr &MI, int &AccessScale,
84                             int &MinOffset, int &MaxOffset) const;
85
86
87  unsigned getInstSizeInBytes(const MachineInstr &MI) const;
88
89  unsigned getInstBundleLength(const MachineInstr &MI) const;
90
91};
92
93bool rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
94                          unsigned FrameReg, int &Offset,
95                          const AArch64InstrInfo &TII);
96
97
98void emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
99                   DebugLoc dl, const TargetInstrInfo &TII,
100                   unsigned DstReg, unsigned SrcReg, unsigned ScratchReg,
101                   int64_t NumBytes,
102                   MachineInstr::MIFlag MIFlags = MachineInstr::NoFlags);
103
104void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
105                  DebugLoc dl, const TargetInstrInfo &TII,
106                  unsigned ScratchReg, int64_t NumBytes,
107                  MachineInstr::MIFlag MIFlags = MachineInstr::NoFlags);
108
109}
110
111#endif
112