1dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines//==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==// 272062f5744557e270a38192554c3126ea5f97434Tim Northover// 372062f5744557e270a38192554c3126ea5f97434Tim Northover// The LLVM Compiler Infrastructure 472062f5744557e270a38192554c3126ea5f97434Tim Northover// 572062f5744557e270a38192554c3126ea5f97434Tim Northover// This file is distributed under the University of Illinois Open Source 672062f5744557e270a38192554c3126ea5f97434Tim Northover// License. See LICENSE.TXT for details. 772062f5744557e270a38192554c3126ea5f97434Tim Northover// 872062f5744557e270a38192554c3126ea5f97434Tim Northover//===----------------------------------------------------------------------===// 972062f5744557e270a38192554c3126ea5f97434Tim Northover// 10dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// This file contains the AArch64 implementation of the MRegisterInfo class. 1172062f5744557e270a38192554c3126ea5f97434Tim Northover// 1272062f5744557e270a38192554c3126ea5f97434Tim Northover//===----------------------------------------------------------------------===// 1372062f5744557e270a38192554c3126ea5f97434Tim Northover 14dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#ifndef LLVM_TARGET_AArch64REGISTERINFO_H 15dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#define LLVM_TARGET_AArch64REGISTERINFO_H 1672062f5744557e270a38192554c3126ea5f97434Tim Northover 1772062f5744557e270a38192554c3126ea5f97434Tim Northover#define GET_REGINFO_HEADER 1872062f5744557e270a38192554c3126ea5f97434Tim Northover#include "AArch64GenRegisterInfo.inc" 1972062f5744557e270a38192554c3126ea5f97434Tim Northover 2072062f5744557e270a38192554c3126ea5f97434Tim Northovernamespace llvm { 2172062f5744557e270a38192554c3126ea5f97434Tim Northover 2272062f5744557e270a38192554c3126ea5f97434Tim Northoverclass AArch64InstrInfo; 2372062f5744557e270a38192554c3126ea5f97434Tim Northoverclass AArch64Subtarget; 24dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesclass MachineFunction; 25dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesclass RegScavenger; 26dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesclass TargetRegisterClass; 2772062f5744557e270a38192554c3126ea5f97434Tim Northover 2872062f5744557e270a38192554c3126ea5f97434Tim Northoverstruct AArch64RegisterInfo : public AArch64GenRegisterInfo { 29dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesprivate: 30dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const AArch64InstrInfo *TII; 31dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const AArch64Subtarget *STI; 3272062f5744557e270a38192554c3126ea5f97434Tim Northover 33dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinespublic: 34dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines AArch64RegisterInfo(const AArch64InstrInfo *tii, const AArch64Subtarget *sti); 3572062f5744557e270a38192554c3126ea5f97434Tim Northover 36dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool isReservedReg(const MachineFunction &MF, unsigned Reg) const; 3772062f5744557e270a38192554c3126ea5f97434Tim Northover 38dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines /// Code Generation virtual methods... 39dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const MCPhysReg * 40dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override; 41dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const uint32_t *getCallPreservedMask(CallingConv::ID) const override; 4272062f5744557e270a38192554c3126ea5f97434Tim Northover 43dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned getCSRFirstUseCost() const override { 44dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // The cost will be compared against BlockFrequency where entry has the 45dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // value of 1 << 14. A value of 5 will choose to spill or split really 46dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // cold path instead of using a callee-saved register. 47dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return 5; 48dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 4972062f5744557e270a38192554c3126ea5f97434Tim Northover 50dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Calls involved in thread-local variable lookup save more registers than 51dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // normal calls, so they need a different mask to represent this. 52dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const uint32_t *getTLSCallPreservedMask() const; 53dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 54dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines /// getThisReturnPreservedMask - Returns a call preserved mask specific to the 55dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines /// case that 'returned' is on an i64 first argument if the calling convention 56dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines /// is one that can (partially) model this attribute with a preserved mask 57dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines /// (i.e. it is a calling convention that uses the same register for the first 58dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines /// i64 argument and an i64 return value) 59dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines /// 60dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines /// Should return NULL in the case that the calling convention does not have 61dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines /// this property 62dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const; 63dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 64dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines BitVector getReservedRegs(const MachineFunction &MF) const override; 6572062f5744557e270a38192554c3126ea5f97434Tim Northover const TargetRegisterClass * 66dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines getPointerRegClass(const MachineFunction &MF, 67dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned Kind = 0) const override; 68dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterClass * 69dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines getCrossCopyRegClass(const TargetRegisterClass *RC) const override; 70dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 71dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool requiresRegisterScavenging(const MachineFunction &MF) const override; 72dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool useFPForScavengingIndex(const MachineFunction &MF) const override; 73dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool requiresFrameIndexScavenging(const MachineFunction &MF) const override; 74dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 75dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; 76dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool isFrameOffsetLegal(const MachineInstr *MI, 77dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines int64_t Offset) const override; 78dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, 79dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines int FrameIdx, 80dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines int64_t Offset) const override; 81dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 82dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines int64_t Offset) const override; 83dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 84dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned FIOperandNum, 85dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines RegScavenger *RS = nullptr) const override; 86dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool cannotEliminateFrame(const MachineFunction &MF) const; 8772062f5744557e270a38192554c3126ea5f97434Tim Northover 88dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override; 89dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool hasBasePointer(const MachineFunction &MF) const; 90dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned getBaseRegister() const; 9172062f5744557e270a38192554c3126ea5f97434Tim Northover 92dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Debug information queries. 93dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned getFrameRegister(const MachineFunction &MF) const override; 9472062f5744557e270a38192554c3126ea5f97434Tim Northover 95dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned getRegPressureLimit(const TargetRegisterClass *RC, 96dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineFunction &MF) const override; 9772062f5744557e270a38192554c3126ea5f97434Tim Northover}; 9872062f5744557e270a38192554c3126ea5f97434Tim Northover 9972062f5744557e270a38192554c3126ea5f97434Tim Northover} // end namespace llvm 10072062f5744557e270a38192554c3126ea5f97434Tim Northover 101dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#endif // LLVM_TARGET_AArch64REGISTERINFO_H 102