AArch64RegisterInfo.h revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the AArch64 implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_AArch64REGISTERINFO_H
15#define LLVM_TARGET_AArch64REGISTERINFO_H
16
17#define GET_REGINFO_HEADER
18#include "AArch64GenRegisterInfo.inc"
19
20namespace llvm {
21
22class AArch64InstrInfo;
23class AArch64Subtarget;
24class MachineFunction;
25class RegScavenger;
26class TargetRegisterClass;
27
28struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
29private:
30  const AArch64InstrInfo *TII;
31  const AArch64Subtarget *STI;
32
33public:
34  AArch64RegisterInfo(const AArch64InstrInfo *tii, const AArch64Subtarget *sti);
35
36  bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
37
38  /// Code Generation virtual methods...
39  const MCPhysReg *
40  getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
41  const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
42
43  unsigned getCSRFirstUseCost() const override {
44    // The cost will be compared against BlockFrequency where entry has the
45    // value of 1 << 14. A value of 5 will choose to spill or split really
46    // cold path instead of using a callee-saved register.
47    return 5;
48  }
49
50  // Calls involved in thread-local variable lookup save more registers than
51  // normal calls, so they need a different mask to represent this.
52  const uint32_t *getTLSCallPreservedMask() const;
53
54  /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
55  /// case that 'returned' is on an i64 first argument if the calling convention
56  /// is one that can (partially) model this attribute with a preserved mask
57  /// (i.e. it is a calling convention that uses the same register for the first
58  /// i64 argument and an i64 return value)
59  ///
60  /// Should return NULL in the case that the calling convention does not have
61  /// this property
62  const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const;
63
64  BitVector getReservedRegs(const MachineFunction &MF) const override;
65  const TargetRegisterClass *
66  getPointerRegClass(const MachineFunction &MF,
67                     unsigned Kind = 0) const override;
68  const TargetRegisterClass *
69  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
70
71  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
72  bool useFPForScavengingIndex(const MachineFunction &MF) const override;
73  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
74
75  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
76  bool isFrameOffsetLegal(const MachineInstr *MI,
77                          int64_t Offset) const override;
78  void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
79                                    int FrameIdx,
80                                    int64_t Offset) const override;
81  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
82                         int64_t Offset) const override;
83  void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
84                           unsigned FIOperandNum,
85                           RegScavenger *RS = nullptr) const override;
86  bool cannotEliminateFrame(const MachineFunction &MF) const;
87
88  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
89  bool hasBasePointer(const MachineFunction &MF) const;
90  unsigned getBaseRegister() const;
91
92  // Debug information queries.
93  unsigned getFrameRegister(const MachineFunction &MF) const override;
94
95  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
96                               MachineFunction &MF) const override;
97};
98
99} // end namespace llvm
100
101#endif // LLVM_TARGET_AArch64REGISTERINFO_H
102