AArch64SchedA57.td revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb 
1//=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for ARM Cortex-A57 to support
11// instruction scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14
15def CortexA57Model : SchedMachineModel {
16  let IssueWidth        =   8; // 3-way decode and 8-way issue
17  let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
18  let LoadLatency       =   4; // Optimistic load latency
19  let MispredictPenalty =  14; // Fetch + Decode/Rename/Dispatch + Branch
20}
21
22//===----------------------------------------------------------------------===//
23// Define each kind of processor resource and number available on Cortex-A57.
24// Cortex A-57 has 8 pipelines that each has its own 8-entry queue where
25// micro-ops wait for their operands and then issue out-of-order.
26
27def A57UnitB : ProcResource<1> { let BufferSize = 8; }  // Type B micro-ops
28def A57UnitI : ProcResource<2> { let BufferSize = 8; }  // Type I micro-ops
29def A57UnitM : ProcResource<1> { let BufferSize = 8; }  // Type M micro-ops
30def A57UnitL : ProcResource<1> { let BufferSize = 8; }  // Type L micro-ops
31def A57UnitS : ProcResource<1> { let BufferSize = 8; }  // Type S micro-ops
32def A57UnitX : ProcResource<1> { let BufferSize = 8; }  // Type X micro-ops
33def A57UnitW : ProcResource<1> { let BufferSize = 8; }  // Type W micro-ops
34let SchedModel = CortexA57Model in {
35  def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>;    // Type V micro-ops
36}
37
38
39let SchedModel = CortexA57Model in {
40
41//===----------------------------------------------------------------------===//
42// Define customized scheduler read/write types specific to the Cortex-A57.
43
44include "AArch64SchedA57WriteRes.td"
45
46//===----------------------------------------------------------------------===//
47// Map the target-defined scheduler read/write resources and latency for
48// Cortex-A57. The Cortex-A57 types are directly associated with resources, so
49// defining the aliases precludes the need for mapping them using WriteRes. The
50// aliases are sufficient for creating a coarse, working model. As the model
51// evolves, InstRWs will be used to override these SchedAliases.
52
53def : SchedAlias<WriteImm,   A57Write_1cyc_1I>;
54def : SchedAlias<WriteI,     A57Write_1cyc_1I>;
55def : SchedAlias<WriteISReg, A57Write_2cyc_1M>;
56def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>;
57def : SchedAlias<WriteExtr,  A57Write_1cyc_1I>;
58def : SchedAlias<WriteIS,    A57Write_1cyc_1I>;
59def : SchedAlias<WriteID32,  A57Write_19cyc_1M>;
60def : SchedAlias<WriteID64,  A57Write_35cyc_1M>;
61def : SchedAlias<WriteIM32,  A57Write_3cyc_1M>;
62def : SchedAlias<WriteIM64,  A57Write_5cyc_1M>;
63def : SchedAlias<WriteBr,    A57Write_1cyc_1B>;
64def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>;
65def : SchedAlias<WriteLD,    A57Write_4cyc_1L>;
66def : SchedAlias<WriteST,    A57Write_1cyc_1S>;
67def : SchedAlias<WriteSTP,   A57Write_1cyc_1S>;
68def : SchedAlias<WriteAdr,   A57Write_1cyc_1I>;
69def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>;
70def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>;
71def : SchedAlias<WriteF,     A57Write_3cyc_1V>;
72def : SchedAlias<WriteFCmp,  A57Write_3cyc_1V>;
73def : SchedAlias<WriteFCvt,  A57Write_5cyc_1V>;
74def : SchedAlias<WriteFCopy, A57Write_3cyc_1V>;
75def : SchedAlias<WriteFImm,  A57Write_3cyc_1V>;
76def : SchedAlias<WriteFMul,  A57Write_5cyc_1V>;
77def : SchedAlias<WriteFDiv,  A57Write_18cyc_1X>;
78def : SchedAlias<WriteV,     A57Write_3cyc_1V>;
79def : SchedAlias<WriteVLD,   A57Write_5cyc_1L>;
80def : SchedAlias<WriteVST,   A57Write_1cyc_1S>;
81
82def : WriteRes<WriteSys,     []> { let Latency = 1; }
83def : WriteRes<WriteBarrier, []> { let Latency = 1; }
84def : WriteRes<WriteHint,    []> { let Latency = 1; }
85
86def : WriteRes<WriteLDHi,    []> { let Latency = 4; }
87
88// Forwarding logic is not [yet] explicitly modeled beyond what is captured
89// in the latencies of the A57 Generic SchedWriteRes's.
90def : ReadAdvance<ReadI,       0>;
91def : ReadAdvance<ReadISReg,   0>;
92def : ReadAdvance<ReadIEReg,   0>;
93def : ReadAdvance<ReadIM,      0>;
94def : ReadAdvance<ReadIMA,     0>;
95def : ReadAdvance<ReadID,      0>;
96def : ReadAdvance<ReadExtrHi,  0>;
97def : ReadAdvance<ReadAdrBase, 0>;
98def : ReadAdvance<ReadVLD,     0>;
99
100
101//===----------------------------------------------------------------------===//
102// Specialize the coarse model by associating instruction groups with the
103// subtarget-defined types. As the modeled is refined, this will override most
104// of the above ShchedAlias mappings.
105
106// Miscellaneous
107// -----------------------------------------------------------------------------
108
109def : InstRW<[WriteI], (instrs COPY)>;
110
111
112// Branch Instructions
113// -----------------------------------------------------------------------------
114
115def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
116def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
117
118
119// Divide and Multiply Instructions
120// -----------------------------------------------------------------------------
121
122// Multiply high
123def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>;
124
125
126// Miscellaneous Data-Processing Instructions
127// -----------------------------------------------------------------------------
128
129def : InstRW<[A57Write_1cyc_1I],    (instrs EXTRWrri)>;
130def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>;
131def : InstRW<[A57Write_2cyc_1M],    (instregex "BFM")>;
132
133
134// Cryptography Extensions
135// -----------------------------------------------------------------------------
136
137def : InstRW<[A57Write_3cyc_1W], (instregex "CRC32")>;
138
139
140// Vector Load
141// -----------------------------------------------------------------------------
142
143def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1i(8|16|32)$")>;
144def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>;
145def : InstRW<[A57Write_5cyc_1L],            (instregex "LD1i(64)$")>;
146def : InstRW<[A57Write_5cyc_1L, WriteAdr],  (instregex "LD1i(64)_POST$")>;
147
148def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1Rv(8b|4h|2s)$")>;
149def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>;
150def : InstRW<[A57Write_5cyc_1L],            (instregex "LD1Rv(1d)$")>;
151def : InstRW<[A57Write_5cyc_1L, WriteAdr],  (instregex "LD1Rv(1d)_POST$")>;
152def : InstRW<[A57Write_8cyc_1L_1V],           (instregex "LD1Rv(16b|8h|4s|2d)$")>;
153def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
154
155def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Onev(8b|4h|2s|1d)$")>;
156def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
157def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Onev(16b|8h|4s|2d)$")>;
158def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
159def : InstRW<[A57Write_5cyc_1L],              (instregex "LD1Twov(8b|4h|2s|1d)$")>;
160def : InstRW<[A57Write_5cyc_1L, WriteAdr],    (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
161def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Twov(16b|8h|4s|2d)$")>;
162def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
163def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Threev(8b|4h|2s|1d)$")>;
164def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
165def : InstRW<[A57Write_7cyc_3L],            (instregex "LD1Threev(16b|8h|4s|2d)$")>;
166def : InstRW<[A57Write_7cyc_3L, WriteAdr],  (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
167def : InstRW<[A57Write_6cyc_2L],             (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
168def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
169def : InstRW<[A57Write_8cyc_4L],           (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
170def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
171
172def : InstRW<[A57Write_8cyc_1L_2V],           (instregex "LD2i(8|16)$")>;
173def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>;
174def : InstRW<[A57Write_6cyc_2L],            (instregex "LD2i(32)$")>;
175def : InstRW<[A57Write_6cyc_2L, WriteAdr],  (instregex "LD2i(32)_POST$")>;
176def : InstRW<[A57Write_8cyc_1L_1V],            (instregex "LD2i(64)$")>;
177def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],  (instregex "LD2i(64)_POST$")>;
178
179def : InstRW<[A57Write_8cyc_1L_1V],            (instregex "LD2Rv(8b|4h|2s)$")>;
180def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],  (instregex "LD2Rv(8b|4h|2s)_POST$")>;
181def : InstRW<[A57Write_5cyc_1L],             (instregex "LD2Rv(1d)$")>;
182def : InstRW<[A57Write_5cyc_1L, WriteAdr],   (instregex "LD2Rv(1d)_POST$")>;
183def : InstRW<[A57Write_8cyc_1L_2V],           (instregex "LD2Rv(16b|8h|4s|2d)$")>;
184def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
185
186def : InstRW<[A57Write_8cyc_1L_1V],             (instregex "LD2Twov(8b|4h|2s)$")>;
187def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr],   (instregex "LD2Twov(8b|4h|2s)_POST$")>;
188def : InstRW<[A57Write_9cyc_2L_2V],           (instregex "LD2Twov(16b|8h|4s)$")>;
189def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>;
190def : InstRW<[A57Write_6cyc_2L],             (instregex "LD2Twov(2d)$")>;
191def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD2Twov(2d)_POST$")>;
192
193def : InstRW<[A57Write_9cyc_1L_3V],           (instregex "LD3i(8|16)$")>;
194def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>;
195def : InstRW<[A57Write_8cyc_1L_2V],            (instregex "LD3i(32)$")>;
196def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],  (instregex "LD3i(32)_POST$")>;
197def : InstRW<[A57Write_6cyc_2L],             (instregex "LD3i(64)$")>;
198def : InstRW<[A57Write_6cyc_2L, WriteAdr],   (instregex "LD3i(64)_POST$")>;
199
200def : InstRW<[A57Write_8cyc_1L_2V],             (instregex "LD3Rv(8b|4h|2s)$")>;
201def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],   (instregex "LD3Rv(8b|4h|2s)_POST$")>;
202def : InstRW<[A57Write_6cyc_2L],              (instregex "LD3Rv(1d)$")>;
203def : InstRW<[A57Write_6cyc_2L, WriteAdr],    (instregex "LD3Rv(1d)_POST$")>;
204def : InstRW<[A57Write_9cyc_1L_3V],            (instregex "LD3Rv(16b|8h|4s)$")>;
205def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr],  (instregex "LD3Rv(16b|8h|4s)_POST$")>;
206def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD3Rv(2d)$")>;
207def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>;
208
209def : InstRW<[A57Write_9cyc_2L_2V],               (instregex "LD3Threev(8b|4h|2s)$")>;
210def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr],     (instregex "LD3Threev(8b|4h|2s)_POST$")>;
211def : InstRW<[A57Write_10cyc_3L_4V],           (instregex "LD3Threev(16b|8h|4s)$")>;
212def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
213def : InstRW<[A57Write_8cyc_4L],               (instregex "LD3Threev(2d)$")>;
214def : InstRW<[A57Write_8cyc_4L, WriteAdr],     (instregex "LD3Threev(2d)_POST$")>;
215
216def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD4i(8|16)$")>;
217def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>;
218def : InstRW<[A57Write_8cyc_1L_2V],             (instregex "LD4i(32)$")>;
219def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],   (instregex "LD4i(32)_POST$")>;
220def : InstRW<[A57Write_9cyc_2L_3V],           (instregex "LD4i(64)$")>;
221def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>;
222
223def : InstRW<[A57Write_8cyc_1L_2V],              (instregex "LD4Rv(8b|4h|2s)$")>;
224def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr],    (instregex "LD4Rv(8b|4h|2s)_POST$")>;
225def : InstRW<[A57Write_6cyc_2L],               (instregex "LD4Rv(1d)$")>;
226def : InstRW<[A57Write_6cyc_2L, WriteAdr],     (instregex "LD4Rv(1d)_POST$")>;
227def : InstRW<[A57Write_9cyc_2L_3V],            (instregex "LD4Rv(16b|8h|4s)$")>;
228def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr],  (instregex "LD4Rv(16b|8h|4s)_POST$")>;
229def : InstRW<[A57Write_9cyc_2L_4V],           (instregex "LD4Rv(2d)$")>;
230def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>;
231
232def : InstRW<[A57Write_9cyc_2L_2V],                (instregex "LD4Fourv(8b|4h|2s)$")>;
233def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr],      (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
234def : InstRW<[A57Write_11cyc_4L_4V],           (instregex "LD4Fourv(16b|8h|4s)$")>;
235def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
236def : InstRW<[A57Write_8cyc_4L],                (instregex "LD4Fourv(2d)$")>;
237def : InstRW<[A57Write_8cyc_4L, WriteAdr],      (instregex "LD4Fourv(2d)_POST$")>;
238
239// Vector Store
240// -----------------------------------------------------------------------------
241
242def : InstRW<[A57Write_1cyc_1S],            (instregex "ST1i(8|16|32)$")>;
243def : InstRW<[A57Write_1cyc_1S, WriteAdr],  (instregex "ST1i(8|16|32)_POST$")>;
244def : InstRW<[A57Write_3cyc_1S_1V],           (instregex "ST1i(64)$")>;
245def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>;
246
247def : InstRW<[A57Write_1cyc_1S],                  (instregex "ST1Onev(8b|4h|2s|1d)$")>;
248def : InstRW<[A57Write_1cyc_1S, WriteAdr],        (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
249def : InstRW<[A57Write_2cyc_2S],                 (instregex "ST1Onev(16b|8h|4s|2d)$")>;
250def : InstRW<[A57Write_2cyc_2S, WriteAdr],       (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
251def : InstRW<[A57Write_2cyc_2S],                 (instregex "ST1Twov(8b|4h|2s|1d)$")>;
252def : InstRW<[A57Write_2cyc_2S, WriteAdr],       (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
253def : InstRW<[A57Write_4cyc_4S],               (instregex "ST1Twov(16b|8h|4s|2d)$")>;
254def : InstRW<[A57Write_4cyc_4S, WriteAdr],     (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
255def : InstRW<[A57Write_3cyc_3S],                (instregex "ST1Threev(8b|4h|2s|1d)$")>;
256def : InstRW<[A57Write_3cyc_3S, WriteAdr],      (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
257def : InstRW<[A57Write_6cyc_6S],             (instregex "ST1Threev(16b|8h|4s|2d)$")>;
258def : InstRW<[A57Write_6cyc_6S, WriteAdr],   (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
259def : InstRW<[A57Write_4cyc_4S],               (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
260def : InstRW<[A57Write_4cyc_4S, WriteAdr],     (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
261def : InstRW<[A57Write_8cyc_8S],           (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
262def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
263
264def : InstRW<[A57Write_3cyc_1S_1V],           (instregex "ST2i(8|16|32)$")>;
265def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>;
266def : InstRW<[A57Write_2cyc_2S],           (instregex "ST2i(64)$")>;
267def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>;
268
269def : InstRW<[A57Write_3cyc_2S_1V],              (instregex "ST2Twov(8b|4h|2s)$")>;
270def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr],    (instregex "ST2Twov(8b|4h|2s)_POST$")>;
271def : InstRW<[A57Write_4cyc_4S_2V],           (instregex "ST2Twov(16b|8h|4s)$")>;
272def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>;
273def : InstRW<[A57Write_4cyc_4S],             (instregex "ST2Twov(2d)$")>;
274def : InstRW<[A57Write_4cyc_4S, WriteAdr],   (instregex "ST2Twov(2d)_POST$")>;
275
276def : InstRW<[A57Write_3cyc_1S_1V],            (instregex "ST3i(8|16)$")>;
277def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr],  (instregex "ST3i(8|16)_POST$")>;
278def : InstRW<[A57Write_3cyc_3S],           (instregex "ST3i(32)$")>;
279def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>;
280def : InstRW<[A57Write_3cyc_2S_1V],           (instregex "ST3i(64)$")>;
281def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>;
282
283def : InstRW<[A57Write_3cyc_3S_2V],                 (instregex "ST3Threev(8b|4h|2s)$")>;
284def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr],       (instregex "ST3Threev(8b|4h|2s)_POST$")>;
285def : InstRW<[A57Write_6cyc_6S_4V],           (instregex "ST3Threev(16b|8h|4s)$")>;
286def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>;
287def : InstRW<[A57Write_6cyc_6S],                (instregex "ST3Threev(2d)$")>;
288def : InstRW<[A57Write_6cyc_6S, WriteAdr],      (instregex "ST3Threev(2d)_POST$")>;
289
290def : InstRW<[A57Write_3cyc_1S_1V],             (instregex "ST4i(8|16)$")>;
291def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr],   (instregex "ST4i(8|16)_POST$")>;
292def : InstRW<[A57Write_4cyc_4S],           (instregex "ST4i(32)$")>;
293def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>;
294def : InstRW<[A57Write_3cyc_2S_1V],            (instregex "ST4i(64)$")>;
295def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr],  (instregex "ST4i(64)_POST$")>;
296
297def : InstRW<[A57Write_4cyc_4S_2V],                  (instregex "ST4Fourv(8b|4h|2s)$")>;
298def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr],        (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
299def : InstRW<[A57Write_8cyc_8S_4V],           (instregex "ST4Fourv(16b|8h|4s)$")>;
300def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
301def : InstRW<[A57Write_8cyc_8S],                (instregex "ST4Fourv(2d)$")>;
302def : InstRW<[A57Write_8cyc_8S, WriteAdr],      (instregex "ST4Fourv(2d)_POST$")>;
303
304} // SchedModel = CortexA57Model
305