AArch64TargetMachine.h revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//=== AArch64TargetMachine.h - Define TargetMachine for AArch64 -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the AArch64 specific subclass of TargetMachine.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_AARCH64TARGETMACHINE_H
15#define LLVM_AARCH64TARGETMACHINE_H
16
17#include "AArch64FrameLowering.h"
18#include "AArch64ISelLowering.h"
19#include "AArch64InstrInfo.h"
20#include "AArch64SelectionDAGInfo.h"
21#include "AArch64Subtarget.h"
22#include "llvm/IR/DataLayout.h"
23#include "llvm/Target/TargetMachine.h"
24
25namespace llvm {
26
27class AArch64TargetMachine : public LLVMTargetMachine {
28  AArch64Subtarget          Subtarget;
29  AArch64InstrInfo          InstrInfo;
30  const DataLayout          DL;
31  AArch64TargetLowering     TLInfo;
32  AArch64SelectionDAGInfo   TSInfo;
33  AArch64FrameLowering      FrameLowering;
34
35public:
36  AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU,
37                       StringRef FS, const TargetOptions &Options,
38                       Reloc::Model RM, CodeModel::Model CM,
39                       CodeGenOpt::Level OL,
40                       bool LittleEndian);
41
42  const AArch64InstrInfo *getInstrInfo() const {
43    return &InstrInfo;
44  }
45
46  const AArch64FrameLowering *getFrameLowering() const {
47    return &FrameLowering;
48  }
49
50  const AArch64TargetLowering *getTargetLowering() const {
51    return &TLInfo;
52  }
53
54  const AArch64SelectionDAGInfo *getSelectionDAGInfo() const {
55    return &TSInfo;
56  }
57
58  const AArch64Subtarget *getSubtargetImpl() const { return &Subtarget; }
59
60  const DataLayout *getDataLayout() const { return &DL; }
61
62  const TargetRegisterInfo *getRegisterInfo() const {
63    return &InstrInfo.getRegisterInfo();
64  }
65  TargetPassConfig *createPassConfig(PassManagerBase &PM);
66
67  virtual void addAnalysisPasses(PassManagerBase &PM);
68};
69
70// AArch64leTargetMachine - AArch64 little endian target machine.
71//
72class AArch64leTargetMachine : public AArch64TargetMachine {
73  virtual void anchor();
74public:
75  AArch64leTargetMachine(const Target &T, StringRef TT,
76                         StringRef CPU, StringRef FS, const TargetOptions &Options,
77                         Reloc::Model RM, CodeModel::Model CM,
78                         CodeGenOpt::Level OL);
79};
80
81// AArch64beTargetMachine - AArch64 big endian target machine.
82//
83class AArch64beTargetMachine : public AArch64TargetMachine {
84  virtual void anchor();
85public:
86  AArch64beTargetMachine(const Target &T, StringRef TT,
87                         StringRef CPU, StringRef FS, const TargetOptions &Options,
88                         Reloc::Model RM, CodeModel::Model CM,
89                         CodeGenOpt::Level OL);
90};
91
92} // End llvm namespace
93
94#endif
95