AArch64Disassembler.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the functions necessary to decode AArch64 instruction 11// bitpatterns into MCInsts (with the help of TableGenerated information from 12// the instruction definitions). 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "arm-disassembler" 17 18#include "AArch64.h" 19#include "AArch64RegisterInfo.h" 20#include "AArch64Subtarget.h" 21#include "Utils/AArch64BaseInfo.h" 22#include "llvm/MC/MCContext.h" 23#include "llvm/MC/MCDisassembler.h" 24#include "llvm/MC/MCExpr.h" 25#include "llvm/MC/MCFixedLenDisassembler.h" 26#include "llvm/MC/MCInst.h" 27#include "llvm/MC/MCInstrDesc.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MemoryObject.h" 31#include "llvm/Support/TargetRegistry.h" 32#include "llvm/Support/raw_ostream.h" 33 34using namespace llvm; 35 36typedef MCDisassembler::DecodeStatus DecodeStatus; 37 38namespace { 39/// AArch64 disassembler for all AArch64 platforms. 40class AArch64Disassembler : public MCDisassembler { 41 OwningPtr<const MCRegisterInfo> RegInfo; 42public: 43 /// Initializes the disassembler. 44 /// 45 AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) 46 : MCDisassembler(STI), RegInfo(Info) { 47 } 48 49 ~AArch64Disassembler() {} 50 51 /// See MCDisassembler. 52 DecodeStatus getInstruction(MCInst &instr, 53 uint64_t &size, 54 const MemoryObject ®ion, 55 uint64_t address, 56 raw_ostream &vStream, 57 raw_ostream &cStream) const; 58 59 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); } 60}; 61 62} 63 64// Forward-declarations used in the auto-generated files. 65static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 66 uint64_t Address, const void *Decoder); 67static DecodeStatus 68DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 69 uint64_t Address, const void *Decoder); 70 71static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 72 uint64_t Address, const void *Decoder); 73static DecodeStatus 74DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 75 uint64_t Address, const void *Decoder); 76 77static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 78 uint64_t Address, const void *Decoder); 79static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 80 uint64_t Address, const void *Decoder); 81static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 82 uint64_t Address, const void *Decoder); 83static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 84 uint64_t Address, const void *Decoder); 85static DecodeStatus DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 86 uint64_t Address, const void *Decoder); 87static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, 88 unsigned RegNo, uint64_t Address, 89 const void *Decoder); 90static DecodeStatus DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, 91 unsigned RegNo, uint64_t Address, 92 const void *Decoder); 93 94static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst, 95 unsigned RegNo, 96 uint64_t Address, 97 const void *Decoder); 98 99static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst, 106 unsigned RegNo, uint64_t Address, 107 const void *Decoder); 108static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst, 109 unsigned RegNo, uint64_t Address, 110 const void *Decoder); 111static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, 113 const void *Decoder); 114static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 115 uint64_t Address, 116 const void *Decoder); 117 118static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst, 119 unsigned OptionHiS, 120 uint64_t Address, 121 const void *Decoder); 122 123 124static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst, 125 unsigned Imm6Bits, 126 uint64_t Address, 127 const void *Decoder); 128 129static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, 130 unsigned Imm6Bits, 131 uint64_t Address, 132 const void *Decoder); 133 134static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, 135 unsigned RmBits, 136 uint64_t Address, 137 const void *Decoder); 138 139static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val, 140 uint64_t Address, const void *Decoder); 141static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val, 142 uint64_t Address, 143 const void *Decoder); 144static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val, 145 uint64_t Address, 146 const void *Decoder); 147static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val, 148 uint64_t Address, 149 const void *Decoder); 150 151static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val, 152 uint64_t Address, const void *Decoder); 153static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val, 154 uint64_t Address, 155 const void *Decoder); 156static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val, 157 uint64_t Address, 158 const void *Decoder); 159static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val, 160 uint64_t Address, 161 const void *Decoder); 162 163template<int RegWidth> 164static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, 165 unsigned FullImm, 166 uint64_t Address, 167 const void *Decoder); 168 169template<int RegWidth> 170static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst, 171 unsigned Bits, 172 uint64_t Address, 173 const void *Decoder); 174 175static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst, 176 unsigned ShiftAmount, 177 uint64_t Address, 178 const void *Decoder); 179template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf> 180static DecodeStatus 181DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, 182 uint64_t Address, const void *Decoder); 183 184static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst, 185 unsigned ShiftAmount, 186 uint64_t Address, 187 const void *Decoder); 188static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, 189 uint64_t Address, 190 const void *Decoder); 191 192static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 193 uint64_t Address, 194 const void *Decoder); 195 196static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst, 197 unsigned Insn, 198 uint64_t Address, 199 const void *Decoder); 200 201static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, 202 unsigned Val, 203 uint64_t Address, 204 const void *Decoder); 205 206template<typename SomeNamedImmMapper> 207static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst, 208 unsigned Val, 209 uint64_t Address, 210 const void *Decoder); 211 212static DecodeStatus 213DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper, 214 llvm::MCInst &Inst, unsigned Val, 215 uint64_t Address, const void *Decoder); 216 217static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst, 218 unsigned Val, 219 uint64_t Address, 220 const void *Decoder); 221 222static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst, 223 unsigned Val, 224 uint64_t Address, 225 const void *Decoder); 226 227 228static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst, 229 unsigned Val, 230 uint64_t Address, 231 const void *Decoder); 232 233static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Val, 234 uint64_t Address, 235 const void *Decoder); 236 237static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn, 238 uint64_t Address, 239 const void *Decoder); 240 241static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn, 242 uint64_t Address, 243 const void *Decoder); 244 245static bool Check(DecodeStatus &Out, DecodeStatus In); 246 247#include "AArch64GenDisassemblerTables.inc" 248 249static bool Check(DecodeStatus &Out, DecodeStatus In) { 250 switch (In) { 251 case MCDisassembler::Success: 252 // Out stays the same. 253 return true; 254 case MCDisassembler::SoftFail: 255 Out = In; 256 return true; 257 case MCDisassembler::Fail: 258 Out = In; 259 return false; 260 } 261 llvm_unreachable("Invalid DecodeStatus!"); 262} 263 264DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 265 const MemoryObject &Region, 266 uint64_t Address, 267 raw_ostream &os, 268 raw_ostream &cs) const { 269 CommentStream = &cs; 270 271 uint8_t bytes[4]; 272 273 // We want to read exactly 4 bytes of data. 274 if (Region.readBytes(Address, 4, bytes) == -1) { 275 Size = 0; 276 return MCDisassembler::Fail; 277 } 278 279 // Encoded as a small-endian 32-bit word in the stream. 280 uint32_t insn = (bytes[3] << 24) | 281 (bytes[2] << 16) | 282 (bytes[1] << 8) | 283 (bytes[0] << 0); 284 285 // Calling the auto-generated decoder function. 286 DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address, 287 this, STI); 288 if (result != MCDisassembler::Fail) { 289 Size = 4; 290 return result; 291 } 292 293 MI.clear(); 294 Size = 0; 295 return MCDisassembler::Fail; 296} 297 298static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 299 const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D); 300 return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo); 301} 302 303static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 304 uint64_t Address, const void *Decoder) { 305 if (RegNo > 31) 306 return MCDisassembler::Fail; 307 308 uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo); 309 Inst.addOperand(MCOperand::CreateReg(Register)); 310 return MCDisassembler::Success; 311} 312 313static DecodeStatus 314DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 315 uint64_t Address, const void *Decoder) { 316 if (RegNo > 31) 317 return MCDisassembler::Fail; 318 319 uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo); 320 Inst.addOperand(MCOperand::CreateReg(Register)); 321 return MCDisassembler::Success; 322} 323 324static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 325 uint64_t Address, 326 const void *Decoder) { 327 if (RegNo > 31) 328 return MCDisassembler::Fail; 329 330 uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo); 331 Inst.addOperand(MCOperand::CreateReg(Register)); 332 return MCDisassembler::Success; 333} 334 335static DecodeStatus 336DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 337 uint64_t Address, const void *Decoder) { 338 if (RegNo > 31) 339 return MCDisassembler::Fail; 340 341 uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo); 342 Inst.addOperand(MCOperand::CreateReg(Register)); 343 return MCDisassembler::Success; 344} 345 346static DecodeStatus 347DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 348 uint64_t Address, const void *Decoder) { 349 if (RegNo > 31) 350 return MCDisassembler::Fail; 351 352 uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo); 353 Inst.addOperand(MCOperand::CreateReg(Register)); 354 return MCDisassembler::Success; 355} 356 357static DecodeStatus 358DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 359 uint64_t Address, const void *Decoder) { 360 if (RegNo > 31) 361 return MCDisassembler::Fail; 362 363 uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo); 364 Inst.addOperand(MCOperand::CreateReg(Register)); 365 return MCDisassembler::Success; 366} 367 368 369static DecodeStatus 370DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 371 uint64_t Address, const void *Decoder) { 372 if (RegNo > 31) 373 return MCDisassembler::Fail; 374 375 uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo); 376 Inst.addOperand(MCOperand::CreateReg(Register)); 377 return MCDisassembler::Success; 378} 379 380static DecodeStatus 381DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 382 uint64_t Address, const void *Decoder) { 383 if (RegNo > 31) 384 return MCDisassembler::Fail; 385 386 uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo); 387 Inst.addOperand(MCOperand::CreateReg(Register)); 388 return MCDisassembler::Success; 389} 390 391static DecodeStatus 392DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 393 uint64_t Address, const void *Decoder) { 394 if (RegNo > 15) 395 return MCDisassembler::Fail; 396 397 return DecodeFPR64RegisterClass(Inst, RegNo, Address, Decoder); 398} 399 400static DecodeStatus 401DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 402 uint64_t Address, const void *Decoder) { 403 if (RegNo > 31) 404 return MCDisassembler::Fail; 405 406 uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo); 407 Inst.addOperand(MCOperand::CreateReg(Register)); 408 return MCDisassembler::Success; 409} 410 411static DecodeStatus 412DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 413 uint64_t Address, const void *Decoder) { 414 if (RegNo > 15) 415 return MCDisassembler::Fail; 416 417 return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder); 418} 419 420static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst, 421 unsigned RegNo, 422 uint64_t Address, 423 const void *Decoder) { 424 if (RegNo > 30) 425 return MCDisassembler::Fail; 426 427 uint16_t Register = getReg(Decoder, AArch64::GPR64noxzrRegClassID, RegNo); 428 Inst.addOperand(MCOperand::CreateReg(Register)); 429 return MCDisassembler::Success; 430} 431 432static DecodeStatus DecodeRegisterClassByID(llvm::MCInst &Inst, unsigned RegNo, 433 unsigned RegID, 434 const void *Decoder) { 435 if (RegNo > 31) 436 return MCDisassembler::Fail; 437 438 uint16_t Register = getReg(Decoder, RegID, RegNo); 439 Inst.addOperand(MCOperand::CreateReg(Register)); 440 return MCDisassembler::Success; 441} 442 443static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 444 uint64_t Address, 445 const void *Decoder) { 446 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DPairRegClassID, 447 Decoder); 448} 449 450static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 451 uint64_t Address, 452 const void *Decoder) { 453 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QPairRegClassID, 454 Decoder); 455} 456 457static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst, 458 unsigned RegNo, uint64_t Address, 459 const void *Decoder) { 460 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DTripleRegClassID, 461 Decoder); 462} 463 464static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst, 465 unsigned RegNo, uint64_t Address, 466 const void *Decoder) { 467 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QTripleRegClassID, 468 Decoder); 469} 470 471static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 472 uint64_t Address, 473 const void *Decoder) { 474 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DQuadRegClassID, 475 Decoder); 476} 477 478static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 479 uint64_t Address, 480 const void *Decoder) { 481 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QQuadRegClassID, 482 Decoder); 483} 484 485static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst, 486 unsigned OptionHiS, 487 uint64_t Address, 488 const void *Decoder) { 489 // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1}, 490 // S}. Hence we want to check bit 1. 491 if (!(OptionHiS & 2)) 492 return MCDisassembler::Fail; 493 494 Inst.addOperand(MCOperand::CreateImm(OptionHiS)); 495 return MCDisassembler::Success; 496} 497 498static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst, 499 unsigned Imm6Bits, 500 uint64_t Address, 501 const void *Decoder) { 502 // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be 503 // between 0 and 31. 504 if (Imm6Bits > 31) 505 return MCDisassembler::Fail; 506 507 Inst.addOperand(MCOperand::CreateImm(Imm6Bits)); 508 return MCDisassembler::Success; 509} 510 511static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, 512 unsigned Imm6Bits, 513 uint64_t Address, 514 const void *Decoder) { 515 // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32. 516 if (Imm6Bits < 32) 517 return MCDisassembler::Fail; 518 519 Inst.addOperand(MCOperand::CreateImm(Imm6Bits)); 520 return MCDisassembler::Success; 521} 522 523static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, 524 unsigned RmBits, 525 uint64_t Address, 526 const void *Decoder) { 527 // Any bits are valid in the instruction (they're architecturally ignored), 528 // but a code generator should insert 0. 529 Inst.addOperand(MCOperand::CreateImm(0)); 530 return MCDisassembler::Success; 531} 532 533static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val, 534 uint64_t Address, 535 const void *Decoder) { 536 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 537 return MCDisassembler::Success; 538} 539 540static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val, 541 uint64_t Address, 542 const void *Decoder) { 543 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 544 return MCDisassembler::Success; 545} 546 547static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val, 548 uint64_t Address, 549 const void *Decoder) { 550 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 551 return MCDisassembler::Success; 552} 553 554static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val, 555 uint64_t Address, 556 const void *Decoder) { 557 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 558 return MCDisassembler::Success; 559} 560 561static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val, 562 uint64_t Address, 563 const void *Decoder) { 564 if (Val > 7) 565 return MCDisassembler::Fail; 566 567 Inst.addOperand(MCOperand::CreateImm(Val)); 568 return MCDisassembler::Success; 569} 570 571static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val, 572 uint64_t Address, 573 const void *Decoder) { 574 if (Val > 15) 575 return MCDisassembler::Fail; 576 577 Inst.addOperand(MCOperand::CreateImm(Val)); 578 return MCDisassembler::Success; 579} 580 581static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val, 582 uint64_t Address, 583 const void *Decoder) { 584 if (Val > 31) 585 return MCDisassembler::Fail; 586 587 Inst.addOperand(MCOperand::CreateImm(Val)); 588 return MCDisassembler::Success; 589} 590 591static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val, 592 uint64_t Address, 593 const void *Decoder) { 594 if (Val > 63) 595 return MCDisassembler::Fail; 596 597 Inst.addOperand(MCOperand::CreateImm(Val)); 598 return MCDisassembler::Success; 599} 600 601template<int RegWidth> 602static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, 603 unsigned FullImm, 604 uint64_t Address, 605 const void *Decoder) { 606 unsigned Imm16 = FullImm & 0xffff; 607 unsigned Shift = FullImm >> 16; 608 609 if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail; 610 611 Inst.addOperand(MCOperand::CreateImm(Imm16)); 612 Inst.addOperand(MCOperand::CreateImm(Shift)); 613 return MCDisassembler::Success; 614} 615 616template<int RegWidth> 617static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst, 618 unsigned Bits, 619 uint64_t Address, 620 const void *Decoder) { 621 uint64_t Imm; 622 if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm)) 623 return MCDisassembler::Fail; 624 625 Inst.addOperand(MCOperand::CreateImm(Bits)); 626 return MCDisassembler::Success; 627} 628 629 630static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst, 631 unsigned ShiftAmount, 632 uint64_t Address, 633 const void *Decoder) { 634 // Only values 0-4 are valid for this 3-bit field 635 if (ShiftAmount > 4) 636 return MCDisassembler::Fail; 637 638 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 639 return MCDisassembler::Success; 640} 641 642static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst, 643 unsigned ShiftAmount, 644 uint64_t Address, 645 const void *Decoder) { 646 // Only values below 32 are valid for a 32-bit register 647 if (ShiftAmount > 31) 648 return MCDisassembler::Fail; 649 650 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 651 return MCDisassembler::Success; 652} 653 654static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, 655 uint64_t Address, 656 const void *Decoder) { 657 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 658 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 659 unsigned ImmS = fieldFromInstruction(Insn, 10, 6); 660 unsigned ImmR = fieldFromInstruction(Insn, 16, 6); 661 unsigned SF = fieldFromInstruction(Insn, 31, 1); 662 663 // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise 664 // out assertions that it thinks should never be hit. 665 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc; 666 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2); 667 668 if (!SF) { 669 // ImmR and ImmS must be between 0 and 31 for 32-bit instructions. 670 if (ImmR > 31 || ImmS > 31) 671 return MCDisassembler::Fail; 672 } 673 674 if (SF) { 675 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 676 // BFM MCInsts use Rd as a source too. 677 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 678 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 679 } else { 680 DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); 681 // BFM MCInsts use Rd as a source too. 682 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); 683 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder); 684 } 685 686 // ASR and LSR have more specific patterns so they won't get here: 687 assert(!(ImmS == 31 && !SF && Opc != BFM) 688 && "shift should have used auto decode"); 689 assert(!(ImmS == 63 && SF && Opc != BFM) 690 && "shift should have used auto decode"); 691 692 // Extension instructions similarly: 693 if (Opc == SBFM && ImmR == 0) { 694 assert((ImmS != 7 && ImmS != 15) && "extension got here"); 695 assert((ImmS != 31 || SF == 0) && "extension got here"); 696 } else if (Opc == UBFM && ImmR == 0) { 697 assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here"); 698 } 699 700 if (Opc == UBFM) { 701 // It might be a LSL instruction, which actually takes the shift amount 702 // itself as an MCInst operand. 703 if (SF && (ImmS + 1) % 64 == ImmR) { 704 Inst.setOpcode(AArch64::LSLxxi); 705 Inst.addOperand(MCOperand::CreateImm(63 - ImmS)); 706 return MCDisassembler::Success; 707 } else if (!SF && (ImmS + 1) % 32 == ImmR) { 708 Inst.setOpcode(AArch64::LSLwwi); 709 Inst.addOperand(MCOperand::CreateImm(31 - ImmS)); 710 return MCDisassembler::Success; 711 } 712 } 713 714 // Otherwise it's definitely either an extract or an insert depending on which 715 // of ImmR or ImmS is larger. 716 unsigned ExtractOp, InsertOp; 717 switch (Opc) { 718 default: llvm_unreachable("unexpected instruction trying to decode bitfield"); 719 case SBFM: 720 ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii; 721 InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii; 722 break; 723 case BFM: 724 ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii; 725 InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii; 726 break; 727 case UBFM: 728 ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii; 729 InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii; 730 break; 731 } 732 733 // Otherwise it's a boring insert or extract 734 Inst.addOperand(MCOperand::CreateImm(ImmR)); 735 Inst.addOperand(MCOperand::CreateImm(ImmS)); 736 737 738 if (ImmS < ImmR) 739 Inst.setOpcode(InsertOp); 740 else 741 Inst.setOpcode(ExtractOp); 742 743 return MCDisassembler::Success; 744} 745 746static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 747 uint64_t Address, 748 const void *Decoder) { 749 // This decoder exists to add the dummy Lane operand to the MCInst, which must 750 // be 1 in assembly but has no other real manifestation. 751 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 752 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 753 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 754 755 if (IsToVec) { 756 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 757 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 758 } else { 759 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 760 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 761 } 762 763 // Add the lane 764 Inst.addOperand(MCOperand::CreateImm(1)); 765 766 return MCDisassembler::Success; 767} 768 769 770static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst, 771 unsigned Insn, 772 uint64_t Address, 773 const void *Decoder) { 774 DecodeStatus Result = MCDisassembler::Success; 775 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 776 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 777 unsigned Rt2 = fieldFromInstruction(Insn, 10, 5); 778 unsigned SImm7 = fieldFromInstruction(Insn, 15, 7); 779 unsigned L = fieldFromInstruction(Insn, 22, 1); 780 unsigned V = fieldFromInstruction(Insn, 26, 1); 781 unsigned Opc = fieldFromInstruction(Insn, 30, 2); 782 783 // Not an official name, but it turns out that bit 23 distinguishes indexed 784 // from non-indexed operations. 785 unsigned Indexed = fieldFromInstruction(Insn, 23, 1); 786 787 if (Indexed && L == 0) { 788 // The MCInst for an indexed store has an out operand and 4 ins: 789 // Rn_wb, Rt, Rt2, Rn, Imm 790 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 791 } 792 793 // You shouldn't load to the same register twice in an instruction... 794 if (L && Rt == Rt2) 795 Result = MCDisassembler::SoftFail; 796 797 // ... or do any operation that writes-back to a transfer register. But note 798 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 799 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 800 Result = MCDisassembler::SoftFail; 801 802 // Exactly how we decode the MCInst's registers depends on the Opc and V 803 // fields of the instruction. These also obviously determine the size of the 804 // operation so we can fill in that information while we're at it. 805 if (V) { 806 // The instruction operates on the FP/SIMD registers 807 switch (Opc) { 808 default: return MCDisassembler::Fail; 809 case 0: 810 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder); 811 DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder); 812 break; 813 case 1: 814 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 815 DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder); 816 break; 817 case 2: 818 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 819 DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder); 820 break; 821 } 822 } else { 823 switch (Opc) { 824 default: return MCDisassembler::Fail; 825 case 0: 826 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder); 827 DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder); 828 break; 829 case 1: 830 assert(L && "unexpected \"store signed\" attempt"); 831 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 832 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder); 833 break; 834 case 2: 835 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 836 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder); 837 break; 838 } 839 } 840 841 if (Indexed && L == 1) { 842 // The MCInst for an indexed load has 3 out operands and an 3 ins: 843 // Rt, Rt2, Rn_wb, Rt2, Rn, Imm 844 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 845 } 846 847 848 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 849 Inst.addOperand(MCOperand::CreateImm(SImm7)); 850 851 return Result; 852} 853 854static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, 855 uint32_t Val, 856 uint64_t Address, 857 const void *Decoder) { 858 unsigned Rt = fieldFromInstruction(Val, 0, 5); 859 unsigned Rn = fieldFromInstruction(Val, 5, 5); 860 unsigned Rt2 = fieldFromInstruction(Val, 10, 5); 861 unsigned MemSize = fieldFromInstruction(Val, 30, 2); 862 863 DecodeStatus S = MCDisassembler::Success; 864 if (Rt == Rt2) S = MCDisassembler::SoftFail; 865 866 switch (MemSize) { 867 case 2: 868 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder))) 869 return MCDisassembler::Fail; 870 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder))) 871 return MCDisassembler::Fail; 872 break; 873 case 3: 874 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder))) 875 return MCDisassembler::Fail; 876 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder))) 877 return MCDisassembler::Fail; 878 break; 879 default: 880 llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction"); 881 } 882 883 if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder))) 884 return MCDisassembler::Fail; 885 886 return S; 887} 888 889template<typename SomeNamedImmMapper> 890static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst, 891 unsigned Val, 892 uint64_t Address, 893 const void *Decoder) { 894 SomeNamedImmMapper Mapper; 895 bool ValidNamed; 896 Mapper.toString(Val, ValidNamed); 897 if (ValidNamed || Mapper.validImm(Val)) { 898 Inst.addOperand(MCOperand::CreateImm(Val)); 899 return MCDisassembler::Success; 900 } 901 902 return MCDisassembler::Fail; 903} 904 905static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper, 906 llvm::MCInst &Inst, 907 unsigned Val, 908 uint64_t Address, 909 const void *Decoder) { 910 bool ValidNamed; 911 Mapper.toString(Val, ValidNamed); 912 913 Inst.addOperand(MCOperand::CreateImm(Val)); 914 915 return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail; 916} 917 918static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst, 919 unsigned Val, 920 uint64_t Address, 921 const void *Decoder) { 922 return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address, 923 Decoder); 924} 925 926static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst, 927 unsigned Val, 928 uint64_t Address, 929 const void *Decoder) { 930 return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address, 931 Decoder); 932} 933 934static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst, 935 unsigned Insn, 936 uint64_t Address, 937 const void *Decoder) { 938 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 939 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 940 unsigned Imm9 = fieldFromInstruction(Insn, 12, 9); 941 942 unsigned Opc = fieldFromInstruction(Insn, 22, 2); 943 unsigned V = fieldFromInstruction(Insn, 26, 1); 944 unsigned Size = fieldFromInstruction(Insn, 30, 2); 945 946 if (Opc == 0 || (V == 1 && Opc == 2)) { 947 // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm 948 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 949 } 950 951 if (V == 0 && (Opc == 2 || Size == 3)) { 952 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 953 } else if (V == 0) { 954 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder); 955 } else if (V == 1 && (Opc & 2)) { 956 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 957 } else { 958 switch (Size) { 959 case 0: 960 DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder); 961 break; 962 case 1: 963 DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder); 964 break; 965 case 2: 966 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder); 967 break; 968 case 3: 969 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 970 break; 971 } 972 } 973 974 if (Opc != 0 && (V != 1 || Opc != 2)) { 975 // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm 976 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 977 } 978 979 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 980 981 Inst.addOperand(MCOperand::CreateImm(Imm9)); 982 983 // N.b. The official documentation says undpredictable if Rt == Rn, but this 984 // takes place at the architectural rather than encoding level: 985 // 986 // "STR xzr, [sp], #4" is perfectly valid. 987 if (V == 0 && Rt == Rn && Rn != 31) 988 return MCDisassembler::SoftFail; 989 else 990 return MCDisassembler::Success; 991} 992 993static MCDisassembler *createAArch64Disassembler(const Target &T, 994 const MCSubtargetInfo &STI) { 995 return new AArch64Disassembler(STI, T.createMCRegInfo("")); 996} 997 998extern "C" void LLVMInitializeAArch64Disassembler() { 999 TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget, 1000 createAArch64Disassembler); 1001 TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget, 1002 createAArch64Disassembler); 1003} 1004 1005template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf> 1006static DecodeStatus 1007DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, 1008 uint64_t Address, const void *Decoder) { 1009 bool IsLSL = false; 1010 if (Ext == A64SE::LSL) 1011 IsLSL = true; 1012 else if (Ext != A64SE::MSL) 1013 return MCDisassembler::Fail; 1014 1015 // MSL and LSLH accepts encoded shift amount 0 or 1. 1016 if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1) 1017 return MCDisassembler::Fail; 1018 1019 // LSL accepts encoded shift amount 0, 1, 2 or 3. 1020 if (IsLSL && ShiftAmount > 3) 1021 return MCDisassembler::Fail; 1022 1023 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 1024 return MCDisassembler::Success; 1025} 1026 1027// Decode post-index vector load/store instructions. 1028// This is necessary as we need to decode Rm: if Rm == 0b11111, the last 1029// operand is an immediate equal the the length of vector list in bytes, 1030// or Rm is decoded to a GPR64noxzr register. 1031static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Insn, 1032 uint64_t Address, 1033 const void *Decoder) { 1034 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 1035 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 1036 unsigned Rm = fieldFromInstruction(Insn, 16, 5); 1037 unsigned Opcode = fieldFromInstruction(Insn, 12, 4); 1038 unsigned IsLoad = fieldFromInstruction(Insn, 22, 1); 1039 // 0 for 64bit vector list, 1 for 128bit vector list 1040 unsigned Is128BitVec = fieldFromInstruction(Insn, 30, 1); 1041 1042 unsigned NumVecs; 1043 switch (Opcode) { 1044 case 0: // ld4/st4 1045 case 2: // ld1/st1 with 4 vectors 1046 NumVecs = 4; break; 1047 case 4: // ld3/st3 1048 case 6: // ld1/st1 with 3 vectors 1049 NumVecs = 3; break; 1050 case 7: // ld1/st1 with 1 vector 1051 NumVecs = 1; break; 1052 case 8: // ld2/st2 1053 case 10: // ld1/st1 with 2 vectors 1054 NumVecs = 2; break; 1055 default: 1056 llvm_unreachable("Invalid opcode for post-index load/store instructions"); 1057 } 1058 1059 // Decode vector list of 1/2/3/4 vectors for load instructions. 1060 if (IsLoad) { 1061 switch (NumVecs) { 1062 case 1: 1063 Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder) 1064 : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 1065 break; 1066 case 2: 1067 Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder) 1068 : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder); 1069 break; 1070 case 3: 1071 Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder) 1072 : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder); 1073 break; 1074 case 4: 1075 Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder) 1076 : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder); 1077 break; 1078 } 1079 } 1080 1081 // Decode write back register, which is equal to Rn. 1082 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1083 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1084 1085 if (Rm == 31) // If Rm is 0x11111, add the vector list length in byte 1086 Inst.addOperand(MCOperand::CreateImm(NumVecs * (Is128BitVec ? 16 : 8))); 1087 else // Decode Rm 1088 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder); 1089 1090 // Decode vector list of 1/2/3/4 vectors for load instructions. 1091 if (!IsLoad) { 1092 switch (NumVecs) { 1093 case 1: 1094 Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder) 1095 : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 1096 break; 1097 case 2: 1098 Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder) 1099 : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder); 1100 break; 1101 case 3: 1102 Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder) 1103 : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder); 1104 break; 1105 case 4: 1106 Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder) 1107 : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder); 1108 break; 1109 } 1110 } 1111 1112 return MCDisassembler::Success; 1113} 1114 1115// Decode post-index vector load/store lane instructions. 1116// This is necessary as we need to decode Rm: if Rm == 0b11111, the last 1117// operand is an immediate equal the the length of the changed bytes, 1118// or Rm is decoded to a GPR64noxzr register. 1119static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn, 1120 uint64_t Address, 1121 const void *Decoder) { 1122 bool Is64bitVec = false; 1123 bool IsLoadDup = false; 1124 bool IsLoad = false; 1125 // The total number of bytes transferred. 1126 // TransferBytes = NumVecs * OneLaneBytes 1127 unsigned TransferBytes = 0; 1128 unsigned NumVecs = 0; 1129 unsigned Opc = Inst.getOpcode(); 1130 switch (Opc) { 1131 case AArch64::LD1R_WB_8B_fixed: case AArch64::LD1R_WB_8B_register: 1132 case AArch64::LD1R_WB_4H_fixed: case AArch64::LD1R_WB_4H_register: 1133 case AArch64::LD1R_WB_2S_fixed: case AArch64::LD1R_WB_2S_register: 1134 case AArch64::LD1R_WB_1D_fixed: case AArch64::LD1R_WB_1D_register: { 1135 switch (Opc) { 1136 case AArch64::LD1R_WB_8B_fixed: case AArch64::LD1R_WB_8B_register: 1137 TransferBytes = 1; break; 1138 case AArch64::LD1R_WB_4H_fixed: case AArch64::LD1R_WB_4H_register: 1139 TransferBytes = 2; break; 1140 case AArch64::LD1R_WB_2S_fixed: case AArch64::LD1R_WB_2S_register: 1141 TransferBytes = 4; break; 1142 case AArch64::LD1R_WB_1D_fixed: case AArch64::LD1R_WB_1D_register: 1143 TransferBytes = 8; break; 1144 } 1145 Is64bitVec = true; 1146 IsLoadDup = true; 1147 NumVecs = 1; 1148 break; 1149 } 1150 1151 case AArch64::LD1R_WB_16B_fixed: case AArch64::LD1R_WB_16B_register: 1152 case AArch64::LD1R_WB_8H_fixed: case AArch64::LD1R_WB_8H_register: 1153 case AArch64::LD1R_WB_4S_fixed: case AArch64::LD1R_WB_4S_register: 1154 case AArch64::LD1R_WB_2D_fixed: case AArch64::LD1R_WB_2D_register: { 1155 switch (Opc) { 1156 case AArch64::LD1R_WB_16B_fixed: case AArch64::LD1R_WB_16B_register: 1157 TransferBytes = 1; break; 1158 case AArch64::LD1R_WB_8H_fixed: case AArch64::LD1R_WB_8H_register: 1159 TransferBytes = 2; break; 1160 case AArch64::LD1R_WB_4S_fixed: case AArch64::LD1R_WB_4S_register: 1161 TransferBytes = 4; break; 1162 case AArch64::LD1R_WB_2D_fixed: case AArch64::LD1R_WB_2D_register: 1163 TransferBytes = 8; break; 1164 } 1165 IsLoadDup = true; 1166 NumVecs = 1; 1167 break; 1168 } 1169 1170 case AArch64::LD2R_WB_8B_fixed: case AArch64::LD2R_WB_8B_register: 1171 case AArch64::LD2R_WB_4H_fixed: case AArch64::LD2R_WB_4H_register: 1172 case AArch64::LD2R_WB_2S_fixed: case AArch64::LD2R_WB_2S_register: 1173 case AArch64::LD2R_WB_1D_fixed: case AArch64::LD2R_WB_1D_register: { 1174 switch (Opc) { 1175 case AArch64::LD2R_WB_8B_fixed: case AArch64::LD2R_WB_8B_register: 1176 TransferBytes = 2; break; 1177 case AArch64::LD2R_WB_4H_fixed: case AArch64::LD2R_WB_4H_register: 1178 TransferBytes = 4; break; 1179 case AArch64::LD2R_WB_2S_fixed: case AArch64::LD2R_WB_2S_register: 1180 TransferBytes = 8; break; 1181 case AArch64::LD2R_WB_1D_fixed: case AArch64::LD2R_WB_1D_register: 1182 TransferBytes = 16; break; 1183 } 1184 Is64bitVec = true; 1185 IsLoadDup = true; 1186 NumVecs = 2; 1187 break; 1188 } 1189 1190 case AArch64::LD2R_WB_16B_fixed: case AArch64::LD2R_WB_16B_register: 1191 case AArch64::LD2R_WB_8H_fixed: case AArch64::LD2R_WB_8H_register: 1192 case AArch64::LD2R_WB_4S_fixed: case AArch64::LD2R_WB_4S_register: 1193 case AArch64::LD2R_WB_2D_fixed: case AArch64::LD2R_WB_2D_register: { 1194 switch (Opc) { 1195 case AArch64::LD2R_WB_16B_fixed: case AArch64::LD2R_WB_16B_register: 1196 TransferBytes = 2; break; 1197 case AArch64::LD2R_WB_8H_fixed: case AArch64::LD2R_WB_8H_register: 1198 TransferBytes = 4; break; 1199 case AArch64::LD2R_WB_4S_fixed: case AArch64::LD2R_WB_4S_register: 1200 TransferBytes = 8; break; 1201 case AArch64::LD2R_WB_2D_fixed: case AArch64::LD2R_WB_2D_register: 1202 TransferBytes = 16; break; 1203 } 1204 IsLoadDup = true; 1205 NumVecs = 2; 1206 break; 1207 } 1208 1209 case AArch64::LD3R_WB_8B_fixed: case AArch64::LD3R_WB_8B_register: 1210 case AArch64::LD3R_WB_4H_fixed: case AArch64::LD3R_WB_4H_register: 1211 case AArch64::LD3R_WB_2S_fixed: case AArch64::LD3R_WB_2S_register: 1212 case AArch64::LD3R_WB_1D_fixed: case AArch64::LD3R_WB_1D_register: { 1213 switch (Opc) { 1214 case AArch64::LD3R_WB_8B_fixed: case AArch64::LD3R_WB_8B_register: 1215 TransferBytes = 3; break; 1216 case AArch64::LD3R_WB_4H_fixed: case AArch64::LD3R_WB_4H_register: 1217 TransferBytes = 6; break; 1218 case AArch64::LD3R_WB_2S_fixed: case AArch64::LD3R_WB_2S_register: 1219 TransferBytes = 12; break; 1220 case AArch64::LD3R_WB_1D_fixed: case AArch64::LD3R_WB_1D_register: 1221 TransferBytes = 24; break; 1222 } 1223 Is64bitVec = true; 1224 IsLoadDup = true; 1225 NumVecs = 3; 1226 break; 1227 } 1228 1229 case AArch64::LD3R_WB_16B_fixed: case AArch64::LD3R_WB_16B_register: 1230 case AArch64::LD3R_WB_4S_fixed: case AArch64::LD3R_WB_8H_register: 1231 case AArch64::LD3R_WB_8H_fixed: case AArch64::LD3R_WB_4S_register: 1232 case AArch64::LD3R_WB_2D_fixed: case AArch64::LD3R_WB_2D_register: { 1233 switch (Opc) { 1234 case AArch64::LD3R_WB_16B_fixed: case AArch64::LD3R_WB_16B_register: 1235 TransferBytes = 3; break; 1236 case AArch64::LD3R_WB_8H_fixed: case AArch64::LD3R_WB_8H_register: 1237 TransferBytes = 6; break; 1238 case AArch64::LD3R_WB_4S_fixed: case AArch64::LD3R_WB_4S_register: 1239 TransferBytes = 12; break; 1240 case AArch64::LD3R_WB_2D_fixed: case AArch64::LD3R_WB_2D_register: 1241 TransferBytes = 24; break; 1242 } 1243 IsLoadDup = true; 1244 NumVecs = 3; 1245 break; 1246 } 1247 1248 case AArch64::LD4R_WB_8B_fixed: case AArch64::LD4R_WB_8B_register: 1249 case AArch64::LD4R_WB_4H_fixed: case AArch64::LD4R_WB_4H_register: 1250 case AArch64::LD4R_WB_2S_fixed: case AArch64::LD4R_WB_2S_register: 1251 case AArch64::LD4R_WB_1D_fixed: case AArch64::LD4R_WB_1D_register: { 1252 switch (Opc) { 1253 case AArch64::LD4R_WB_8B_fixed: case AArch64::LD4R_WB_8B_register: 1254 TransferBytes = 4; break; 1255 case AArch64::LD4R_WB_4H_fixed: case AArch64::LD4R_WB_4H_register: 1256 TransferBytes = 8; break; 1257 case AArch64::LD4R_WB_2S_fixed: case AArch64::LD4R_WB_2S_register: 1258 TransferBytes = 16; break; 1259 case AArch64::LD4R_WB_1D_fixed: case AArch64::LD4R_WB_1D_register: 1260 TransferBytes = 32; break; 1261 } 1262 Is64bitVec = true; 1263 IsLoadDup = true; 1264 NumVecs = 4; 1265 break; 1266 } 1267 1268 case AArch64::LD4R_WB_16B_fixed: case AArch64::LD4R_WB_16B_register: 1269 case AArch64::LD4R_WB_4S_fixed: case AArch64::LD4R_WB_8H_register: 1270 case AArch64::LD4R_WB_8H_fixed: case AArch64::LD4R_WB_4S_register: 1271 case AArch64::LD4R_WB_2D_fixed: case AArch64::LD4R_WB_2D_register: { 1272 switch (Opc) { 1273 case AArch64::LD4R_WB_16B_fixed: case AArch64::LD4R_WB_16B_register: 1274 TransferBytes = 4; break; 1275 case AArch64::LD4R_WB_8H_fixed: case AArch64::LD4R_WB_8H_register: 1276 TransferBytes = 8; break; 1277 case AArch64::LD4R_WB_4S_fixed: case AArch64::LD4R_WB_4S_register: 1278 TransferBytes = 16; break; 1279 case AArch64::LD4R_WB_2D_fixed: case AArch64::LD4R_WB_2D_register: 1280 TransferBytes = 32; break; 1281 } 1282 IsLoadDup = true; 1283 NumVecs = 4; 1284 break; 1285 } 1286 1287 case AArch64::LD1LN_WB_B_fixed: case AArch64::LD1LN_WB_B_register: 1288 case AArch64::LD1LN_WB_H_fixed: case AArch64::LD1LN_WB_H_register: 1289 case AArch64::LD1LN_WB_S_fixed: case AArch64::LD1LN_WB_S_register: 1290 case AArch64::LD1LN_WB_D_fixed: case AArch64::LD1LN_WB_D_register: { 1291 switch (Opc) { 1292 case AArch64::LD1LN_WB_B_fixed: case AArch64::LD1LN_WB_B_register: 1293 TransferBytes = 1; break; 1294 case AArch64::LD1LN_WB_H_fixed: case AArch64::LD1LN_WB_H_register: 1295 TransferBytes = 2; break; 1296 case AArch64::LD1LN_WB_S_fixed: case AArch64::LD1LN_WB_S_register: 1297 TransferBytes = 4; break; 1298 case AArch64::LD1LN_WB_D_fixed: case AArch64::LD1LN_WB_D_register: 1299 TransferBytes = 8; break; 1300 } 1301 IsLoad = true; 1302 NumVecs = 1; 1303 break; 1304 } 1305 1306 case AArch64::LD2LN_WB_B_fixed: case AArch64::LD2LN_WB_B_register: 1307 case AArch64::LD2LN_WB_H_fixed: case AArch64::LD2LN_WB_H_register: 1308 case AArch64::LD2LN_WB_S_fixed: case AArch64::LD2LN_WB_S_register: 1309 case AArch64::LD2LN_WB_D_fixed: case AArch64::LD2LN_WB_D_register: { 1310 switch (Opc) { 1311 case AArch64::LD2LN_WB_B_fixed: case AArch64::LD2LN_WB_B_register: 1312 TransferBytes = 2; break; 1313 case AArch64::LD2LN_WB_H_fixed: case AArch64::LD2LN_WB_H_register: 1314 TransferBytes = 4; break; 1315 case AArch64::LD2LN_WB_S_fixed: case AArch64::LD2LN_WB_S_register: 1316 TransferBytes = 8; break; 1317 case AArch64::LD2LN_WB_D_fixed: case AArch64::LD2LN_WB_D_register: 1318 TransferBytes = 16; break; 1319 } 1320 IsLoad = true; 1321 NumVecs = 2; 1322 break; 1323 } 1324 1325 case AArch64::LD3LN_WB_B_fixed: case AArch64::LD3LN_WB_B_register: 1326 case AArch64::LD3LN_WB_H_fixed: case AArch64::LD3LN_WB_H_register: 1327 case AArch64::LD3LN_WB_S_fixed: case AArch64::LD3LN_WB_S_register: 1328 case AArch64::LD3LN_WB_D_fixed: case AArch64::LD3LN_WB_D_register: { 1329 switch (Opc) { 1330 case AArch64::LD3LN_WB_B_fixed: case AArch64::LD3LN_WB_B_register: 1331 TransferBytes = 3; break; 1332 case AArch64::LD3LN_WB_H_fixed: case AArch64::LD3LN_WB_H_register: 1333 TransferBytes = 6; break; 1334 case AArch64::LD3LN_WB_S_fixed: case AArch64::LD3LN_WB_S_register: 1335 TransferBytes = 12; break; 1336 case AArch64::LD3LN_WB_D_fixed: case AArch64::LD3LN_WB_D_register: 1337 TransferBytes = 24; break; 1338 } 1339 IsLoad = true; 1340 NumVecs = 3; 1341 break; 1342 } 1343 1344 case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register: 1345 case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register: 1346 case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register: 1347 case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: { 1348 switch (Opc) { 1349 case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register: 1350 TransferBytes = 4; break; 1351 case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register: 1352 TransferBytes = 8; break; 1353 case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register: 1354 TransferBytes = 16; break; 1355 case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: 1356 TransferBytes = 32; break; 1357 } 1358 IsLoad = true; 1359 NumVecs = 4; 1360 break; 1361 } 1362 1363 case AArch64::ST1LN_WB_B_fixed: case AArch64::ST1LN_WB_B_register: 1364 case AArch64::ST1LN_WB_H_fixed: case AArch64::ST1LN_WB_H_register: 1365 case AArch64::ST1LN_WB_S_fixed: case AArch64::ST1LN_WB_S_register: 1366 case AArch64::ST1LN_WB_D_fixed: case AArch64::ST1LN_WB_D_register: { 1367 switch (Opc) { 1368 case AArch64::ST1LN_WB_B_fixed: case AArch64::ST1LN_WB_B_register: 1369 TransferBytes = 1; break; 1370 case AArch64::ST1LN_WB_H_fixed: case AArch64::ST1LN_WB_H_register: 1371 TransferBytes = 2; break; 1372 case AArch64::ST1LN_WB_S_fixed: case AArch64::ST1LN_WB_S_register: 1373 TransferBytes = 4; break; 1374 case AArch64::ST1LN_WB_D_fixed: case AArch64::ST1LN_WB_D_register: 1375 TransferBytes = 8; break; 1376 } 1377 NumVecs = 1; 1378 break; 1379 } 1380 1381 case AArch64::ST2LN_WB_B_fixed: case AArch64::ST2LN_WB_B_register: 1382 case AArch64::ST2LN_WB_H_fixed: case AArch64::ST2LN_WB_H_register: 1383 case AArch64::ST2LN_WB_S_fixed: case AArch64::ST2LN_WB_S_register: 1384 case AArch64::ST2LN_WB_D_fixed: case AArch64::ST2LN_WB_D_register: { 1385 switch (Opc) { 1386 case AArch64::ST2LN_WB_B_fixed: case AArch64::ST2LN_WB_B_register: 1387 TransferBytes = 2; break; 1388 case AArch64::ST2LN_WB_H_fixed: case AArch64::ST2LN_WB_H_register: 1389 TransferBytes = 4; break; 1390 case AArch64::ST2LN_WB_S_fixed: case AArch64::ST2LN_WB_S_register: 1391 TransferBytes = 8; break; 1392 case AArch64::ST2LN_WB_D_fixed: case AArch64::ST2LN_WB_D_register: 1393 TransferBytes = 16; break; 1394 } 1395 NumVecs = 2; 1396 break; 1397 } 1398 1399 case AArch64::ST3LN_WB_B_fixed: case AArch64::ST3LN_WB_B_register: 1400 case AArch64::ST3LN_WB_H_fixed: case AArch64::ST3LN_WB_H_register: 1401 case AArch64::ST3LN_WB_S_fixed: case AArch64::ST3LN_WB_S_register: 1402 case AArch64::ST3LN_WB_D_fixed: case AArch64::ST3LN_WB_D_register: { 1403 switch (Opc) { 1404 case AArch64::ST3LN_WB_B_fixed: case AArch64::ST3LN_WB_B_register: 1405 TransferBytes = 3; break; 1406 case AArch64::ST3LN_WB_H_fixed: case AArch64::ST3LN_WB_H_register: 1407 TransferBytes = 6; break; 1408 case AArch64::ST3LN_WB_S_fixed: case AArch64::ST3LN_WB_S_register: 1409 TransferBytes = 12; break; 1410 case AArch64::ST3LN_WB_D_fixed: case AArch64::ST3LN_WB_D_register: 1411 TransferBytes = 24; break; 1412 } 1413 NumVecs = 3; 1414 break; 1415 } 1416 1417 case AArch64::ST4LN_WB_B_fixed: case AArch64::ST4LN_WB_B_register: 1418 case AArch64::ST4LN_WB_H_fixed: case AArch64::ST4LN_WB_H_register: 1419 case AArch64::ST4LN_WB_S_fixed: case AArch64::ST4LN_WB_S_register: 1420 case AArch64::ST4LN_WB_D_fixed: case AArch64::ST4LN_WB_D_register: { 1421 switch (Opc) { 1422 case AArch64::ST4LN_WB_B_fixed: case AArch64::ST4LN_WB_B_register: 1423 TransferBytes = 4; break; 1424 case AArch64::ST4LN_WB_H_fixed: case AArch64::ST4LN_WB_H_register: 1425 TransferBytes = 8; break; 1426 case AArch64::ST4LN_WB_S_fixed: case AArch64::ST4LN_WB_S_register: 1427 TransferBytes = 16; break; 1428 case AArch64::ST4LN_WB_D_fixed: case AArch64::ST4LN_WB_D_register: 1429 TransferBytes = 32; break; 1430 } 1431 NumVecs = 4; 1432 break; 1433 } 1434 1435 default: 1436 return MCDisassembler::Fail; 1437 } // End of switch (Opc) 1438 1439 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 1440 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 1441 unsigned Rm = fieldFromInstruction(Insn, 16, 5); 1442 1443 // Decode post-index of load duplicate lane 1444 if (IsLoadDup) { 1445 switch (NumVecs) { 1446 case 1: 1447 Is64bitVec ? DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder) 1448 : DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 1449 break; 1450 case 2: 1451 Is64bitVec ? DecodeDPairRegisterClass(Inst, Rt, Address, Decoder) 1452 : DecodeQPairRegisterClass(Inst, Rt, Address, Decoder); 1453 break; 1454 case 3: 1455 Is64bitVec ? DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder) 1456 : DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder); 1457 break; 1458 case 4: 1459 Is64bitVec ? DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder) 1460 : DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder); 1461 } 1462 1463 // Decode write back register, which is equal to Rn. 1464 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1465 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1466 1467 if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes 1468 Inst.addOperand(MCOperand::CreateImm(TransferBytes)); 1469 else // Decode Rm 1470 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder); 1471 1472 return MCDisassembler::Success; 1473 } 1474 1475 // Decode post-index of load/store lane 1476 // Loads have a vector list as output. 1477 if (IsLoad) { 1478 switch (NumVecs) { 1479 case 1: 1480 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 1481 break; 1482 case 2: 1483 DecodeQPairRegisterClass(Inst, Rt, Address, Decoder); 1484 break; 1485 case 3: 1486 DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder); 1487 break; 1488 case 4: 1489 DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder); 1490 } 1491 } 1492 1493 // Decode write back register, which is equal to Rn. 1494 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1495 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1496 1497 if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes 1498 Inst.addOperand(MCOperand::CreateImm(TransferBytes)); 1499 else // Decode Rm 1500 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder); 1501 1502 // Decode the source vector list. 1503 switch (NumVecs) { 1504 case 1: 1505 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 1506 break; 1507 case 2: 1508 DecodeQPairRegisterClass(Inst, Rt, Address, Decoder); 1509 break; 1510 case 3: 1511 DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder); 1512 break; 1513 case 4: 1514 DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder); 1515 } 1516 1517 // Decode lane 1518 unsigned Q = fieldFromInstruction(Insn, 30, 1); 1519 unsigned S = fieldFromInstruction(Insn, 10, 3); 1520 unsigned lane = 0; 1521 // Calculate the number of lanes by number of vectors and transferred bytes. 1522 // NumLanes = 16 bytes / bytes of each lane 1523 unsigned NumLanes = 16 / (TransferBytes / NumVecs); 1524 switch (NumLanes) { 1525 case 16: // A vector has 16 lanes, each lane is 1 bytes. 1526 lane = (Q << 3) | S; 1527 break; 1528 case 8: 1529 lane = (Q << 2) | (S >> 1); 1530 break; 1531 case 4: 1532 lane = (Q << 1) | (S >> 2); 1533 break; 1534 case 2: 1535 lane = Q; 1536 break; 1537 } 1538 Inst.addOperand(MCOperand::CreateImm(lane)); 1539 1540 return MCDisassembler::Success; 1541} 1542 1543static DecodeStatus DecodeSHLLInstruction(MCInst &Inst, unsigned Insn, 1544 uint64_t Address, 1545 const void *Decoder) { 1546 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 1547 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 1548 unsigned size = fieldFromInstruction(Insn, 22, 2); 1549 unsigned Q = fieldFromInstruction(Insn, 30, 1); 1550 1551 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 1552 1553 if(Q) 1554 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 1555 else 1556 DecodeFPR64RegisterClass(Inst, Rn, Address, Decoder); 1557 1558 switch (size) { 1559 case 0: 1560 Inst.addOperand(MCOperand::CreateImm(8)); 1561 break; 1562 case 1: 1563 Inst.addOperand(MCOperand::CreateImm(16)); 1564 break; 1565 case 2: 1566 Inst.addOperand(MCOperand::CreateImm(32)); 1567 break; 1568 default : 1569 return MCDisassembler::Fail; 1570 } 1571 return MCDisassembler::Success; 1572} 1573 1574