AArch64Disassembler.cpp revision 36c7806f4eacd676932ba630246f88e0e37b1cd4
1//===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the functions necessary to decode AArch64 instruction 11// bitpatterns into MCInsts (with the help of TableGenerated information from 12// the instruction definitions). 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "arm-disassembler" 17 18#include "AArch64.h" 19#include "AArch64RegisterInfo.h" 20#include "AArch64Subtarget.h" 21#include "Utils/AArch64BaseInfo.h" 22#include "llvm/MC/MCInst.h" 23#include "llvm/MC/MCInstrDesc.h" 24#include "llvm/MC/MCExpr.h" 25#include "llvm/MC/MCContext.h" 26#include "llvm/MC/MCDisassembler.h" 27#include "llvm/MC/MCFixedLenDisassembler.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/MemoryObject.h" 30#include "llvm/Support/ErrorHandling.h" 31#include "llvm/Support/TargetRegistry.h" 32#include "llvm/Support/raw_ostream.h" 33 34using namespace llvm; 35 36typedef MCDisassembler::DecodeStatus DecodeStatus; 37 38namespace { 39/// AArch64 disassembler for all AArch64 platforms. 40class AArch64Disassembler : public MCDisassembler { 41 OwningPtr<const MCRegisterInfo> RegInfo; 42public: 43 /// Initializes the disassembler. 44 /// 45 AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) 46 : MCDisassembler(STI), RegInfo(Info) { 47 } 48 49 ~AArch64Disassembler() {} 50 51 /// See MCDisassembler. 52 DecodeStatus getInstruction(MCInst &instr, 53 uint64_t &size, 54 const MemoryObject ®ion, 55 uint64_t address, 56 raw_ostream &vStream, 57 raw_ostream &cStream) const; 58 59 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); } 60}; 61 62} 63 64// Forward-declarations used in the auto-generated files. 65static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 66 uint64_t Address, const void *Decoder); 67static DecodeStatus 68DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 69 uint64_t Address, const void *Decoder); 70 71static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 72 uint64_t Address, const void *Decoder); 73static DecodeStatus 74DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 75 uint64_t Address, const void *Decoder); 76 77static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 78 uint64_t Address, const void *Decoder); 79static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 80 uint64_t Address, const void *Decoder); 81static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 82 uint64_t Address, const void *Decoder); 83static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 84 uint64_t Address, const void *Decoder); 85static DecodeStatus DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 86 uint64_t Address, const void *Decoder); 87static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, 88 unsigned RegNo, uint64_t Address, 89 const void *Decoder); 90static DecodeStatus DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, 91 unsigned RegNo, uint64_t Address, 92 const void *Decoder); 93 94static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst, 95 unsigned RegNo, 96 uint64_t Address, 97 const void *Decoder); 98 99static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 100 uint64_t Address, 101 const void *Decoder); 102static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 103 uint64_t Address, 104 const void *Decoder); 105static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst, 106 unsigned RegNo, uint64_t Address, 107 const void *Decoder); 108static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst, 109 unsigned RegNo, uint64_t Address, 110 const void *Decoder); 111static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, 113 const void *Decoder); 114static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 115 uint64_t Address, 116 const void *Decoder); 117 118static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst, 119 unsigned OptionHiS, 120 uint64_t Address, 121 const void *Decoder); 122 123 124static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst, 125 unsigned Imm6Bits, 126 uint64_t Address, 127 const void *Decoder); 128 129static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, 130 unsigned Imm6Bits, 131 uint64_t Address, 132 const void *Decoder); 133 134static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, 135 unsigned RmBits, 136 uint64_t Address, 137 const void *Decoder); 138 139static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val, 140 uint64_t Address, const void *Decoder); 141static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val, 142 uint64_t Address, 143 const void *Decoder); 144static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val, 145 uint64_t Address, 146 const void *Decoder); 147static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val, 148 uint64_t Address, 149 const void *Decoder); 150 151static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val, 152 uint64_t Address, const void *Decoder); 153static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val, 154 uint64_t Address, 155 const void *Decoder); 156static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val, 157 uint64_t Address, 158 const void *Decoder); 159static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val, 160 uint64_t Address, 161 const void *Decoder); 162 163template<int RegWidth> 164static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, 165 unsigned FullImm, 166 uint64_t Address, 167 const void *Decoder); 168 169template<int RegWidth> 170static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst, 171 unsigned Bits, 172 uint64_t Address, 173 const void *Decoder); 174 175static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst, 176 unsigned ShiftAmount, 177 uint64_t Address, 178 const void *Decoder); 179template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf> 180static DecodeStatus 181DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, 182 uint64_t Address, const void *Decoder); 183 184static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst, 185 unsigned ShiftAmount, 186 uint64_t Address, 187 const void *Decoder); 188static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, 189 uint64_t Address, 190 const void *Decoder); 191 192static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 193 uint64_t Address, 194 const void *Decoder); 195 196static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst, 197 unsigned Insn, 198 uint64_t Address, 199 const void *Decoder); 200 201static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, 202 unsigned Val, 203 uint64_t Address, 204 const void *Decoder); 205 206template<typename SomeNamedImmMapper> 207static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst, 208 unsigned Val, 209 uint64_t Address, 210 const void *Decoder); 211 212static DecodeStatus 213DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper, 214 llvm::MCInst &Inst, unsigned Val, 215 uint64_t Address, const void *Decoder); 216 217static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst, 218 unsigned Val, 219 uint64_t Address, 220 const void *Decoder); 221 222static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst, 223 unsigned Val, 224 uint64_t Address, 225 const void *Decoder); 226 227 228static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst, 229 unsigned Val, 230 uint64_t Address, 231 const void *Decoder); 232 233static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Val, 234 uint64_t Address, 235 const void *Decoder); 236 237static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn, 238 uint64_t Address, 239 const void *Decoder); 240 241static bool Check(DecodeStatus &Out, DecodeStatus In); 242 243#include "AArch64GenDisassemblerTables.inc" 244#include "AArch64GenInstrInfo.inc" 245 246static bool Check(DecodeStatus &Out, DecodeStatus In) { 247 switch (In) { 248 case MCDisassembler::Success: 249 // Out stays the same. 250 return true; 251 case MCDisassembler::SoftFail: 252 Out = In; 253 return true; 254 case MCDisassembler::Fail: 255 Out = In; 256 return false; 257 } 258 llvm_unreachable("Invalid DecodeStatus!"); 259} 260 261DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 262 const MemoryObject &Region, 263 uint64_t Address, 264 raw_ostream &os, 265 raw_ostream &cs) const { 266 CommentStream = &cs; 267 268 uint8_t bytes[4]; 269 270 // We want to read exactly 4 bytes of data. 271 if (Region.readBytes(Address, 4, bytes) == -1) { 272 Size = 0; 273 return MCDisassembler::Fail; 274 } 275 276 // Encoded as a small-endian 32-bit word in the stream. 277 uint32_t insn = (bytes[3] << 24) | 278 (bytes[2] << 16) | 279 (bytes[1] << 8) | 280 (bytes[0] << 0); 281 282 // Calling the auto-generated decoder function. 283 DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address, 284 this, STI); 285 if (result != MCDisassembler::Fail) { 286 Size = 4; 287 return result; 288 } 289 290 MI.clear(); 291 Size = 0; 292 return MCDisassembler::Fail; 293} 294 295static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { 296 const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D); 297 return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo); 298} 299 300static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 301 uint64_t Address, const void *Decoder) { 302 if (RegNo > 31) 303 return MCDisassembler::Fail; 304 305 uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo); 306 Inst.addOperand(MCOperand::CreateReg(Register)); 307 return MCDisassembler::Success; 308} 309 310static DecodeStatus 311DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 312 uint64_t Address, const void *Decoder) { 313 if (RegNo > 31) 314 return MCDisassembler::Fail; 315 316 uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo); 317 Inst.addOperand(MCOperand::CreateReg(Register)); 318 return MCDisassembler::Success; 319} 320 321static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 322 uint64_t Address, 323 const void *Decoder) { 324 if (RegNo > 31) 325 return MCDisassembler::Fail; 326 327 uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo); 328 Inst.addOperand(MCOperand::CreateReg(Register)); 329 return MCDisassembler::Success; 330} 331 332static DecodeStatus 333DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 334 uint64_t Address, const void *Decoder) { 335 if (RegNo > 31) 336 return MCDisassembler::Fail; 337 338 uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo); 339 Inst.addOperand(MCOperand::CreateReg(Register)); 340 return MCDisassembler::Success; 341} 342 343static DecodeStatus 344DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 345 uint64_t Address, const void *Decoder) { 346 if (RegNo > 31) 347 return MCDisassembler::Fail; 348 349 uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo); 350 Inst.addOperand(MCOperand::CreateReg(Register)); 351 return MCDisassembler::Success; 352} 353 354static DecodeStatus 355DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 356 uint64_t Address, const void *Decoder) { 357 if (RegNo > 31) 358 return MCDisassembler::Fail; 359 360 uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo); 361 Inst.addOperand(MCOperand::CreateReg(Register)); 362 return MCDisassembler::Success; 363} 364 365 366static DecodeStatus 367DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 368 uint64_t Address, const void *Decoder) { 369 if (RegNo > 31) 370 return MCDisassembler::Fail; 371 372 uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo); 373 Inst.addOperand(MCOperand::CreateReg(Register)); 374 return MCDisassembler::Success; 375} 376 377static DecodeStatus 378DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 379 uint64_t Address, const void *Decoder) { 380 if (RegNo > 31) 381 return MCDisassembler::Fail; 382 383 uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo); 384 Inst.addOperand(MCOperand::CreateReg(Register)); 385 return MCDisassembler::Success; 386} 387 388static DecodeStatus 389DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 390 uint64_t Address, const void *Decoder) { 391 if (RegNo > 15) 392 return MCDisassembler::Fail; 393 394 return DecodeFPR64RegisterClass(Inst, RegNo, Address, Decoder); 395} 396 397static DecodeStatus 398DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 399 uint64_t Address, const void *Decoder) { 400 if (RegNo > 31) 401 return MCDisassembler::Fail; 402 403 uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo); 404 Inst.addOperand(MCOperand::CreateReg(Register)); 405 return MCDisassembler::Success; 406} 407 408static DecodeStatus 409DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 410 uint64_t Address, const void *Decoder) { 411 if (RegNo > 15) 412 return MCDisassembler::Fail; 413 414 return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder); 415} 416 417static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst, 418 unsigned RegNo, 419 uint64_t Address, 420 const void *Decoder) { 421 if (RegNo > 30) 422 return MCDisassembler::Fail; 423 424 uint16_t Register = getReg(Decoder, AArch64::GPR64noxzrRegClassID, RegNo); 425 Inst.addOperand(MCOperand::CreateReg(Register)); 426 return MCDisassembler::Success; 427} 428 429static DecodeStatus DecodeRegisterClassByID(llvm::MCInst &Inst, unsigned RegNo, 430 unsigned RegID, 431 const void *Decoder) { 432 if (RegNo > 31) 433 return MCDisassembler::Fail; 434 435 uint16_t Register = getReg(Decoder, RegID, RegNo); 436 Inst.addOperand(MCOperand::CreateReg(Register)); 437 return MCDisassembler::Success; 438} 439 440static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 441 uint64_t Address, 442 const void *Decoder) { 443 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DPairRegClassID, 444 Decoder); 445} 446 447static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 448 uint64_t Address, 449 const void *Decoder) { 450 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QPairRegClassID, 451 Decoder); 452} 453 454static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst, 455 unsigned RegNo, uint64_t Address, 456 const void *Decoder) { 457 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DTripleRegClassID, 458 Decoder); 459} 460 461static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst, 462 unsigned RegNo, uint64_t Address, 463 const void *Decoder) { 464 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QTripleRegClassID, 465 Decoder); 466} 467 468static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 469 uint64_t Address, 470 const void *Decoder) { 471 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DQuadRegClassID, 472 Decoder); 473} 474 475static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 476 uint64_t Address, 477 const void *Decoder) { 478 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QQuadRegClassID, 479 Decoder); 480} 481 482static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst, 483 unsigned OptionHiS, 484 uint64_t Address, 485 const void *Decoder) { 486 // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1}, 487 // S}. Hence we want to check bit 1. 488 if (!(OptionHiS & 2)) 489 return MCDisassembler::Fail; 490 491 Inst.addOperand(MCOperand::CreateImm(OptionHiS)); 492 return MCDisassembler::Success; 493} 494 495static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst, 496 unsigned Imm6Bits, 497 uint64_t Address, 498 const void *Decoder) { 499 // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be 500 // between 0 and 31. 501 if (Imm6Bits > 31) 502 return MCDisassembler::Fail; 503 504 Inst.addOperand(MCOperand::CreateImm(Imm6Bits)); 505 return MCDisassembler::Success; 506} 507 508static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, 509 unsigned Imm6Bits, 510 uint64_t Address, 511 const void *Decoder) { 512 // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32. 513 if (Imm6Bits < 32) 514 return MCDisassembler::Fail; 515 516 Inst.addOperand(MCOperand::CreateImm(Imm6Bits)); 517 return MCDisassembler::Success; 518} 519 520static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, 521 unsigned RmBits, 522 uint64_t Address, 523 const void *Decoder) { 524 // Any bits are valid in the instruction (they're architecturally ignored), 525 // but a code generator should insert 0. 526 Inst.addOperand(MCOperand::CreateImm(0)); 527 return MCDisassembler::Success; 528} 529 530static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val, 531 uint64_t Address, 532 const void *Decoder) { 533 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 534 return MCDisassembler::Success; 535} 536 537static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val, 538 uint64_t Address, 539 const void *Decoder) { 540 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 541 return MCDisassembler::Success; 542} 543 544static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val, 545 uint64_t Address, 546 const void *Decoder) { 547 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 548 return MCDisassembler::Success; 549} 550 551static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val, 552 uint64_t Address, 553 const void *Decoder) { 554 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 555 return MCDisassembler::Success; 556} 557 558static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val, 559 uint64_t Address, 560 const void *Decoder) { 561 if (Val > 7) 562 return MCDisassembler::Fail; 563 564 Inst.addOperand(MCOperand::CreateImm(Val)); 565 return MCDisassembler::Success; 566} 567 568static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val, 569 uint64_t Address, 570 const void *Decoder) { 571 if (Val > 15) 572 return MCDisassembler::Fail; 573 574 Inst.addOperand(MCOperand::CreateImm(Val)); 575 return MCDisassembler::Success; 576} 577 578static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val, 579 uint64_t Address, 580 const void *Decoder) { 581 if (Val > 31) 582 return MCDisassembler::Fail; 583 584 Inst.addOperand(MCOperand::CreateImm(Val)); 585 return MCDisassembler::Success; 586} 587 588static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val, 589 uint64_t Address, 590 const void *Decoder) { 591 if (Val > 63) 592 return MCDisassembler::Fail; 593 594 Inst.addOperand(MCOperand::CreateImm(Val)); 595 return MCDisassembler::Success; 596} 597 598template<int RegWidth> 599static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, 600 unsigned FullImm, 601 uint64_t Address, 602 const void *Decoder) { 603 unsigned Imm16 = FullImm & 0xffff; 604 unsigned Shift = FullImm >> 16; 605 606 if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail; 607 608 Inst.addOperand(MCOperand::CreateImm(Imm16)); 609 Inst.addOperand(MCOperand::CreateImm(Shift)); 610 return MCDisassembler::Success; 611} 612 613template<int RegWidth> 614static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst, 615 unsigned Bits, 616 uint64_t Address, 617 const void *Decoder) { 618 uint64_t Imm; 619 if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm)) 620 return MCDisassembler::Fail; 621 622 Inst.addOperand(MCOperand::CreateImm(Bits)); 623 return MCDisassembler::Success; 624} 625 626 627static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst, 628 unsigned ShiftAmount, 629 uint64_t Address, 630 const void *Decoder) { 631 // Only values 0-4 are valid for this 3-bit field 632 if (ShiftAmount > 4) 633 return MCDisassembler::Fail; 634 635 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 636 return MCDisassembler::Success; 637} 638 639static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst, 640 unsigned ShiftAmount, 641 uint64_t Address, 642 const void *Decoder) { 643 // Only values below 32 are valid for a 32-bit register 644 if (ShiftAmount > 31) 645 return MCDisassembler::Fail; 646 647 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 648 return MCDisassembler::Success; 649} 650 651static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, 652 uint64_t Address, 653 const void *Decoder) { 654 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 655 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 656 unsigned ImmS = fieldFromInstruction(Insn, 10, 6); 657 unsigned ImmR = fieldFromInstruction(Insn, 16, 6); 658 unsigned SF = fieldFromInstruction(Insn, 31, 1); 659 660 // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise 661 // out assertions that it thinks should never be hit. 662 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc; 663 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2); 664 665 if (!SF) { 666 // ImmR and ImmS must be between 0 and 31 for 32-bit instructions. 667 if (ImmR > 31 || ImmS > 31) 668 return MCDisassembler::Fail; 669 } 670 671 if (SF) { 672 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 673 // BFM MCInsts use Rd as a source too. 674 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 675 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 676 } else { 677 DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); 678 // BFM MCInsts use Rd as a source too. 679 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); 680 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder); 681 } 682 683 // ASR and LSR have more specific patterns so they won't get here: 684 assert(!(ImmS == 31 && !SF && Opc != BFM) 685 && "shift should have used auto decode"); 686 assert(!(ImmS == 63 && SF && Opc != BFM) 687 && "shift should have used auto decode"); 688 689 // Extension instructions similarly: 690 if (Opc == SBFM && ImmR == 0) { 691 assert((ImmS != 7 && ImmS != 15) && "extension got here"); 692 assert((ImmS != 31 || SF == 0) && "extension got here"); 693 } else if (Opc == UBFM && ImmR == 0) { 694 assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here"); 695 } 696 697 if (Opc == UBFM) { 698 // It might be a LSL instruction, which actually takes the shift amount 699 // itself as an MCInst operand. 700 if (SF && (ImmS + 1) % 64 == ImmR) { 701 Inst.setOpcode(AArch64::LSLxxi); 702 Inst.addOperand(MCOperand::CreateImm(63 - ImmS)); 703 return MCDisassembler::Success; 704 } else if (!SF && (ImmS + 1) % 32 == ImmR) { 705 Inst.setOpcode(AArch64::LSLwwi); 706 Inst.addOperand(MCOperand::CreateImm(31 - ImmS)); 707 return MCDisassembler::Success; 708 } 709 } 710 711 // Otherwise it's definitely either an extract or an insert depending on which 712 // of ImmR or ImmS is larger. 713 unsigned ExtractOp, InsertOp; 714 switch (Opc) { 715 default: llvm_unreachable("unexpected instruction trying to decode bitfield"); 716 case SBFM: 717 ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii; 718 InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii; 719 break; 720 case BFM: 721 ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii; 722 InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii; 723 break; 724 case UBFM: 725 ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii; 726 InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii; 727 break; 728 } 729 730 // Otherwise it's a boring insert or extract 731 Inst.addOperand(MCOperand::CreateImm(ImmR)); 732 Inst.addOperand(MCOperand::CreateImm(ImmS)); 733 734 735 if (ImmS < ImmR) 736 Inst.setOpcode(InsertOp); 737 else 738 Inst.setOpcode(ExtractOp); 739 740 return MCDisassembler::Success; 741} 742 743static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, 744 uint64_t Address, 745 const void *Decoder) { 746 // This decoder exists to add the dummy Lane operand to the MCInst, which must 747 // be 1 in assembly but has no other real manifestation. 748 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 749 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 750 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 751 752 if (IsToVec) { 753 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 754 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 755 } else { 756 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 757 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 758 } 759 760 // Add the lane 761 Inst.addOperand(MCOperand::CreateImm(1)); 762 763 return MCDisassembler::Success; 764} 765 766 767static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst, 768 unsigned Insn, 769 uint64_t Address, 770 const void *Decoder) { 771 DecodeStatus Result = MCDisassembler::Success; 772 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 773 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 774 unsigned Rt2 = fieldFromInstruction(Insn, 10, 5); 775 unsigned SImm7 = fieldFromInstruction(Insn, 15, 7); 776 unsigned L = fieldFromInstruction(Insn, 22, 1); 777 unsigned V = fieldFromInstruction(Insn, 26, 1); 778 unsigned Opc = fieldFromInstruction(Insn, 30, 2); 779 780 // Not an official name, but it turns out that bit 23 distinguishes indexed 781 // from non-indexed operations. 782 unsigned Indexed = fieldFromInstruction(Insn, 23, 1); 783 784 if (Indexed && L == 0) { 785 // The MCInst for an indexed store has an out operand and 4 ins: 786 // Rn_wb, Rt, Rt2, Rn, Imm 787 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 788 } 789 790 // You shouldn't load to the same register twice in an instruction... 791 if (L && Rt == Rt2) 792 Result = MCDisassembler::SoftFail; 793 794 // ... or do any operation that writes-back to a transfer register. But note 795 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 796 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 797 Result = MCDisassembler::SoftFail; 798 799 // Exactly how we decode the MCInst's registers depends on the Opc and V 800 // fields of the instruction. These also obviously determine the size of the 801 // operation so we can fill in that information while we're at it. 802 if (V) { 803 // The instruction operates on the FP/SIMD registers 804 switch (Opc) { 805 default: return MCDisassembler::Fail; 806 case 0: 807 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder); 808 DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder); 809 break; 810 case 1: 811 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 812 DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder); 813 break; 814 case 2: 815 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 816 DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder); 817 break; 818 } 819 } else { 820 switch (Opc) { 821 default: return MCDisassembler::Fail; 822 case 0: 823 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder); 824 DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder); 825 break; 826 case 1: 827 assert(L && "unexpected \"store signed\" attempt"); 828 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 829 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder); 830 break; 831 case 2: 832 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 833 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder); 834 break; 835 } 836 } 837 838 if (Indexed && L == 1) { 839 // The MCInst for an indexed load has 3 out operands and an 3 ins: 840 // Rt, Rt2, Rn_wb, Rt2, Rn, Imm 841 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 842 } 843 844 845 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 846 Inst.addOperand(MCOperand::CreateImm(SImm7)); 847 848 return Result; 849} 850 851static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, 852 uint32_t Val, 853 uint64_t Address, 854 const void *Decoder) { 855 unsigned Rt = fieldFromInstruction(Val, 0, 5); 856 unsigned Rn = fieldFromInstruction(Val, 5, 5); 857 unsigned Rt2 = fieldFromInstruction(Val, 10, 5); 858 unsigned MemSize = fieldFromInstruction(Val, 30, 2); 859 860 DecodeStatus S = MCDisassembler::Success; 861 if (Rt == Rt2) S = MCDisassembler::SoftFail; 862 863 switch (MemSize) { 864 case 2: 865 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder))) 866 return MCDisassembler::Fail; 867 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder))) 868 return MCDisassembler::Fail; 869 break; 870 case 3: 871 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder))) 872 return MCDisassembler::Fail; 873 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder))) 874 return MCDisassembler::Fail; 875 break; 876 default: 877 llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction"); 878 } 879 880 if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder))) 881 return MCDisassembler::Fail; 882 883 return S; 884} 885 886template<typename SomeNamedImmMapper> 887static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst, 888 unsigned Val, 889 uint64_t Address, 890 const void *Decoder) { 891 SomeNamedImmMapper Mapper; 892 bool ValidNamed; 893 Mapper.toString(Val, ValidNamed); 894 if (ValidNamed || Mapper.validImm(Val)) { 895 Inst.addOperand(MCOperand::CreateImm(Val)); 896 return MCDisassembler::Success; 897 } 898 899 return MCDisassembler::Fail; 900} 901 902static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper, 903 llvm::MCInst &Inst, 904 unsigned Val, 905 uint64_t Address, 906 const void *Decoder) { 907 bool ValidNamed; 908 Mapper.toString(Val, ValidNamed); 909 910 Inst.addOperand(MCOperand::CreateImm(Val)); 911 912 return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail; 913} 914 915static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst, 916 unsigned Val, 917 uint64_t Address, 918 const void *Decoder) { 919 return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address, 920 Decoder); 921} 922 923static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst, 924 unsigned Val, 925 uint64_t Address, 926 const void *Decoder) { 927 return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address, 928 Decoder); 929} 930 931static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst, 932 unsigned Insn, 933 uint64_t Address, 934 const void *Decoder) { 935 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 936 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 937 unsigned Imm9 = fieldFromInstruction(Insn, 12, 9); 938 939 unsigned Opc = fieldFromInstruction(Insn, 22, 2); 940 unsigned V = fieldFromInstruction(Insn, 26, 1); 941 unsigned Size = fieldFromInstruction(Insn, 30, 2); 942 943 if (Opc == 0 || (V == 1 && Opc == 2)) { 944 // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm 945 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 946 } 947 948 if (V == 0 && (Opc == 2 || Size == 3)) { 949 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); 950 } else if (V == 0) { 951 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder); 952 } else if (V == 1 && (Opc & 2)) { 953 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 954 } else { 955 switch (Size) { 956 case 0: 957 DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder); 958 break; 959 case 1: 960 DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder); 961 break; 962 case 2: 963 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder); 964 break; 965 case 3: 966 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 967 break; 968 } 969 } 970 971 if (Opc != 0 && (V != 1 || Opc != 2)) { 972 // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm 973 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 974 } 975 976 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 977 978 Inst.addOperand(MCOperand::CreateImm(Imm9)); 979 980 // N.b. The official documentation says undpredictable if Rt == Rn, but this 981 // takes place at the architectural rather than encoding level: 982 // 983 // "STR xzr, [sp], #4" is perfectly valid. 984 if (V == 0 && Rt == Rn && Rn != 31) 985 return MCDisassembler::SoftFail; 986 else 987 return MCDisassembler::Success; 988} 989 990static MCDisassembler *createAArch64Disassembler(const Target &T, 991 const MCSubtargetInfo &STI) { 992 return new AArch64Disassembler(STI, T.createMCRegInfo("")); 993} 994 995extern "C" void LLVMInitializeAArch64Disassembler() { 996 TargetRegistry::RegisterMCDisassembler(TheAArch64Target, 997 createAArch64Disassembler); 998} 999 1000template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf> 1001static DecodeStatus 1002DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, 1003 uint64_t Address, const void *Decoder) { 1004 bool IsLSL = false; 1005 if (Ext == A64SE::LSL) 1006 IsLSL = true; 1007 else if (Ext != A64SE::MSL) 1008 return MCDisassembler::Fail; 1009 1010 // MSL and LSLH accepts encoded shift amount 0 or 1. 1011 if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1) 1012 return MCDisassembler::Fail; 1013 1014 // LSL accepts encoded shift amount 0, 1, 2 or 3. 1015 if (IsLSL && ShiftAmount > 3) 1016 return MCDisassembler::Fail; 1017 1018 Inst.addOperand(MCOperand::CreateImm(ShiftAmount)); 1019 return MCDisassembler::Success; 1020} 1021 1022// Decode post-index vector load/store instructions. 1023// This is necessary as we need to decode Rm: if Rm == 0b11111, the last 1024// operand is an immediate equal the the length of vector list in bytes, 1025// or Rm is decoded to a GPR64noxzr register. 1026static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Insn, 1027 uint64_t Address, 1028 const void *Decoder) { 1029 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 1030 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 1031 unsigned Rm = fieldFromInstruction(Insn, 16, 5); 1032 unsigned Opcode = fieldFromInstruction(Insn, 12, 4); 1033 unsigned IsLoad = fieldFromInstruction(Insn, 22, 1); 1034 // 0 for 64bit vector list, 1 for 128bit vector list 1035 unsigned Is128BitVec = fieldFromInstruction(Insn, 30, 1); 1036 1037 unsigned NumVecs; 1038 switch (Opcode) { 1039 case 0: // ld4/st4 1040 case 2: // ld1/st1 with 4 vectors 1041 NumVecs = 4; break; 1042 case 4: // ld3/st3 1043 case 6: // ld1/st1 with 3 vectors 1044 NumVecs = 3; break; 1045 case 7: // ld1/st1 with 1 vector 1046 NumVecs = 1; break; 1047 case 8: // ld2/st2 1048 case 10: // ld1/st1 with 2 vectors 1049 NumVecs = 2; break; 1050 default: 1051 llvm_unreachable("Invalid opcode for post-index load/store instructions"); 1052 } 1053 1054 // Decode vector list of 1/2/3/4 vectors for load instructions. 1055 if (IsLoad) { 1056 switch (NumVecs) { 1057 case 1: 1058 Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder) 1059 : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 1060 break; 1061 case 2: 1062 Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder) 1063 : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder); 1064 break; 1065 case 3: 1066 Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder) 1067 : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder); 1068 break; 1069 case 4: 1070 Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder) 1071 : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder); 1072 break; 1073 } 1074 } 1075 1076 // Decode write back register, which is equal to Rn. 1077 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1078 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1079 1080 if (Rm == 31) // If Rm is 0x11111, add the vector list length in byte 1081 Inst.addOperand(MCOperand::CreateImm(NumVecs * (Is128BitVec ? 16 : 8))); 1082 else // Decode Rm 1083 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder); 1084 1085 // Decode vector list of 1/2/3/4 vectors for load instructions. 1086 if (!IsLoad) { 1087 switch (NumVecs) { 1088 case 1: 1089 Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder) 1090 : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder); 1091 break; 1092 case 2: 1093 Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder) 1094 : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder); 1095 break; 1096 case 3: 1097 Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder) 1098 : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder); 1099 break; 1100 case 4: 1101 Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder) 1102 : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder); 1103 break; 1104 } 1105 } 1106 1107 return MCDisassembler::Success; 1108} 1109 1110// Decode post-index vector load/store lane instructions. 1111// This is necessary as we need to decode Rm: if Rm == 0b11111, the last 1112// operand is an immediate equal the the length of the changed bytes, 1113// or Rm is decoded to a GPR64noxzr register. 1114static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn, 1115 uint64_t Address, 1116 const void *Decoder) { 1117 bool Is64bitVec = false; 1118 bool IsLoadDup = false; 1119 bool IsLoad = false; 1120 unsigned TransferBytes = 0; // The total number of bytes transferred. 1121 unsigned NumVecs = 0; 1122 unsigned Opc = Inst.getOpcode(); 1123 switch (Opc) { 1124 case AArch64::LD1R_WB_8B_fixed: case AArch64::LD1R_WB_8B_register: 1125 case AArch64::LD1R_WB_4H_fixed: case AArch64::LD1R_WB_4H_register: 1126 case AArch64::LD1R_WB_2S_fixed: case AArch64::LD1R_WB_2S_register: 1127 case AArch64::LD1R_WB_1D_fixed: case AArch64::LD1R_WB_1D_register: { 1128 switch (Opc) { 1129 case AArch64::LD1R_WB_8B_fixed: case AArch64::LD1R_WB_8B_register: 1130 TransferBytes = 1; break; 1131 case AArch64::LD1R_WB_4H_fixed: case AArch64::LD1R_WB_4H_register: 1132 TransferBytes = 2; break; 1133 case AArch64::LD1R_WB_2S_fixed: case AArch64::LD1R_WB_2S_register: 1134 TransferBytes = 4; break; 1135 case AArch64::LD1R_WB_1D_fixed: case AArch64::LD1R_WB_1D_register: 1136 TransferBytes = 8; break; 1137 } 1138 Is64bitVec = true; 1139 IsLoadDup = true; 1140 NumVecs = 1; 1141 break; 1142 } 1143 1144 case AArch64::LD1R_WB_16B_fixed: case AArch64::LD1R_WB_16B_register: 1145 case AArch64::LD1R_WB_8H_fixed: case AArch64::LD1R_WB_8H_register: 1146 case AArch64::LD1R_WB_4S_fixed: case AArch64::LD1R_WB_4S_register: 1147 case AArch64::LD1R_WB_2D_fixed: case AArch64::LD1R_WB_2D_register: { 1148 switch (Opc) { 1149 case AArch64::LD1R_WB_16B_fixed: case AArch64::LD1R_WB_16B_register: 1150 TransferBytes = 1; break; 1151 case AArch64::LD1R_WB_8H_fixed: case AArch64::LD1R_WB_8H_register: 1152 TransferBytes = 2; break; 1153 case AArch64::LD1R_WB_4S_fixed: case AArch64::LD1R_WB_4S_register: 1154 TransferBytes = 4; break; 1155 case AArch64::LD1R_WB_2D_fixed: case AArch64::LD1R_WB_2D_register: 1156 TransferBytes = 8; break; 1157 } 1158 IsLoadDup = true; 1159 NumVecs = 1; 1160 break; 1161 } 1162 1163 case AArch64::LD2R_WB_8B_fixed: case AArch64::LD2R_WB_8B_register: 1164 case AArch64::LD2R_WB_4H_fixed: case AArch64::LD2R_WB_4H_register: 1165 case AArch64::LD2R_WB_2S_fixed: case AArch64::LD2R_WB_2S_register: 1166 case AArch64::LD2R_WB_1D_fixed: case AArch64::LD2R_WB_1D_register: { 1167 switch (Opc) { 1168 case AArch64::LD2R_WB_8B_fixed: case AArch64::LD2R_WB_8B_register: 1169 TransferBytes = 2; break; 1170 case AArch64::LD2R_WB_4H_fixed: case AArch64::LD2R_WB_4H_register: 1171 TransferBytes = 4; break; 1172 case AArch64::LD2R_WB_2S_fixed: case AArch64::LD2R_WB_2S_register: 1173 TransferBytes = 8; break; 1174 case AArch64::LD2R_WB_1D_fixed: case AArch64::LD2R_WB_1D_register: 1175 TransferBytes = 16; break; 1176 } 1177 Is64bitVec = true; 1178 IsLoadDup = true; 1179 NumVecs = 2; 1180 break; 1181 } 1182 1183 case AArch64::LD2R_WB_16B_fixed: case AArch64::LD2R_WB_16B_register: 1184 case AArch64::LD2R_WB_8H_fixed: case AArch64::LD2R_WB_8H_register: 1185 case AArch64::LD2R_WB_4S_fixed: case AArch64::LD2R_WB_4S_register: 1186 case AArch64::LD2R_WB_2D_fixed: case AArch64::LD2R_WB_2D_register: { 1187 switch (Opc) { 1188 case AArch64::LD2R_WB_16B_fixed: case AArch64::LD2R_WB_16B_register: 1189 TransferBytes = 2; break; 1190 case AArch64::LD2R_WB_8H_fixed: case AArch64::LD2R_WB_8H_register: 1191 TransferBytes = 4; break; 1192 case AArch64::LD2R_WB_4S_fixed: case AArch64::LD2R_WB_4S_register: 1193 TransferBytes = 8; break; 1194 case AArch64::LD2R_WB_2D_fixed: case AArch64::LD2R_WB_2D_register: 1195 TransferBytes = 16; break; 1196 } 1197 IsLoadDup = true; 1198 NumVecs = 2; 1199 break; 1200 } 1201 1202 case AArch64::LD3R_WB_8B_fixed: case AArch64::LD3R_WB_8B_register: 1203 case AArch64::LD3R_WB_4H_fixed: case AArch64::LD3R_WB_4H_register: 1204 case AArch64::LD3R_WB_2S_fixed: case AArch64::LD3R_WB_2S_register: 1205 case AArch64::LD3R_WB_1D_fixed: case AArch64::LD3R_WB_1D_register: { 1206 switch (Opc) { 1207 case AArch64::LD3R_WB_8B_fixed: case AArch64::LD3R_WB_8B_register: 1208 TransferBytes = 3; break; 1209 case AArch64::LD3R_WB_4H_fixed: case AArch64::LD3R_WB_4H_register: 1210 TransferBytes = 6; break; 1211 case AArch64::LD3R_WB_2S_fixed: case AArch64::LD3R_WB_2S_register: 1212 TransferBytes = 12; break; 1213 case AArch64::LD3R_WB_1D_fixed: case AArch64::LD3R_WB_1D_register: 1214 TransferBytes = 24; break; 1215 } 1216 Is64bitVec = true; 1217 IsLoadDup = true; 1218 NumVecs = 3; 1219 break; 1220 } 1221 1222 case AArch64::LD3R_WB_16B_fixed: case AArch64::LD3R_WB_16B_register: 1223 case AArch64::LD3R_WB_4S_fixed: case AArch64::LD3R_WB_8H_register: 1224 case AArch64::LD3R_WB_8H_fixed: case AArch64::LD3R_WB_4S_register: 1225 case AArch64::LD3R_WB_2D_fixed: case AArch64::LD3R_WB_2D_register: { 1226 switch (Opc) { 1227 case AArch64::LD3R_WB_16B_fixed: case AArch64::LD3R_WB_16B_register: 1228 TransferBytes = 3; break; 1229 case AArch64::LD3R_WB_8H_fixed: case AArch64::LD3R_WB_8H_register: 1230 TransferBytes = 6; break; 1231 case AArch64::LD3R_WB_4S_fixed: case AArch64::LD3R_WB_4S_register: 1232 TransferBytes = 12; break; 1233 case AArch64::LD3R_WB_2D_fixed: case AArch64::LD3R_WB_2D_register: 1234 TransferBytes = 24; break; 1235 } 1236 IsLoadDup = true; 1237 NumVecs = 3; 1238 break; 1239 } 1240 1241 case AArch64::LD4R_WB_8B_fixed: case AArch64::LD4R_WB_8B_register: 1242 case AArch64::LD4R_WB_4H_fixed: case AArch64::LD4R_WB_4H_register: 1243 case AArch64::LD4R_WB_2S_fixed: case AArch64::LD4R_WB_2S_register: 1244 case AArch64::LD4R_WB_1D_fixed: case AArch64::LD4R_WB_1D_register: { 1245 switch (Opc) { 1246 case AArch64::LD4R_WB_8B_fixed: case AArch64::LD4R_WB_8B_register: 1247 TransferBytes = 4; break; 1248 case AArch64::LD4R_WB_4H_fixed: case AArch64::LD4R_WB_4H_register: 1249 TransferBytes = 8; break; 1250 case AArch64::LD4R_WB_2S_fixed: case AArch64::LD4R_WB_2S_register: 1251 TransferBytes = 16; break; 1252 case AArch64::LD4R_WB_1D_fixed: case AArch64::LD4R_WB_1D_register: 1253 TransferBytes = 32; break; 1254 } 1255 Is64bitVec = true; 1256 IsLoadDup = true; 1257 NumVecs = 4; 1258 break; 1259 } 1260 1261 case AArch64::LD4R_WB_16B_fixed: case AArch64::LD4R_WB_16B_register: 1262 case AArch64::LD4R_WB_4S_fixed: case AArch64::LD4R_WB_8H_register: 1263 case AArch64::LD4R_WB_8H_fixed: case AArch64::LD4R_WB_4S_register: 1264 case AArch64::LD4R_WB_2D_fixed: case AArch64::LD4R_WB_2D_register: { 1265 switch (Opc) { 1266 case AArch64::LD4R_WB_16B_fixed: case AArch64::LD4R_WB_16B_register: 1267 TransferBytes = 4; break; 1268 case AArch64::LD4R_WB_8H_fixed: case AArch64::LD4R_WB_8H_register: 1269 TransferBytes = 8; break; 1270 case AArch64::LD4R_WB_4S_fixed: case AArch64::LD4R_WB_4S_register: 1271 TransferBytes = 16; break; 1272 case AArch64::LD4R_WB_2D_fixed: case AArch64::LD4R_WB_2D_register: 1273 TransferBytes = 32; break; 1274 } 1275 IsLoadDup = true; 1276 NumVecs = 4; 1277 break; 1278 } 1279 1280 case AArch64::LD1LN_WB_B_fixed: case AArch64::LD1LN_WB_B_register: 1281 case AArch64::LD1LN_WB_H_fixed: case AArch64::LD1LN_WB_H_register: 1282 case AArch64::LD1LN_WB_S_fixed: case AArch64::LD1LN_WB_S_register: 1283 case AArch64::LD1LN_WB_D_fixed: case AArch64::LD1LN_WB_D_register: { 1284 switch (Opc) { 1285 case AArch64::LD1LN_WB_B_fixed: case AArch64::LD1LN_WB_B_register: 1286 TransferBytes = 1; break; 1287 case AArch64::LD1LN_WB_H_fixed: case AArch64::LD1LN_WB_H_register: 1288 TransferBytes = 2; break; 1289 case AArch64::LD1LN_WB_S_fixed: case AArch64::LD1LN_WB_S_register: 1290 TransferBytes = 4; break; 1291 case AArch64::LD1LN_WB_D_fixed: case AArch64::LD1LN_WB_D_register: 1292 TransferBytes = 8; break; 1293 } 1294 IsLoad = true; 1295 NumVecs = 1; 1296 break; 1297 } 1298 1299 case AArch64::LD2LN_WB_B_fixed: case AArch64::LD2LN_WB_B_register: 1300 case AArch64::LD2LN_WB_H_fixed: case AArch64::LD2LN_WB_H_register: 1301 case AArch64::LD2LN_WB_S_fixed: case AArch64::LD2LN_WB_S_register: 1302 case AArch64::LD2LN_WB_D_fixed: case AArch64::LD2LN_WB_D_register: { 1303 switch (Opc) { 1304 case AArch64::LD2LN_WB_B_fixed: case AArch64::LD2LN_WB_B_register: 1305 TransferBytes = 2; break; 1306 case AArch64::LD2LN_WB_H_fixed: case AArch64::LD2LN_WB_H_register: 1307 TransferBytes = 4; break; 1308 case AArch64::LD2LN_WB_S_fixed: case AArch64::LD2LN_WB_S_register: 1309 TransferBytes = 8; break; 1310 case AArch64::LD2LN_WB_D_fixed: case AArch64::LD2LN_WB_D_register: 1311 TransferBytes = 16; break; 1312 } 1313 IsLoad = true; 1314 NumVecs = 2; 1315 break; 1316 } 1317 1318 case AArch64::LD3LN_WB_B_fixed: case AArch64::LD3LN_WB_B_register: 1319 case AArch64::LD3LN_WB_H_fixed: case AArch64::LD3LN_WB_H_register: 1320 case AArch64::LD3LN_WB_S_fixed: case AArch64::LD3LN_WB_S_register: 1321 case AArch64::LD3LN_WB_D_fixed: case AArch64::LD3LN_WB_D_register: { 1322 switch (Opc) { 1323 case AArch64::LD3LN_WB_B_fixed: case AArch64::LD3LN_WB_B_register: 1324 TransferBytes = 3; break; 1325 case AArch64::LD3LN_WB_H_fixed: case AArch64::LD3LN_WB_H_register: 1326 TransferBytes = 6; break; 1327 case AArch64::LD3LN_WB_S_fixed: case AArch64::LD3LN_WB_S_register: 1328 TransferBytes = 12; break; 1329 case AArch64::LD3LN_WB_D_fixed: case AArch64::LD3LN_WB_D_register: 1330 TransferBytes = 24; break; 1331 } 1332 IsLoad = true; 1333 NumVecs = 3; 1334 break; 1335 } 1336 1337 case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register: 1338 case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register: 1339 case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register: 1340 case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: { 1341 switch (Opc) { 1342 case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register: 1343 TransferBytes = 3; break; 1344 case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register: 1345 TransferBytes = 6; break; 1346 case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register: 1347 TransferBytes = 12; break; 1348 case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: 1349 TransferBytes = 24; break; 1350 } 1351 IsLoad = true; 1352 NumVecs = 4; 1353 break; 1354 } 1355 1356 case AArch64::ST1LN_WB_B_fixed: case AArch64::ST1LN_WB_B_register: 1357 case AArch64::ST1LN_WB_H_fixed: case AArch64::ST1LN_WB_H_register: 1358 case AArch64::ST1LN_WB_S_fixed: case AArch64::ST1LN_WB_S_register: 1359 case AArch64::ST1LN_WB_D_fixed: case AArch64::ST1LN_WB_D_register: { 1360 switch (Opc) { 1361 case AArch64::ST1LN_WB_B_fixed: case AArch64::ST1LN_WB_B_register: 1362 TransferBytes = 1; break; 1363 case AArch64::ST1LN_WB_H_fixed: case AArch64::ST1LN_WB_H_register: 1364 TransferBytes = 2; break; 1365 case AArch64::ST1LN_WB_S_fixed: case AArch64::ST1LN_WB_S_register: 1366 TransferBytes = 4; break; 1367 case AArch64::ST1LN_WB_D_fixed: case AArch64::ST1LN_WB_D_register: 1368 TransferBytes = 8; break; 1369 } 1370 NumVecs = 1; 1371 break; 1372 } 1373 1374 case AArch64::ST2LN_WB_B_fixed: case AArch64::ST2LN_WB_B_register: 1375 case AArch64::ST2LN_WB_H_fixed: case AArch64::ST2LN_WB_H_register: 1376 case AArch64::ST2LN_WB_S_fixed: case AArch64::ST2LN_WB_S_register: 1377 case AArch64::ST2LN_WB_D_fixed: case AArch64::ST2LN_WB_D_register: { 1378 switch (Opc) { 1379 case AArch64::ST2LN_WB_B_fixed: case AArch64::ST2LN_WB_B_register: 1380 TransferBytes = 2; break; 1381 case AArch64::ST2LN_WB_H_fixed: case AArch64::ST2LN_WB_H_register: 1382 TransferBytes = 4; break; 1383 case AArch64::ST2LN_WB_S_fixed: case AArch64::ST2LN_WB_S_register: 1384 TransferBytes = 8; break; 1385 case AArch64::ST2LN_WB_D_fixed: case AArch64::ST2LN_WB_D_register: 1386 TransferBytes = 16; break; 1387 } 1388 NumVecs = 2; 1389 break; 1390 } 1391 1392 case AArch64::ST3LN_WB_B_fixed: case AArch64::ST3LN_WB_B_register: 1393 case AArch64::ST3LN_WB_H_fixed: case AArch64::ST3LN_WB_H_register: 1394 case AArch64::ST3LN_WB_S_fixed: case AArch64::ST3LN_WB_S_register: 1395 case AArch64::ST3LN_WB_D_fixed: case AArch64::ST3LN_WB_D_register: { 1396 switch (Opc) { 1397 case AArch64::ST3LN_WB_B_fixed: case AArch64::ST3LN_WB_B_register: 1398 TransferBytes = 3; break; 1399 case AArch64::ST3LN_WB_H_fixed: case AArch64::ST3LN_WB_H_register: 1400 TransferBytes = 6; break; 1401 case AArch64::ST3LN_WB_S_fixed: case AArch64::ST3LN_WB_S_register: 1402 TransferBytes = 12; break; 1403 case AArch64::ST3LN_WB_D_fixed: case AArch64::ST3LN_WB_D_register: 1404 TransferBytes = 24; break; 1405 } 1406 NumVecs = 3; 1407 break; 1408 } 1409 1410 case AArch64::ST4LN_WB_B_fixed: case AArch64::ST4LN_WB_B_register: 1411 case AArch64::ST4LN_WB_H_fixed: case AArch64::ST4LN_WB_H_register: 1412 case AArch64::ST4LN_WB_S_fixed: case AArch64::ST4LN_WB_S_register: 1413 case AArch64::ST4LN_WB_D_fixed: case AArch64::ST4LN_WB_D_register: { 1414 switch (Opc) { 1415 case AArch64::ST4LN_WB_B_fixed: case AArch64::ST4LN_WB_B_register: 1416 TransferBytes = 4; break; 1417 case AArch64::ST4LN_WB_H_fixed: case AArch64::ST4LN_WB_H_register: 1418 TransferBytes = 8; break; 1419 case AArch64::ST4LN_WB_S_fixed: case AArch64::ST4LN_WB_S_register: 1420 TransferBytes = 16; break; 1421 case AArch64::ST4LN_WB_D_fixed: case AArch64::ST4LN_WB_D_register: 1422 TransferBytes = 32; break; 1423 } 1424 NumVecs = 4; 1425 break; 1426 } 1427 1428 default: 1429 return MCDisassembler::Fail; 1430 } // End of switch (Opc) 1431 1432 unsigned Rt = fieldFromInstruction(Insn, 0, 5); 1433 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 1434 unsigned Rm = fieldFromInstruction(Insn, 16, 5); 1435 1436 // Decode post-index of load duplicate lane 1437 if (IsLoadDup) { 1438 switch (NumVecs) { 1439 case 1: 1440 Is64bitVec ? DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder) 1441 : DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 1442 break; 1443 case 2: 1444 Is64bitVec ? DecodeDPairRegisterClass(Inst, Rt, Address, Decoder) 1445 : DecodeQPairRegisterClass(Inst, Rt, Address, Decoder); 1446 break; 1447 case 3: 1448 Is64bitVec ? DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder) 1449 : DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder); 1450 break; 1451 case 4: 1452 Is64bitVec ? DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder) 1453 : DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder); 1454 } 1455 1456 // Decode write back register, which is equal to Rn. 1457 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1458 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1459 1460 if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes 1461 Inst.addOperand(MCOperand::CreateImm(TransferBytes)); 1462 else // Decode Rm 1463 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder); 1464 1465 return MCDisassembler::Success; 1466 } 1467 1468 // Decode post-index of load/store lane 1469 // Loads have a vector list as output. 1470 if (IsLoad) { 1471 switch (NumVecs) { 1472 case 1: 1473 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 1474 break; 1475 case 2: 1476 DecodeQPairRegisterClass(Inst, Rt, Address, Decoder); 1477 break; 1478 case 3: 1479 DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder); 1480 break; 1481 case 4: 1482 DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder); 1483 } 1484 } 1485 1486 // Decode write back register, which is equal to Rn. 1487 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1488 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder); 1489 1490 if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes 1491 Inst.addOperand(MCOperand::CreateImm(TransferBytes)); 1492 else // Decode Rm 1493 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder); 1494 1495 // Decode the source vector list. 1496 switch (NumVecs) { 1497 case 1: 1498 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder); 1499 break; 1500 case 2: 1501 DecodeQPairRegisterClass(Inst, Rt, Address, Decoder); 1502 break; 1503 case 3: 1504 DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder); 1505 break; 1506 case 4: 1507 DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder); 1508 } 1509 1510 // Decode lane 1511 unsigned Q = fieldFromInstruction(Insn, 30, 1); 1512 unsigned S = fieldFromInstruction(Insn, 10, 3); 1513 unsigned lane = 0; 1514 switch (NumVecs) { 1515 case 1: 1516 lane = (Q << 3) & S; 1517 break; 1518 case 2: 1519 lane = (Q << 2) & (S >> 1); 1520 break; 1521 case 3: 1522 lane = (Q << 1) & (S >> 2); 1523 break; 1524 case 4: 1525 lane = Q; 1526 break; 1527 } 1528 Inst.addOperand(MCOperand::CreateImm(lane)); 1529 1530 return MCDisassembler::Success; 1531} 1532