AArch64InstPrinter.cpp revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb 
1//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an AArch64 MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AArch64InstPrinter.h"
15#include "MCTargetDesc/AArch64AddressingModes.h"
16#include "Utils/AArch64BaseInfo.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/ADT/StringExtras.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/Support/Format.h"
23#include "llvm/Support/raw_ostream.h"
24using namespace llvm;
25
26#define DEBUG_TYPE "asm-printer"
27
28#define GET_INSTRUCTION_NAME
29#define PRINT_ALIAS_INSTR
30#include "AArch64GenAsmWriter.inc"
31#define GET_INSTRUCTION_NAME
32#define PRINT_ALIAS_INSTR
33#include "AArch64GenAsmWriter1.inc"
34
35AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI,
36                                       const MCInstrInfo &MII,
37                                       const MCRegisterInfo &MRI,
38                                       const MCSubtargetInfo &STI)
39    : MCInstPrinter(MAI, MII, MRI) {
40  // Initialize the set of available features.
41  setAvailableFeatures(STI.getFeatureBits());
42}
43
44AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI,
45                                                 const MCInstrInfo &MII,
46                                                 const MCRegisterInfo &MRI,
47                                                 const MCSubtargetInfo &STI)
48    : AArch64InstPrinter(MAI, MII, MRI, STI) {}
49
50void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51  // This is for .cfi directives.
52  OS << getRegisterName(RegNo);
53}
54
55void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
56                                   StringRef Annot) {
57  // Check for special encodings and print the canonical alias instead.
58
59  unsigned Opcode = MI->getOpcode();
60
61  if (Opcode == AArch64::SYSxt)
62    if (printSysAlias(MI, O)) {
63      printAnnotation(O, Annot);
64      return;
65    }
66
67  // SBFM/UBFM should print to a nicer aliased form if possible.
68  if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
69      Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
70    const MCOperand &Op0 = MI->getOperand(0);
71    const MCOperand &Op1 = MI->getOperand(1);
72    const MCOperand &Op2 = MI->getOperand(2);
73    const MCOperand &Op3 = MI->getOperand(3);
74
75    bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
76    bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
77    if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
78      const char *AsmMnemonic = nullptr;
79
80      switch (Op3.getImm()) {
81      default:
82        break;
83      case 7:
84        if (IsSigned)
85          AsmMnemonic = "sxtb";
86        else if (!Is64Bit)
87          AsmMnemonic = "uxtb";
88        break;
89      case 15:
90        if (IsSigned)
91          AsmMnemonic = "sxth";
92        else if (!Is64Bit)
93          AsmMnemonic = "uxth";
94        break;
95      case 31:
96        // *xtw is only valid for signed 64-bit operations.
97        if (Is64Bit && IsSigned)
98          AsmMnemonic = "sxtw";
99        break;
100      }
101
102      if (AsmMnemonic) {
103        O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
104          << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
105        printAnnotation(O, Annot);
106        return;
107      }
108    }
109
110    // All immediate shifts are aliases, implemented using the Bitfield
111    // instruction. In all cases the immediate shift amount shift must be in
112    // the range 0 to (reg.size -1).
113    if (Op2.isImm() && Op3.isImm()) {
114      const char *AsmMnemonic = nullptr;
115      int shift = 0;
116      int64_t immr = Op2.getImm();
117      int64_t imms = Op3.getImm();
118      if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
119        AsmMnemonic = "lsl";
120        shift = 31 - imms;
121      } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
122                 ((imms + 1 == immr))) {
123        AsmMnemonic = "lsl";
124        shift = 63 - imms;
125      } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
126        AsmMnemonic = "lsr";
127        shift = immr;
128      } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
129        AsmMnemonic = "lsr";
130        shift = immr;
131      } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
132        AsmMnemonic = "asr";
133        shift = immr;
134      } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
135        AsmMnemonic = "asr";
136        shift = immr;
137      }
138      if (AsmMnemonic) {
139        O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
140          << ", " << getRegisterName(Op1.getReg()) << ", #" << shift;
141        printAnnotation(O, Annot);
142        return;
143      }
144    }
145
146    // SBFIZ/UBFIZ aliases
147    if (Op2.getImm() > Op3.getImm()) {
148      O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
149        << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
150        << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
151      printAnnotation(O, Annot);
152      return;
153    }
154
155    // Otherwise SBFX/UBFX is the preferred form
156    O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
157      << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
158      << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
159    printAnnotation(O, Annot);
160    return;
161  }
162
163  if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
164    const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
165    const MCOperand &Op2 = MI->getOperand(2);
166    int ImmR = MI->getOperand(3).getImm();
167    int ImmS = MI->getOperand(4).getImm();
168
169    // BFI alias
170    if (ImmS < ImmR) {
171      int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
172      int LSB = (BitWidth - ImmR) % BitWidth;
173      int Width = ImmS + 1;
174      O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
175        << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width;
176      printAnnotation(O, Annot);
177      return;
178    }
179
180    int LSB = ImmR;
181    int Width = ImmS - ImmR + 1;
182    // Otherwise BFXIL the preferred form
183    O << "\tbfxil\t"
184      << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
185      << ", #" << LSB << ", #" << Width;
186    printAnnotation(O, Annot);
187    return;
188  }
189
190  // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
191  // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
192  // printed.
193  if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
194       Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
195      MI->getOperand(1).isExpr()) {
196    if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
197      O << "\tmovz\t";
198    else
199      O << "\tmovn\t";
200
201    O << getRegisterName(MI->getOperand(0).getReg()) << ", #"
202      << *MI->getOperand(1).getExpr();
203    return;
204  }
205
206  if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
207      MI->getOperand(2).isExpr()) {
208    O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
209      << *MI->getOperand(2).getExpr();
210    return;
211  }
212
213  if (!printAliasInstr(MI, O))
214    printInstruction(MI, O);
215
216  printAnnotation(O, Annot);
217}
218
219static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
220                                bool &IsTbx) {
221  switch (Opcode) {
222  case AArch64::TBXv8i8One:
223  case AArch64::TBXv8i8Two:
224  case AArch64::TBXv8i8Three:
225  case AArch64::TBXv8i8Four:
226    IsTbx = true;
227    Layout = ".8b";
228    return true;
229  case AArch64::TBLv8i8One:
230  case AArch64::TBLv8i8Two:
231  case AArch64::TBLv8i8Three:
232  case AArch64::TBLv8i8Four:
233    IsTbx = false;
234    Layout = ".8b";
235    return true;
236  case AArch64::TBXv16i8One:
237  case AArch64::TBXv16i8Two:
238  case AArch64::TBXv16i8Three:
239  case AArch64::TBXv16i8Four:
240    IsTbx = true;
241    Layout = ".16b";
242    return true;
243  case AArch64::TBLv16i8One:
244  case AArch64::TBLv16i8Two:
245  case AArch64::TBLv16i8Three:
246  case AArch64::TBLv16i8Four:
247    IsTbx = false;
248    Layout = ".16b";
249    return true;
250  default:
251    return false;
252  }
253}
254
255struct LdStNInstrDesc {
256  unsigned Opcode;
257  const char *Mnemonic;
258  const char *Layout;
259  int ListOperand;
260  bool HasLane;
261  int NaturalOffset;
262};
263
264static LdStNInstrDesc LdStNInstInfo[] = {
265  { AArch64::LD1i8,             "ld1",  ".b",     1, true,  0  },
266  { AArch64::LD1i16,            "ld1",  ".h",     1, true,  0  },
267  { AArch64::LD1i32,            "ld1",  ".s",     1, true,  0  },
268  { AArch64::LD1i64,            "ld1",  ".d",     1, true,  0  },
269  { AArch64::LD1i8_POST,        "ld1",  ".b",     2, true,  1  },
270  { AArch64::LD1i16_POST,       "ld1",  ".h",     2, true,  2  },
271  { AArch64::LD1i32_POST,       "ld1",  ".s",     2, true,  4  },
272  { AArch64::LD1i64_POST,       "ld1",  ".d",     2, true,  8  },
273  { AArch64::LD1Rv16b,          "ld1r", ".16b",   0, false, 0  },
274  { AArch64::LD1Rv8h,           "ld1r", ".8h",    0, false, 0  },
275  { AArch64::LD1Rv4s,           "ld1r", ".4s",    0, false, 0  },
276  { AArch64::LD1Rv2d,           "ld1r", ".2d",    0, false, 0  },
277  { AArch64::LD1Rv8b,           "ld1r", ".8b",    0, false, 0  },
278  { AArch64::LD1Rv4h,           "ld1r", ".4h",    0, false, 0  },
279  { AArch64::LD1Rv2s,           "ld1r", ".2s",    0, false, 0  },
280  { AArch64::LD1Rv1d,           "ld1r", ".1d",    0, false, 0  },
281  { AArch64::LD1Rv16b_POST,     "ld1r", ".16b",   1, false, 1  },
282  { AArch64::LD1Rv8h_POST,      "ld1r", ".8h",    1, false, 2  },
283  { AArch64::LD1Rv4s_POST,      "ld1r", ".4s",    1, false, 4  },
284  { AArch64::LD1Rv2d_POST,      "ld1r", ".2d",    1, false, 8  },
285  { AArch64::LD1Rv8b_POST,      "ld1r", ".8b",    1, false, 1  },
286  { AArch64::LD1Rv4h_POST,      "ld1r", ".4h",    1, false, 2  },
287  { AArch64::LD1Rv2s_POST,      "ld1r", ".2s",    1, false, 4  },
288  { AArch64::LD1Rv1d_POST,      "ld1r", ".1d",    1, false, 8  },
289  { AArch64::LD1Onev16b,        "ld1",  ".16b",   0, false, 0  },
290  { AArch64::LD1Onev8h,         "ld1",  ".8h",    0, false, 0  },
291  { AArch64::LD1Onev4s,         "ld1",  ".4s",    0, false, 0  },
292  { AArch64::LD1Onev2d,         "ld1",  ".2d",    0, false, 0  },
293  { AArch64::LD1Onev8b,         "ld1",  ".8b",    0, false, 0  },
294  { AArch64::LD1Onev4h,         "ld1",  ".4h",    0, false, 0  },
295  { AArch64::LD1Onev2s,         "ld1",  ".2s",    0, false, 0  },
296  { AArch64::LD1Onev1d,         "ld1",  ".1d",    0, false, 0  },
297  { AArch64::LD1Onev16b_POST,   "ld1",  ".16b",   1, false, 16 },
298  { AArch64::LD1Onev8h_POST,    "ld1",  ".8h",    1, false, 16 },
299  { AArch64::LD1Onev4s_POST,    "ld1",  ".4s",    1, false, 16 },
300  { AArch64::LD1Onev2d_POST,    "ld1",  ".2d",    1, false, 16 },
301  { AArch64::LD1Onev8b_POST,    "ld1",  ".8b",    1, false, 8  },
302  { AArch64::LD1Onev4h_POST,    "ld1",  ".4h",    1, false, 8  },
303  { AArch64::LD1Onev2s_POST,    "ld1",  ".2s",    1, false, 8  },
304  { AArch64::LD1Onev1d_POST,    "ld1",  ".1d",    1, false, 8  },
305  { AArch64::LD1Twov16b,        "ld1",  ".16b",   0, false, 0  },
306  { AArch64::LD1Twov8h,         "ld1",  ".8h",    0, false, 0  },
307  { AArch64::LD1Twov4s,         "ld1",  ".4s",    0, false, 0  },
308  { AArch64::LD1Twov2d,         "ld1",  ".2d",    0, false, 0  },
309  { AArch64::LD1Twov8b,         "ld1",  ".8b",    0, false, 0  },
310  { AArch64::LD1Twov4h,         "ld1",  ".4h",    0, false, 0  },
311  { AArch64::LD1Twov2s,         "ld1",  ".2s",    0, false, 0  },
312  { AArch64::LD1Twov1d,         "ld1",  ".1d",    0, false, 0  },
313  { AArch64::LD1Twov16b_POST,   "ld1",  ".16b",   1, false, 32 },
314  { AArch64::LD1Twov8h_POST,    "ld1",  ".8h",    1, false, 32 },
315  { AArch64::LD1Twov4s_POST,    "ld1",  ".4s",    1, false, 32 },
316  { AArch64::LD1Twov2d_POST,    "ld1",  ".2d",    1, false, 32 },
317  { AArch64::LD1Twov8b_POST,    "ld1",  ".8b",    1, false, 16 },
318  { AArch64::LD1Twov4h_POST,    "ld1",  ".4h",    1, false, 16 },
319  { AArch64::LD1Twov2s_POST,    "ld1",  ".2s",    1, false, 16 },
320  { AArch64::LD1Twov1d_POST,    "ld1",  ".1d",    1, false, 16 },
321  { AArch64::LD1Threev16b,      "ld1",  ".16b",   0, false, 0  },
322  { AArch64::LD1Threev8h,       "ld1",  ".8h",    0, false, 0  },
323  { AArch64::LD1Threev4s,       "ld1",  ".4s",    0, false, 0  },
324  { AArch64::LD1Threev2d,       "ld1",  ".2d",    0, false, 0  },
325  { AArch64::LD1Threev8b,       "ld1",  ".8b",    0, false, 0  },
326  { AArch64::LD1Threev4h,       "ld1",  ".4h",    0, false, 0  },
327  { AArch64::LD1Threev2s,       "ld1",  ".2s",    0, false, 0  },
328  { AArch64::LD1Threev1d,       "ld1",  ".1d",    0, false, 0  },
329  { AArch64::LD1Threev16b_POST, "ld1",  ".16b",   1, false, 48 },
330  { AArch64::LD1Threev8h_POST,  "ld1",  ".8h",    1, false, 48 },
331  { AArch64::LD1Threev4s_POST,  "ld1",  ".4s",    1, false, 48 },
332  { AArch64::LD1Threev2d_POST,  "ld1",  ".2d",    1, false, 48 },
333  { AArch64::LD1Threev8b_POST,  "ld1",  ".8b",    1, false, 24 },
334  { AArch64::LD1Threev4h_POST,  "ld1",  ".4h",    1, false, 24 },
335  { AArch64::LD1Threev2s_POST,  "ld1",  ".2s",    1, false, 24 },
336  { AArch64::LD1Threev1d_POST,  "ld1",  ".1d",    1, false, 24 },
337  { AArch64::LD1Fourv16b,       "ld1",  ".16b",   0, false, 0  },
338  { AArch64::LD1Fourv8h,        "ld1",  ".8h",    0, false, 0  },
339  { AArch64::LD1Fourv4s,        "ld1",  ".4s",    0, false, 0  },
340  { AArch64::LD1Fourv2d,        "ld1",  ".2d",    0, false, 0  },
341  { AArch64::LD1Fourv8b,        "ld1",  ".8b",    0, false, 0  },
342  { AArch64::LD1Fourv4h,        "ld1",  ".4h",    0, false, 0  },
343  { AArch64::LD1Fourv2s,        "ld1",  ".2s",    0, false, 0  },
344  { AArch64::LD1Fourv1d,        "ld1",  ".1d",    0, false, 0  },
345  { AArch64::LD1Fourv16b_POST,  "ld1",  ".16b",   1, false, 64 },
346  { AArch64::LD1Fourv8h_POST,   "ld1",  ".8h",    1, false, 64 },
347  { AArch64::LD1Fourv4s_POST,   "ld1",  ".4s",    1, false, 64 },
348  { AArch64::LD1Fourv2d_POST,   "ld1",  ".2d",    1, false, 64 },
349  { AArch64::LD1Fourv8b_POST,   "ld1",  ".8b",    1, false, 32 },
350  { AArch64::LD1Fourv4h_POST,   "ld1",  ".4h",    1, false, 32 },
351  { AArch64::LD1Fourv2s_POST,   "ld1",  ".2s",    1, false, 32 },
352  { AArch64::LD1Fourv1d_POST,   "ld1",  ".1d",    1, false, 32 },
353  { AArch64::LD2i8,             "ld2",  ".b",     1, true,  0  },
354  { AArch64::LD2i16,            "ld2",  ".h",     1, true,  0  },
355  { AArch64::LD2i32,            "ld2",  ".s",     1, true,  0  },
356  { AArch64::LD2i64,            "ld2",  ".d",     1, true,  0  },
357  { AArch64::LD2i8_POST,        "ld2",  ".b",     2, true,  2  },
358  { AArch64::LD2i16_POST,       "ld2",  ".h",     2, true,  4  },
359  { AArch64::LD2i32_POST,       "ld2",  ".s",     2, true,  8  },
360  { AArch64::LD2i64_POST,       "ld2",  ".d",     2, true,  16  },
361  { AArch64::LD2Rv16b,          "ld2r", ".16b",   0, false, 0  },
362  { AArch64::LD2Rv8h,           "ld2r", ".8h",    0, false, 0  },
363  { AArch64::LD2Rv4s,           "ld2r", ".4s",    0, false, 0  },
364  { AArch64::LD2Rv2d,           "ld2r", ".2d",    0, false, 0  },
365  { AArch64::LD2Rv8b,           "ld2r", ".8b",    0, false, 0  },
366  { AArch64::LD2Rv4h,           "ld2r", ".4h",    0, false, 0  },
367  { AArch64::LD2Rv2s,           "ld2r", ".2s",    0, false, 0  },
368  { AArch64::LD2Rv1d,           "ld2r", ".1d",    0, false, 0  },
369  { AArch64::LD2Rv16b_POST,     "ld2r", ".16b",   1, false, 2  },
370  { AArch64::LD2Rv8h_POST,      "ld2r", ".8h",    1, false, 4  },
371  { AArch64::LD2Rv4s_POST,      "ld2r", ".4s",    1, false, 8  },
372  { AArch64::LD2Rv2d_POST,      "ld2r", ".2d",    1, false, 16 },
373  { AArch64::LD2Rv8b_POST,      "ld2r", ".8b",    1, false, 2  },
374  { AArch64::LD2Rv4h_POST,      "ld2r", ".4h",    1, false, 4  },
375  { AArch64::LD2Rv2s_POST,      "ld2r", ".2s",    1, false, 8  },
376  { AArch64::LD2Rv1d_POST,      "ld2r", ".1d",    1, false, 16 },
377  { AArch64::LD2Twov16b,        "ld2",  ".16b",   0, false, 0  },
378  { AArch64::LD2Twov8h,         "ld2",  ".8h",    0, false, 0  },
379  { AArch64::LD2Twov4s,         "ld2",  ".4s",    0, false, 0  },
380  { AArch64::LD2Twov2d,         "ld2",  ".2d",    0, false, 0  },
381  { AArch64::LD2Twov8b,         "ld2",  ".8b",    0, false, 0  },
382  { AArch64::LD2Twov4h,         "ld2",  ".4h",    0, false, 0  },
383  { AArch64::LD2Twov2s,         "ld2",  ".2s",    0, false, 0  },
384  { AArch64::LD2Twov16b_POST,   "ld2",  ".16b",   1, false, 32 },
385  { AArch64::LD2Twov8h_POST,    "ld2",  ".8h",    1, false, 32 },
386  { AArch64::LD2Twov4s_POST,    "ld2",  ".4s",    1, false, 32 },
387  { AArch64::LD2Twov2d_POST,    "ld2",  ".2d",    1, false, 32 },
388  { AArch64::LD2Twov8b_POST,    "ld2",  ".8b",    1, false, 16 },
389  { AArch64::LD2Twov4h_POST,    "ld2",  ".4h",    1, false, 16 },
390  { AArch64::LD2Twov2s_POST,    "ld2",  ".2s",    1, false, 16 },
391  { AArch64::LD3i8,             "ld3",  ".b",     1, true,  0  },
392  { AArch64::LD3i16,            "ld3",  ".h",     1, true,  0  },
393  { AArch64::LD3i32,            "ld3",  ".s",     1, true,  0  },
394  { AArch64::LD3i64,            "ld3",  ".d",     1, true,  0  },
395  { AArch64::LD3i8_POST,        "ld3",  ".b",     2, true,  3  },
396  { AArch64::LD3i16_POST,       "ld3",  ".h",     2, true,  6  },
397  { AArch64::LD3i32_POST,       "ld3",  ".s",     2, true,  12  },
398  { AArch64::LD3i64_POST,       "ld3",  ".d",     2, true,  24  },
399  { AArch64::LD3Rv16b,          "ld3r", ".16b",   0, false, 0  },
400  { AArch64::LD3Rv8h,           "ld3r", ".8h",    0, false, 0  },
401  { AArch64::LD3Rv4s,           "ld3r", ".4s",    0, false, 0  },
402  { AArch64::LD3Rv2d,           "ld3r", ".2d",    0, false, 0  },
403  { AArch64::LD3Rv8b,           "ld3r", ".8b",    0, false, 0  },
404  { AArch64::LD3Rv4h,           "ld3r", ".4h",    0, false, 0  },
405  { AArch64::LD3Rv2s,           "ld3r", ".2s",    0, false, 0  },
406  { AArch64::LD3Rv1d,           "ld3r", ".1d",    0, false, 0  },
407  { AArch64::LD3Rv16b_POST,     "ld3r", ".16b",   1, false, 3  },
408  { AArch64::LD3Rv8h_POST,      "ld3r", ".8h",    1, false, 6  },
409  { AArch64::LD3Rv4s_POST,      "ld3r", ".4s",    1, false, 12 },
410  { AArch64::LD3Rv2d_POST,      "ld3r", ".2d",    1, false, 24 },
411  { AArch64::LD3Rv8b_POST,      "ld3r", ".8b",    1, false, 3  },
412  { AArch64::LD3Rv4h_POST,      "ld3r", ".4h",    1, false, 6  },
413  { AArch64::LD3Rv2s_POST,      "ld3r", ".2s",    1, false, 12 },
414  { AArch64::LD3Rv1d_POST,      "ld3r", ".1d",    1, false, 24 },
415  { AArch64::LD3Threev16b,      "ld3",  ".16b",   0, false, 0  },
416  { AArch64::LD3Threev8h,       "ld3",  ".8h",    0, false, 0  },
417  { AArch64::LD3Threev4s,       "ld3",  ".4s",    0, false, 0  },
418  { AArch64::LD3Threev2d,       "ld3",  ".2d",    0, false, 0  },
419  { AArch64::LD3Threev8b,       "ld3",  ".8b",    0, false, 0  },
420  { AArch64::LD3Threev4h,       "ld3",  ".4h",    0, false, 0  },
421  { AArch64::LD3Threev2s,       "ld3",  ".2s",    0, false, 0  },
422  { AArch64::LD3Threev16b_POST, "ld3",  ".16b",   1, false, 48 },
423  { AArch64::LD3Threev8h_POST,  "ld3",  ".8h",    1, false, 48 },
424  { AArch64::LD3Threev4s_POST,  "ld3",  ".4s",    1, false, 48 },
425  { AArch64::LD3Threev2d_POST,  "ld3",  ".2d",    1, false, 48 },
426  { AArch64::LD3Threev8b_POST,  "ld3",  ".8b",    1, false, 24 },
427  { AArch64::LD3Threev4h_POST,  "ld3",  ".4h",    1, false, 24 },
428  { AArch64::LD3Threev2s_POST,  "ld3",  ".2s",    1, false, 24 },
429  { AArch64::LD4i8,             "ld4",  ".b",     1, true,  0  },
430  { AArch64::LD4i16,            "ld4",  ".h",     1, true,  0  },
431  { AArch64::LD4i32,            "ld4",  ".s",     1, true,  0  },
432  { AArch64::LD4i64,            "ld4",  ".d",     1, true,  0  },
433  { AArch64::LD4i8_POST,        "ld4",  ".b",     2, true,  4  },
434  { AArch64::LD4i16_POST,       "ld4",  ".h",     2, true,  8  },
435  { AArch64::LD4i32_POST,       "ld4",  ".s",     2, true,  16 },
436  { AArch64::LD4i64_POST,       "ld4",  ".d",     2, true,  32 },
437  { AArch64::LD4Rv16b,          "ld4r", ".16b",   0, false, 0  },
438  { AArch64::LD4Rv8h,           "ld4r", ".8h",    0, false, 0  },
439  { AArch64::LD4Rv4s,           "ld4r", ".4s",    0, false, 0  },
440  { AArch64::LD4Rv2d,           "ld4r", ".2d",    0, false, 0  },
441  { AArch64::LD4Rv8b,           "ld4r", ".8b",    0, false, 0  },
442  { AArch64::LD4Rv4h,           "ld4r", ".4h",    0, false, 0  },
443  { AArch64::LD4Rv2s,           "ld4r", ".2s",    0, false, 0  },
444  { AArch64::LD4Rv1d,           "ld4r", ".1d",    0, false, 0  },
445  { AArch64::LD4Rv16b_POST,     "ld4r", ".16b",   1, false, 4  },
446  { AArch64::LD4Rv8h_POST,      "ld4r", ".8h",    1, false, 8  },
447  { AArch64::LD4Rv4s_POST,      "ld4r", ".4s",    1, false, 16 },
448  { AArch64::LD4Rv2d_POST,      "ld4r", ".2d",    1, false, 32 },
449  { AArch64::LD4Rv8b_POST,      "ld4r", ".8b",    1, false, 4  },
450  { AArch64::LD4Rv4h_POST,      "ld4r", ".4h",    1, false, 8  },
451  { AArch64::LD4Rv2s_POST,      "ld4r", ".2s",    1, false, 16 },
452  { AArch64::LD4Rv1d_POST,      "ld4r", ".1d",    1, false, 32 },
453  { AArch64::LD4Fourv16b,       "ld4",  ".16b",   0, false, 0  },
454  { AArch64::LD4Fourv8h,        "ld4",  ".8h",    0, false, 0  },
455  { AArch64::LD4Fourv4s,        "ld4",  ".4s",    0, false, 0  },
456  { AArch64::LD4Fourv2d,        "ld4",  ".2d",    0, false, 0  },
457  { AArch64::LD4Fourv8b,        "ld4",  ".8b",    0, false, 0  },
458  { AArch64::LD4Fourv4h,        "ld4",  ".4h",    0, false, 0  },
459  { AArch64::LD4Fourv2s,        "ld4",  ".2s",    0, false, 0  },
460  { AArch64::LD4Fourv16b_POST,  "ld4",  ".16b",   1, false, 64 },
461  { AArch64::LD4Fourv8h_POST,   "ld4",  ".8h",    1, false, 64 },
462  { AArch64::LD4Fourv4s_POST,   "ld4",  ".4s",    1, false, 64 },
463  { AArch64::LD4Fourv2d_POST,   "ld4",  ".2d",    1, false, 64 },
464  { AArch64::LD4Fourv8b_POST,   "ld4",  ".8b",    1, false, 32 },
465  { AArch64::LD4Fourv4h_POST,   "ld4",  ".4h",    1, false, 32 },
466  { AArch64::LD4Fourv2s_POST,   "ld4",  ".2s",    1, false, 32 },
467  { AArch64::ST1i8,             "st1",  ".b",     0, true,  0  },
468  { AArch64::ST1i16,            "st1",  ".h",     0, true,  0  },
469  { AArch64::ST1i32,            "st1",  ".s",     0, true,  0  },
470  { AArch64::ST1i64,            "st1",  ".d",     0, true,  0  },
471  { AArch64::ST1i8_POST,        "st1",  ".b",     1, true,  1  },
472  { AArch64::ST1i16_POST,       "st1",  ".h",     1, true,  2  },
473  { AArch64::ST1i32_POST,       "st1",  ".s",     1, true,  4  },
474  { AArch64::ST1i64_POST,       "st1",  ".d",     1, true,  8  },
475  { AArch64::ST1Onev16b,        "st1",  ".16b",   0, false, 0  },
476  { AArch64::ST1Onev8h,         "st1",  ".8h",    0, false, 0  },
477  { AArch64::ST1Onev4s,         "st1",  ".4s",    0, false, 0  },
478  { AArch64::ST1Onev2d,         "st1",  ".2d",    0, false, 0  },
479  { AArch64::ST1Onev8b,         "st1",  ".8b",    0, false, 0  },
480  { AArch64::ST1Onev4h,         "st1",  ".4h",    0, false, 0  },
481  { AArch64::ST1Onev2s,         "st1",  ".2s",    0, false, 0  },
482  { AArch64::ST1Onev1d,         "st1",  ".1d",    0, false, 0  },
483  { AArch64::ST1Onev16b_POST,   "st1",  ".16b",   1, false, 16 },
484  { AArch64::ST1Onev8h_POST,    "st1",  ".8h",    1, false, 16 },
485  { AArch64::ST1Onev4s_POST,    "st1",  ".4s",    1, false, 16 },
486  { AArch64::ST1Onev2d_POST,    "st1",  ".2d",    1, false, 16 },
487  { AArch64::ST1Onev8b_POST,    "st1",  ".8b",    1, false, 8  },
488  { AArch64::ST1Onev4h_POST,    "st1",  ".4h",    1, false, 8  },
489  { AArch64::ST1Onev2s_POST,    "st1",  ".2s",    1, false, 8  },
490  { AArch64::ST1Onev1d_POST,    "st1",  ".1d",    1, false, 8  },
491  { AArch64::ST1Twov16b,        "st1",  ".16b",   0, false, 0  },
492  { AArch64::ST1Twov8h,         "st1",  ".8h",    0, false, 0  },
493  { AArch64::ST1Twov4s,         "st1",  ".4s",    0, false, 0  },
494  { AArch64::ST1Twov2d,         "st1",  ".2d",    0, false, 0  },
495  { AArch64::ST1Twov8b,         "st1",  ".8b",    0, false, 0  },
496  { AArch64::ST1Twov4h,         "st1",  ".4h",    0, false, 0  },
497  { AArch64::ST1Twov2s,         "st1",  ".2s",    0, false, 0  },
498  { AArch64::ST1Twov1d,         "st1",  ".1d",    0, false, 0  },
499  { AArch64::ST1Twov16b_POST,   "st1",  ".16b",   1, false, 32 },
500  { AArch64::ST1Twov8h_POST,    "st1",  ".8h",    1, false, 32 },
501  { AArch64::ST1Twov4s_POST,    "st1",  ".4s",    1, false, 32 },
502  { AArch64::ST1Twov2d_POST,    "st1",  ".2d",    1, false, 32 },
503  { AArch64::ST1Twov8b_POST,    "st1",  ".8b",    1, false, 16 },
504  { AArch64::ST1Twov4h_POST,    "st1",  ".4h",    1, false, 16 },
505  { AArch64::ST1Twov2s_POST,    "st1",  ".2s",    1, false, 16 },
506  { AArch64::ST1Twov1d_POST,    "st1",  ".1d",    1, false, 16 },
507  { AArch64::ST1Threev16b,      "st1",  ".16b",   0, false, 0  },
508  { AArch64::ST1Threev8h,       "st1",  ".8h",    0, false, 0  },
509  { AArch64::ST1Threev4s,       "st1",  ".4s",    0, false, 0  },
510  { AArch64::ST1Threev2d,       "st1",  ".2d",    0, false, 0  },
511  { AArch64::ST1Threev8b,       "st1",  ".8b",    0, false, 0  },
512  { AArch64::ST1Threev4h,       "st1",  ".4h",    0, false, 0  },
513  { AArch64::ST1Threev2s,       "st1",  ".2s",    0, false, 0  },
514  { AArch64::ST1Threev1d,       "st1",  ".1d",    0, false, 0  },
515  { AArch64::ST1Threev16b_POST, "st1",  ".16b",   1, false, 48 },
516  { AArch64::ST1Threev8h_POST,  "st1",  ".8h",    1, false, 48 },
517  { AArch64::ST1Threev4s_POST,  "st1",  ".4s",    1, false, 48 },
518  { AArch64::ST1Threev2d_POST,  "st1",  ".2d",    1, false, 48 },
519  { AArch64::ST1Threev8b_POST,  "st1",  ".8b",    1, false, 24 },
520  { AArch64::ST1Threev4h_POST,  "st1",  ".4h",    1, false, 24 },
521  { AArch64::ST1Threev2s_POST,  "st1",  ".2s",    1, false, 24 },
522  { AArch64::ST1Threev1d_POST,  "st1",  ".1d",    1, false, 24 },
523  { AArch64::ST1Fourv16b,       "st1",  ".16b",   0, false, 0  },
524  { AArch64::ST1Fourv8h,        "st1",  ".8h",    0, false, 0  },
525  { AArch64::ST1Fourv4s,        "st1",  ".4s",    0, false, 0  },
526  { AArch64::ST1Fourv2d,        "st1",  ".2d",    0, false, 0  },
527  { AArch64::ST1Fourv8b,        "st1",  ".8b",    0, false, 0  },
528  { AArch64::ST1Fourv4h,        "st1",  ".4h",    0, false, 0  },
529  { AArch64::ST1Fourv2s,        "st1",  ".2s",    0, false, 0  },
530  { AArch64::ST1Fourv1d,        "st1",  ".1d",    0, false, 0  },
531  { AArch64::ST1Fourv16b_POST,  "st1",  ".16b",   1, false, 64 },
532  { AArch64::ST1Fourv8h_POST,   "st1",  ".8h",    1, false, 64 },
533  { AArch64::ST1Fourv4s_POST,   "st1",  ".4s",    1, false, 64 },
534  { AArch64::ST1Fourv2d_POST,   "st1",  ".2d",    1, false, 64 },
535  { AArch64::ST1Fourv8b_POST,   "st1",  ".8b",    1, false, 32 },
536  { AArch64::ST1Fourv4h_POST,   "st1",  ".4h",    1, false, 32 },
537  { AArch64::ST1Fourv2s_POST,   "st1",  ".2s",    1, false, 32 },
538  { AArch64::ST1Fourv1d_POST,   "st1",  ".1d",    1, false, 32 },
539  { AArch64::ST2i8,             "st2",  ".b",     0, true,  0  },
540  { AArch64::ST2i16,            "st2",  ".h",     0, true,  0  },
541  { AArch64::ST2i32,            "st2",  ".s",     0, true,  0  },
542  { AArch64::ST2i64,            "st2",  ".d",     0, true,  0  },
543  { AArch64::ST2i8_POST,        "st2",  ".b",     1, true,  2  },
544  { AArch64::ST2i16_POST,       "st2",  ".h",     1, true,  4  },
545  { AArch64::ST2i32_POST,       "st2",  ".s",     1, true,  8  },
546  { AArch64::ST2i64_POST,       "st2",  ".d",     1, true,  16 },
547  { AArch64::ST2Twov16b,        "st2",  ".16b",   0, false, 0  },
548  { AArch64::ST2Twov8h,         "st2",  ".8h",    0, false, 0  },
549  { AArch64::ST2Twov4s,         "st2",  ".4s",    0, false, 0  },
550  { AArch64::ST2Twov2d,         "st2",  ".2d",    0, false, 0  },
551  { AArch64::ST2Twov8b,         "st2",  ".8b",    0, false, 0  },
552  { AArch64::ST2Twov4h,         "st2",  ".4h",    0, false, 0  },
553  { AArch64::ST2Twov2s,         "st2",  ".2s",    0, false, 0  },
554  { AArch64::ST2Twov16b_POST,   "st2",  ".16b",   1, false, 32 },
555  { AArch64::ST2Twov8h_POST,    "st2",  ".8h",    1, false, 32 },
556  { AArch64::ST2Twov4s_POST,    "st2",  ".4s",    1, false, 32 },
557  { AArch64::ST2Twov2d_POST,    "st2",  ".2d",    1, false, 32 },
558  { AArch64::ST2Twov8b_POST,    "st2",  ".8b",    1, false, 16 },
559  { AArch64::ST2Twov4h_POST,    "st2",  ".4h",    1, false, 16 },
560  { AArch64::ST2Twov2s_POST,    "st2",  ".2s",    1, false, 16 },
561  { AArch64::ST3i8,             "st3",  ".b",     0, true,  0  },
562  { AArch64::ST3i16,            "st3",  ".h",     0, true,  0  },
563  { AArch64::ST3i32,            "st3",  ".s",     0, true,  0  },
564  { AArch64::ST3i64,            "st3",  ".d",     0, true,  0  },
565  { AArch64::ST3i8_POST,        "st3",  ".b",     1, true,  3  },
566  { AArch64::ST3i16_POST,       "st3",  ".h",     1, true,  6  },
567  { AArch64::ST3i32_POST,       "st3",  ".s",     1, true,  12 },
568  { AArch64::ST3i64_POST,       "st3",  ".d",     1, true,  24 },
569  { AArch64::ST3Threev16b,      "st3",  ".16b",   0, false, 0  },
570  { AArch64::ST3Threev8h,       "st3",  ".8h",    0, false, 0  },
571  { AArch64::ST3Threev4s,       "st3",  ".4s",    0, false, 0  },
572  { AArch64::ST3Threev2d,       "st3",  ".2d",    0, false, 0  },
573  { AArch64::ST3Threev8b,       "st3",  ".8b",    0, false, 0  },
574  { AArch64::ST3Threev4h,       "st3",  ".4h",    0, false, 0  },
575  { AArch64::ST3Threev2s,       "st3",  ".2s",    0, false, 0  },
576  { AArch64::ST3Threev16b_POST, "st3",  ".16b",   1, false, 48 },
577  { AArch64::ST3Threev8h_POST,  "st3",  ".8h",    1, false, 48 },
578  { AArch64::ST3Threev4s_POST,  "st3",  ".4s",    1, false, 48 },
579  { AArch64::ST3Threev2d_POST,  "st3",  ".2d",    1, false, 48 },
580  { AArch64::ST3Threev8b_POST,  "st3",  ".8b",    1, false, 24 },
581  { AArch64::ST3Threev4h_POST,  "st3",  ".4h",    1, false, 24 },
582  { AArch64::ST3Threev2s_POST,  "st3",  ".2s",    1, false, 24 },
583  { AArch64::ST4i8,             "st4",  ".b",     0, true,  0  },
584  { AArch64::ST4i16,            "st4",  ".h",     0, true,  0  },
585  { AArch64::ST4i32,            "st4",  ".s",     0, true,  0  },
586  { AArch64::ST4i64,            "st4",  ".d",     0, true,  0  },
587  { AArch64::ST4i8_POST,        "st4",  ".b",     1, true,  4  },
588  { AArch64::ST4i16_POST,       "st4",  ".h",     1, true,  8  },
589  { AArch64::ST4i32_POST,       "st4",  ".s",     1, true,  16 },
590  { AArch64::ST4i64_POST,       "st4",  ".d",     1, true,  32 },
591  { AArch64::ST4Fourv16b,       "st4",  ".16b",   0, false, 0  },
592  { AArch64::ST4Fourv8h,        "st4",  ".8h",    0, false, 0  },
593  { AArch64::ST4Fourv4s,        "st4",  ".4s",    0, false, 0  },
594  { AArch64::ST4Fourv2d,        "st4",  ".2d",    0, false, 0  },
595  { AArch64::ST4Fourv8b,        "st4",  ".8b",    0, false, 0  },
596  { AArch64::ST4Fourv4h,        "st4",  ".4h",    0, false, 0  },
597  { AArch64::ST4Fourv2s,        "st4",  ".2s",    0, false, 0  },
598  { AArch64::ST4Fourv16b_POST,  "st4",  ".16b",   1, false, 64 },
599  { AArch64::ST4Fourv8h_POST,   "st4",  ".8h",    1, false, 64 },
600  { AArch64::ST4Fourv4s_POST,   "st4",  ".4s",    1, false, 64 },
601  { AArch64::ST4Fourv2d_POST,   "st4",  ".2d",    1, false, 64 },
602  { AArch64::ST4Fourv8b_POST,   "st4",  ".8b",    1, false, 32 },
603  { AArch64::ST4Fourv4h_POST,   "st4",  ".4h",    1, false, 32 },
604  { AArch64::ST4Fourv2s_POST,   "st4",  ".2s",    1, false, 32 },
605};
606
607static LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
608  unsigned Idx;
609  for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx)
610    if (LdStNInstInfo[Idx].Opcode == Opcode)
611      return &LdStNInstInfo[Idx];
612
613  return nullptr;
614}
615
616void AArch64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
617                                        StringRef Annot) {
618  unsigned Opcode = MI->getOpcode();
619  StringRef Layout, Mnemonic;
620
621  bool IsTbx;
622  if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
623    O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
624      << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", ";
625
626    unsigned ListOpNum = IsTbx ? 2 : 1;
627    printVectorList(MI, ListOpNum, O, "");
628
629    O << ", "
630      << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
631    printAnnotation(O, Annot);
632    return;
633  }
634
635  if (LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
636    O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
637
638    // Now onto the operands: first a vector list with possible lane
639    // specifier. E.g. { v0 }[2]
640    int OpNum = LdStDesc->ListOperand;
641    printVectorList(MI, OpNum++, O, "");
642
643    if (LdStDesc->HasLane)
644      O << '[' << MI->getOperand(OpNum++).getImm() << ']';
645
646    // Next the address: [xN]
647    unsigned AddrReg = MI->getOperand(OpNum++).getReg();
648    O << ", [" << getRegisterName(AddrReg) << ']';
649
650    // Finally, there might be a post-indexed offset.
651    if (LdStDesc->NaturalOffset != 0) {
652      unsigned Reg = MI->getOperand(OpNum++).getReg();
653      if (Reg != AArch64::XZR)
654        O << ", " << getRegisterName(Reg);
655      else {
656        assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
657        O << ", #" << LdStDesc->NaturalOffset;
658      }
659    }
660
661    printAnnotation(O, Annot);
662    return;
663  }
664
665  AArch64InstPrinter::printInst(MI, O, Annot);
666}
667
668bool AArch64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
669#ifndef NDEBUG
670  unsigned Opcode = MI->getOpcode();
671  assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
672#endif
673
674  const char *Asm = nullptr;
675  const MCOperand &Op1 = MI->getOperand(0);
676  const MCOperand &Cn = MI->getOperand(1);
677  const MCOperand &Cm = MI->getOperand(2);
678  const MCOperand &Op2 = MI->getOperand(3);
679
680  unsigned Op1Val = Op1.getImm();
681  unsigned CnVal = Cn.getImm();
682  unsigned CmVal = Cm.getImm();
683  unsigned Op2Val = Op2.getImm();
684
685  if (CnVal == 7) {
686    switch (CmVal) {
687    default:
688      break;
689
690    // IC aliases
691    case 1:
692      if (Op1Val == 0 && Op2Val == 0)
693        Asm = "ic\tialluis";
694      break;
695    case 5:
696      if (Op1Val == 0 && Op2Val == 0)
697        Asm = "ic\tiallu";
698      else if (Op1Val == 3 && Op2Val == 1)
699        Asm = "ic\tivau";
700      break;
701
702    // DC aliases
703    case 4:
704      if (Op1Val == 3 && Op2Val == 1)
705        Asm = "dc\tzva";
706      break;
707    case 6:
708      if (Op1Val == 0 && Op2Val == 1)
709        Asm = "dc\tivac";
710      if (Op1Val == 0 && Op2Val == 2)
711        Asm = "dc\tisw";
712      break;
713    case 10:
714      if (Op1Val == 3 && Op2Val == 1)
715        Asm = "dc\tcvac";
716      else if (Op1Val == 0 && Op2Val == 2)
717        Asm = "dc\tcsw";
718      break;
719    case 11:
720      if (Op1Val == 3 && Op2Val == 1)
721        Asm = "dc\tcvau";
722      break;
723    case 14:
724      if (Op1Val == 3 && Op2Val == 1)
725        Asm = "dc\tcivac";
726      else if (Op1Val == 0 && Op2Val == 2)
727        Asm = "dc\tcisw";
728      break;
729
730    // AT aliases
731    case 8:
732      switch (Op1Val) {
733      default:
734        break;
735      case 0:
736        switch (Op2Val) {
737        default:
738          break;
739        case 0: Asm = "at\ts1e1r"; break;
740        case 1: Asm = "at\ts1e1w"; break;
741        case 2: Asm = "at\ts1e0r"; break;
742        case 3: Asm = "at\ts1e0w"; break;
743        }
744        break;
745      case 4:
746        switch (Op2Val) {
747        default:
748          break;
749        case 0: Asm = "at\ts1e2r"; break;
750        case 1: Asm = "at\ts1e2w"; break;
751        case 4: Asm = "at\ts12e1r"; break;
752        case 5: Asm = "at\ts12e1w"; break;
753        case 6: Asm = "at\ts12e0r"; break;
754        case 7: Asm = "at\ts12e0w"; break;
755        }
756        break;
757      case 6:
758        switch (Op2Val) {
759        default:
760          break;
761        case 0: Asm = "at\ts1e3r"; break;
762        case 1: Asm = "at\ts1e3w"; break;
763        }
764        break;
765      }
766      break;
767    }
768  } else if (CnVal == 8) {
769    // TLBI aliases
770    switch (CmVal) {
771    default:
772      break;
773    case 3:
774      switch (Op1Val) {
775      default:
776        break;
777      case 0:
778        switch (Op2Val) {
779        default:
780          break;
781        case 0: Asm = "tlbi\tvmalle1is"; break;
782        case 1: Asm = "tlbi\tvae1is"; break;
783        case 2: Asm = "tlbi\taside1is"; break;
784        case 3: Asm = "tlbi\tvaae1is"; break;
785        case 5: Asm = "tlbi\tvale1is"; break;
786        case 7: Asm = "tlbi\tvaale1is"; break;
787        }
788        break;
789      case 4:
790        switch (Op2Val) {
791        default:
792          break;
793        case 0: Asm = "tlbi\talle2is"; break;
794        case 1: Asm = "tlbi\tvae2is"; break;
795        case 4: Asm = "tlbi\talle1is"; break;
796        case 5: Asm = "tlbi\tvale2is"; break;
797        case 6: Asm = "tlbi\tvmalls12e1is"; break;
798        }
799        break;
800      case 6:
801        switch (Op2Val) {
802        default:
803          break;
804        case 0: Asm = "tlbi\talle3is"; break;
805        case 1: Asm = "tlbi\tvae3is"; break;
806        case 5: Asm = "tlbi\tvale3is"; break;
807        }
808        break;
809      }
810      break;
811    case 0:
812      switch (Op1Val) {
813      default:
814        break;
815      case 4:
816        switch (Op2Val) {
817        default:
818          break;
819        case 1: Asm = "tlbi\tipas2e1is"; break;
820        case 5: Asm = "tlbi\tipas2le1is"; break;
821        }
822        break;
823      }
824      break;
825    case 4:
826      switch (Op1Val) {
827      default:
828        break;
829      case 4:
830        switch (Op2Val) {
831        default:
832          break;
833        case 1: Asm = "tlbi\tipas2e1"; break;
834        case 5: Asm = "tlbi\tipas2le1"; break;
835        }
836        break;
837      }
838      break;
839    case 7:
840      switch (Op1Val) {
841      default:
842        break;
843      case 0:
844        switch (Op2Val) {
845        default:
846          break;
847        case 0: Asm = "tlbi\tvmalle1"; break;
848        case 1: Asm = "tlbi\tvae1"; break;
849        case 2: Asm = "tlbi\taside1"; break;
850        case 3: Asm = "tlbi\tvaae1"; break;
851        case 5: Asm = "tlbi\tvale1"; break;
852        case 7: Asm = "tlbi\tvaale1"; break;
853        }
854        break;
855      case 4:
856        switch (Op2Val) {
857        default:
858          break;
859        case 0: Asm = "tlbi\talle2"; break;
860        case 1: Asm = "tlbi\tvae2"; break;
861        case 4: Asm = "tlbi\talle1"; break;
862        case 5: Asm = "tlbi\tvale2"; break;
863        case 6: Asm = "tlbi\tvmalls12e1"; break;
864        }
865        break;
866      case 6:
867        switch (Op2Val) {
868        default:
869          break;
870        case 0: Asm = "tlbi\talle3"; break;
871        case 1: Asm = "tlbi\tvae3";  break;
872        case 5: Asm = "tlbi\tvale3"; break;
873        }
874        break;
875      }
876      break;
877    }
878  }
879
880  if (Asm) {
881    unsigned Reg = MI->getOperand(4).getReg();
882
883    O << '\t' << Asm;
884    if (StringRef(Asm).lower().find("all") == StringRef::npos)
885      O << ", " << getRegisterName(Reg);
886  }
887
888  return Asm != nullptr;
889}
890
891void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
892                                      raw_ostream &O) {
893  const MCOperand &Op = MI->getOperand(OpNo);
894  if (Op.isReg()) {
895    unsigned Reg = Op.getReg();
896    O << getRegisterName(Reg);
897  } else if (Op.isImm()) {
898    O << '#' << Op.getImm();
899  } else {
900    assert(Op.isExpr() && "unknown operand kind in printOperand");
901    O << *Op.getExpr();
902  }
903}
904
905void AArch64InstPrinter::printHexImm(const MCInst *MI, unsigned OpNo,
906                                     raw_ostream &O) {
907  const MCOperand &Op = MI->getOperand(OpNo);
908  O << format("#%#llx", Op.getImm());
909}
910
911void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
912                                             unsigned Imm, raw_ostream &O) {
913  const MCOperand &Op = MI->getOperand(OpNo);
914  if (Op.isReg()) {
915    unsigned Reg = Op.getReg();
916    if (Reg == AArch64::XZR)
917      O << "#" << Imm;
918    else
919      O << getRegisterName(Reg);
920  } else
921    llvm_unreachable("unknown operand kind in printPostIncOperand64");
922}
923
924void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
925                                          raw_ostream &O) {
926  const MCOperand &Op = MI->getOperand(OpNo);
927  assert(Op.isReg() && "Non-register vreg operand!");
928  unsigned Reg = Op.getReg();
929  O << getRegisterName(Reg, AArch64::vreg);
930}
931
932void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
933                                           raw_ostream &O) {
934  const MCOperand &Op = MI->getOperand(OpNo);
935  assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
936  O << "c" << Op.getImm();
937}
938
939void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
940                                        raw_ostream &O) {
941  const MCOperand &MO = MI->getOperand(OpNum);
942  if (MO.isImm()) {
943    unsigned Val = (MO.getImm() & 0xfff);
944    assert(Val == MO.getImm() && "Add/sub immediate out of range!");
945    unsigned Shift =
946        AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
947    O << '#' << Val;
948    if (Shift != 0)
949      printShifter(MI, OpNum + 1, O);
950
951    if (CommentStream)
952      *CommentStream << '=' << (Val << Shift) << '\n';
953  } else {
954    assert(MO.isExpr() && "Unexpected operand type!");
955    O << *MO.getExpr();
956    printShifter(MI, OpNum + 1, O);
957  }
958}
959
960void AArch64InstPrinter::printLogicalImm32(const MCInst *MI, unsigned OpNum,
961                                           raw_ostream &O) {
962  uint64_t Val = MI->getOperand(OpNum).getImm();
963  O << "#0x";
964  O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 32));
965}
966
967void AArch64InstPrinter::printLogicalImm64(const MCInst *MI, unsigned OpNum,
968                                           raw_ostream &O) {
969  uint64_t Val = MI->getOperand(OpNum).getImm();
970  O << "#0x";
971  O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 64));
972}
973
974void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
975                                      raw_ostream &O) {
976  unsigned Val = MI->getOperand(OpNum).getImm();
977  // LSL #0 should not be printed.
978  if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL &&
979      AArch64_AM::getShiftValue(Val) == 0)
980    return;
981  O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val))
982    << " #" << AArch64_AM::getShiftValue(Val);
983}
984
985void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
986                                              raw_ostream &O) {
987  O << getRegisterName(MI->getOperand(OpNum).getReg());
988  printShifter(MI, OpNum + 1, O);
989}
990
991void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
992                                               raw_ostream &O) {
993  O << getRegisterName(MI->getOperand(OpNum).getReg());
994  printArithExtend(MI, OpNum + 1, O);
995}
996
997void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
998                                          raw_ostream &O) {
999  unsigned Val = MI->getOperand(OpNum).getImm();
1000  AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val);
1001  unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val);
1002
1003  // If the destination or first source register operand is [W]SP, print
1004  // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1005  // all.
1006  if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
1007    unsigned Dest = MI->getOperand(0).getReg();
1008    unsigned Src1 = MI->getOperand(1).getReg();
1009    if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1010          ExtType == AArch64_AM::UXTX) ||
1011         ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
1012          ExtType == AArch64_AM::UXTW) ) {
1013      if (ShiftVal != 0)
1014        O << ", lsl #" << ShiftVal;
1015      return;
1016    }
1017  }
1018  O << ", " << AArch64_AM::getShiftExtendName(ExtType);
1019  if (ShiftVal != 0)
1020    O << " #" << ShiftVal;
1021}
1022
1023void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
1024                                        raw_ostream &O, char SrcRegKind,
1025                                        unsigned Width) {
1026  unsigned SignExtend = MI->getOperand(OpNum).getImm();
1027  unsigned DoShift = MI->getOperand(OpNum + 1).getImm();
1028
1029  // sxtw, sxtx, uxtw or lsl (== uxtx)
1030  bool IsLSL = !SignExtend && SrcRegKind == 'x';
1031  if (IsLSL)
1032    O << "lsl";
1033  else
1034    O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
1035
1036  if (DoShift || IsLSL)
1037    O << " #" << Log2_32(Width / 8);
1038}
1039
1040void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1041                                       raw_ostream &O) {
1042  AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1043  O << AArch64CC::getCondCodeName(CC);
1044}
1045
1046void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
1047                                              raw_ostream &O) {
1048  AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1049  O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC));
1050}
1051
1052void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1053                                        raw_ostream &O) {
1054  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
1055}
1056
1057template<int Scale>
1058void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1059                                       raw_ostream &O) {
1060  O << '#' << Scale * MI->getOperand(OpNum).getImm();
1061}
1062
1063void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
1064                                           unsigned Scale, raw_ostream &O) {
1065  const MCOperand MO = MI->getOperand(OpNum);
1066  if (MO.isImm()) {
1067    O << "#" << (MO.getImm() * Scale);
1068  } else {
1069    assert(MO.isExpr() && "Unexpected operand type!");
1070    O << *MO.getExpr();
1071  }
1072}
1073
1074void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1075                                          unsigned Scale, raw_ostream &O) {
1076  const MCOperand MO1 = MI->getOperand(OpNum + 1);
1077  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
1078  if (MO1.isImm()) {
1079      O << ", #" << (MO1.getImm() * Scale);
1080  } else {
1081    assert(MO1.isExpr() && "Unexpected operand type!");
1082    O << ", " << *MO1.getExpr();
1083  }
1084  O << ']';
1085}
1086
1087void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1088                                         raw_ostream &O) {
1089  unsigned prfop = MI->getOperand(OpNum).getImm();
1090  bool Valid;
1091  StringRef Name = AArch64PRFM::PRFMMapper().toString(prfop, Valid);
1092  if (Valid)
1093    O << Name;
1094  else
1095    O << '#' << prfop;
1096}
1097
1098void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1099                                           raw_ostream &O) {
1100  const MCOperand &MO = MI->getOperand(OpNum);
1101  float FPImm =
1102      MO.isFPImm() ? MO.getFPImm() : AArch64_AM::getFPImmFloat(MO.getImm());
1103
1104  // 8 decimal places are enough to perfectly represent permitted floats.
1105  O << format("#%.8f", FPImm);
1106}
1107
1108static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
1109  while (Stride--) {
1110    switch (Reg) {
1111    default:
1112      llvm_unreachable("Vector register expected!");
1113    case AArch64::Q0:  Reg = AArch64::Q1;  break;
1114    case AArch64::Q1:  Reg = AArch64::Q2;  break;
1115    case AArch64::Q2:  Reg = AArch64::Q3;  break;
1116    case AArch64::Q3:  Reg = AArch64::Q4;  break;
1117    case AArch64::Q4:  Reg = AArch64::Q5;  break;
1118    case AArch64::Q5:  Reg = AArch64::Q6;  break;
1119    case AArch64::Q6:  Reg = AArch64::Q7;  break;
1120    case AArch64::Q7:  Reg = AArch64::Q8;  break;
1121    case AArch64::Q8:  Reg = AArch64::Q9;  break;
1122    case AArch64::Q9:  Reg = AArch64::Q10; break;
1123    case AArch64::Q10: Reg = AArch64::Q11; break;
1124    case AArch64::Q11: Reg = AArch64::Q12; break;
1125    case AArch64::Q12: Reg = AArch64::Q13; break;
1126    case AArch64::Q13: Reg = AArch64::Q14; break;
1127    case AArch64::Q14: Reg = AArch64::Q15; break;
1128    case AArch64::Q15: Reg = AArch64::Q16; break;
1129    case AArch64::Q16: Reg = AArch64::Q17; break;
1130    case AArch64::Q17: Reg = AArch64::Q18; break;
1131    case AArch64::Q18: Reg = AArch64::Q19; break;
1132    case AArch64::Q19: Reg = AArch64::Q20; break;
1133    case AArch64::Q20: Reg = AArch64::Q21; break;
1134    case AArch64::Q21: Reg = AArch64::Q22; break;
1135    case AArch64::Q22: Reg = AArch64::Q23; break;
1136    case AArch64::Q23: Reg = AArch64::Q24; break;
1137    case AArch64::Q24: Reg = AArch64::Q25; break;
1138    case AArch64::Q25: Reg = AArch64::Q26; break;
1139    case AArch64::Q26: Reg = AArch64::Q27; break;
1140    case AArch64::Q27: Reg = AArch64::Q28; break;
1141    case AArch64::Q28: Reg = AArch64::Q29; break;
1142    case AArch64::Q29: Reg = AArch64::Q30; break;
1143    case AArch64::Q30: Reg = AArch64::Q31; break;
1144    // Vector lists can wrap around.
1145    case AArch64::Q31:
1146      Reg = AArch64::Q0;
1147      break;
1148    }
1149  }
1150  return Reg;
1151}
1152
1153void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1154                                         raw_ostream &O,
1155                                         StringRef LayoutSuffix) {
1156  unsigned Reg = MI->getOperand(OpNum).getReg();
1157
1158  O << "{ ";
1159
1160  // Work out how many registers there are in the list (if there is an actual
1161  // list).
1162  unsigned NumRegs = 1;
1163  if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1164      MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
1165    NumRegs = 2;
1166  else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1167           MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1168    NumRegs = 3;
1169  else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1170           MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))
1171    NumRegs = 4;
1172
1173  // Now forget about the list and find out what the first register is.
1174  if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1175    Reg = FirstReg;
1176  else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1177    Reg = FirstReg;
1178
1179  // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1180  // printing (otherwise getRegisterName fails).
1181  if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1182    const MCRegisterClass &FPR128RC =
1183        MRI.getRegClass(AArch64::FPR128RegClassID);
1184    Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1185  }
1186
1187  for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
1188    O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
1189    if (i + 1 != NumRegs)
1190      O << ", ";
1191  }
1192
1193  O << " }";
1194}
1195
1196void AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
1197                                                        unsigned OpNum,
1198                                                        raw_ostream &O) {
1199  printVectorList(MI, OpNum, O, "");
1200}
1201
1202template <unsigned NumLanes, char LaneKind>
1203void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
1204                                              raw_ostream &O) {
1205  std::string Suffix(".");
1206  if (NumLanes)
1207    Suffix += itostr(NumLanes) + LaneKind;
1208  else
1209    Suffix += LaneKind;
1210
1211  printVectorList(MI, OpNum, O, Suffix);
1212}
1213
1214void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1215                                          raw_ostream &O) {
1216  O << "[" << MI->getOperand(OpNum).getImm() << "]";
1217}
1218
1219void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, unsigned OpNum,
1220                                           raw_ostream &O) {
1221  const MCOperand &Op = MI->getOperand(OpNum);
1222
1223  // If the label has already been resolved to an immediate offset (say, when
1224  // we're running the disassembler), just print the immediate.
1225  if (Op.isImm()) {
1226    O << "#" << (Op.getImm() << 2);
1227    return;
1228  }
1229
1230  // If the branch target is simply an address then print it in hex.
1231  const MCConstantExpr *BranchTarget =
1232      dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1233  int64_t Address;
1234  if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
1235    O << "0x";
1236    O.write_hex(Address);
1237  } else {
1238    // Otherwise, just print the expression.
1239    O << *MI->getOperand(OpNum).getExpr();
1240  }
1241}
1242
1243void AArch64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum,
1244                                        raw_ostream &O) {
1245  const MCOperand &Op = MI->getOperand(OpNum);
1246
1247  // If the label has already been resolved to an immediate offset (say, when
1248  // we're running the disassembler), just print the immediate.
1249  if (Op.isImm()) {
1250    O << "#" << (Op.getImm() << 12);
1251    return;
1252  }
1253
1254  // Otherwise, just print the expression.
1255  O << *MI->getOperand(OpNum).getExpr();
1256}
1257
1258void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
1259                                            raw_ostream &O) {
1260  unsigned Val = MI->getOperand(OpNo).getImm();
1261  unsigned Opcode = MI->getOpcode();
1262
1263  bool Valid;
1264  StringRef Name;
1265  if (Opcode == AArch64::ISB)
1266    Name = AArch64ISB::ISBMapper().toString(Val, Valid);
1267  else
1268    Name = AArch64DB::DBarrierMapper().toString(Val, Valid);
1269  if (Valid)
1270    O << Name;
1271  else
1272    O << "#" << Val;
1273}
1274
1275void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
1276                                                raw_ostream &O) {
1277  unsigned Val = MI->getOperand(OpNo).getImm();
1278
1279  bool Valid;
1280  auto Mapper = AArch64SysReg::MRSMapper(getAvailableFeatures());
1281  std::string Name = Mapper.toString(Val, Valid);
1282
1283  if (Valid)
1284    O << StringRef(Name).upper();
1285}
1286
1287void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
1288                                                raw_ostream &O) {
1289  unsigned Val = MI->getOperand(OpNo).getImm();
1290
1291  bool Valid;
1292  auto Mapper = AArch64SysReg::MSRMapper(getAvailableFeatures());
1293  std::string Name = Mapper.toString(Val, Valid);
1294
1295  if (Valid)
1296    O << StringRef(Name).upper();
1297}
1298
1299void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
1300                                                raw_ostream &O) {
1301  unsigned Val = MI->getOperand(OpNo).getImm();
1302
1303  bool Valid;
1304  StringRef Name = AArch64PState::PStateMapper().toString(Val, Valid);
1305  if (Valid)
1306    O << StringRef(Name.str()).upper();
1307  else
1308    O << "#" << Val;
1309}
1310
1311void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
1312                                                raw_ostream &O) {
1313  unsigned RawVal = MI->getOperand(OpNo).getImm();
1314  uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
1315  O << format("#%#016llx", Val);
1316}
1317