172062f5744557e270a38192554c3126ea5f97434Tim Northover//===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===// 272062f5744557e270a38192554c3126ea5f97434Tim Northover// 372062f5744557e270a38192554c3126ea5f97434Tim Northover// The LLVM Compiler Infrastructure 472062f5744557e270a38192554c3126ea5f97434Tim Northover// 572062f5744557e270a38192554c3126ea5f97434Tim Northover// This file is distributed under the University of Illinois Open Source 672062f5744557e270a38192554c3126ea5f97434Tim Northover// License. See LICENSE.TXT for details. 772062f5744557e270a38192554c3126ea5f97434Tim Northover// 872062f5744557e270a38192554c3126ea5f97434Tim Northover//===----------------------------------------------------------------------===// 972062f5744557e270a38192554c3126ea5f97434Tim Northover// 1072062f5744557e270a38192554c3126ea5f97434Tim Northover// This file provides AArch64 specific target descriptions. 1172062f5744557e270a38192554c3126ea5f97434Tim Northover// 1272062f5744557e270a38192554c3126ea5f97434Tim Northover//===----------------------------------------------------------------------===// 1372062f5744557e270a38192554c3126ea5f97434Tim Northover 14dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#ifndef AArch64MCTARGETDESC_H 15dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#define AArch64MCTARGETDESC_H 1672062f5744557e270a38192554c3126ea5f97434Tim Northover 1772062f5744557e270a38192554c3126ea5f97434Tim Northover#include "llvm/Support/DataTypes.h" 18dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#include <string> 1972062f5744557e270a38192554c3126ea5f97434Tim Northover 2072062f5744557e270a38192554c3126ea5f97434Tim Northovernamespace llvm { 2172062f5744557e270a38192554c3126ea5f97434Tim Northoverclass MCAsmBackend; 2272062f5744557e270a38192554c3126ea5f97434Tim Northoverclass MCCodeEmitter; 2372062f5744557e270a38192554c3126ea5f97434Tim Northoverclass MCContext; 2472062f5744557e270a38192554c3126ea5f97434Tim Northoverclass MCInstrInfo; 2572062f5744557e270a38192554c3126ea5f97434Tim Northoverclass MCRegisterInfo; 26dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesclass MCObjectWriter; 2772062f5744557e270a38192554c3126ea5f97434Tim Northoverclass MCSubtargetInfo; 2872062f5744557e270a38192554c3126ea5f97434Tim Northoverclass StringRef; 2972062f5744557e270a38192554c3126ea5f97434Tim Northoverclass Target; 3072062f5744557e270a38192554c3126ea5f97434Tim Northoverclass raw_ostream; 3172062f5744557e270a38192554c3126ea5f97434Tim Northover 3236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hinesextern Target TheAArch64leTarget; 3336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hinesextern Target TheAArch64beTarget; 34dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesextern Target TheARM64leTarget; 35dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesextern Target TheARM64beTarget; 3672062f5744557e270a38192554c3126ea5f97434Tim Northover 3772062f5744557e270a38192554c3126ea5f97434Tim NorthoverMCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII, 38dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const MCRegisterInfo &MRI, 39dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const MCSubtargetInfo &STI, 40dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MCContext &Ctx); 41dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen HinesMCAsmBackend *createAArch64leAsmBackend(const Target &T, 42dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const MCRegisterInfo &MRI, StringRef TT, 43dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines StringRef CPU); 44dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen HinesMCAsmBackend *createAArch64beAsmBackend(const Target &T, 45dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const MCRegisterInfo &MRI, StringRef TT, 46dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines StringRef CPU); 4772062f5744557e270a38192554c3126ea5f97434Tim Northover 48dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen HinesMCObjectWriter *createAArch64ELFObjectWriter(raw_ostream &OS, uint8_t OSABI, 4936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines bool IsLittleEndian); 5072062f5744557e270a38192554c3126ea5f97434Tim Northover 51dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen HinesMCObjectWriter *createAArch64MachObjectWriter(raw_ostream &OS, uint32_t CPUType, 52dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines uint32_t CPUSubtype); 5372062f5744557e270a38192554c3126ea5f97434Tim Northover 5472062f5744557e270a38192554c3126ea5f97434Tim Northover} // End llvm namespace 5572062f5744557e270a38192554c3126ea5f97434Tim Northover 5672062f5744557e270a38192554c3126ea5f97434Tim Northover// Defines symbolic names for AArch64 registers. This defines a mapping from 5772062f5744557e270a38192554c3126ea5f97434Tim Northover// register name to register number. 5872062f5744557e270a38192554c3126ea5f97434Tim Northover// 5972062f5744557e270a38192554c3126ea5f97434Tim Northover#define GET_REGINFO_ENUM 6072062f5744557e270a38192554c3126ea5f97434Tim Northover#include "AArch64GenRegisterInfo.inc" 6172062f5744557e270a38192554c3126ea5f97434Tim Northover 6272062f5744557e270a38192554c3126ea5f97434Tim Northover// Defines symbolic names for the AArch64 instructions. 6372062f5744557e270a38192554c3126ea5f97434Tim Northover// 6472062f5744557e270a38192554c3126ea5f97434Tim Northover#define GET_INSTRINFO_ENUM 6572062f5744557e270a38192554c3126ea5f97434Tim Northover#include "AArch64GenInstrInfo.inc" 6672062f5744557e270a38192554c3126ea5f97434Tim Northover 6772062f5744557e270a38192554c3126ea5f97434Tim Northover#define GET_SUBTARGETINFO_ENUM 6872062f5744557e270a38192554c3126ea5f97434Tim Northover#include "AArch64GenSubtargetInfo.inc" 6972062f5744557e270a38192554c3126ea5f97434Tim Northover 7072062f5744557e270a38192554c3126ea5f97434Tim Northover#endif 71