1//===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides basic encoding and assembly information for AArch64.
11//
12//===----------------------------------------------------------------------===//
13#include "AArch64BaseInfo.h"
14#include "llvm/ADT/APFloat.h"
15#include "llvm/ADT/SmallVector.h"
16#include "llvm/ADT/StringExtras.h"
17#include "llvm/Support/Regex.h"
18
19using namespace llvm;
20
21StringRef AArch64NamedImmMapper::toString(uint32_t Value, bool &Valid) const {
22  for (unsigned i = 0; i < NumPairs; ++i) {
23    if (Pairs[i].Value == Value) {
24      Valid = true;
25      return Pairs[i].Name;
26    }
27  }
28
29  Valid = false;
30  return StringRef();
31}
32
33uint32_t AArch64NamedImmMapper::fromString(StringRef Name, bool &Valid) const {
34  std::string LowerCaseName = Name.lower();
35  for (unsigned i = 0; i < NumPairs; ++i) {
36    if (Pairs[i].Name == LowerCaseName) {
37      Valid = true;
38      return Pairs[i].Value;
39    }
40  }
41
42  Valid = false;
43  return -1;
44}
45
46bool AArch64NamedImmMapper::validImm(uint32_t Value) const {
47  return Value < TooBigImm;
48}
49
50const AArch64NamedImmMapper::Mapping AArch64AT::ATMapper::ATPairs[] = {
51  {"s1e1r", S1E1R},
52  {"s1e2r", S1E2R},
53  {"s1e3r", S1E3R},
54  {"s1e1w", S1E1W},
55  {"s1e2w", S1E2W},
56  {"s1e3w", S1E3W},
57  {"s1e0r", S1E0R},
58  {"s1e0w", S1E0W},
59  {"s12e1r", S12E1R},
60  {"s12e1w", S12E1W},
61  {"s12e0r", S12E0R},
62  {"s12e0w", S12E0W},
63};
64
65AArch64AT::ATMapper::ATMapper()
66  : AArch64NamedImmMapper(ATPairs, 0) {}
67
68const AArch64NamedImmMapper::Mapping AArch64DB::DBarrierMapper::DBarrierPairs[] = {
69  {"oshld", OSHLD},
70  {"oshst", OSHST},
71  {"osh", OSH},
72  {"nshld", NSHLD},
73  {"nshst", NSHST},
74  {"nsh", NSH},
75  {"ishld", ISHLD},
76  {"ishst", ISHST},
77  {"ish", ISH},
78  {"ld", LD},
79  {"st", ST},
80  {"sy", SY}
81};
82
83AArch64DB::DBarrierMapper::DBarrierMapper()
84  : AArch64NamedImmMapper(DBarrierPairs, 16u) {}
85
86const AArch64NamedImmMapper::Mapping AArch64DC::DCMapper::DCPairs[] = {
87  {"zva", ZVA},
88  {"ivac", IVAC},
89  {"isw", ISW},
90  {"cvac", CVAC},
91  {"csw", CSW},
92  {"cvau", CVAU},
93  {"civac", CIVAC},
94  {"cisw", CISW}
95};
96
97AArch64DC::DCMapper::DCMapper()
98  : AArch64NamedImmMapper(DCPairs, 0) {}
99
100const AArch64NamedImmMapper::Mapping AArch64IC::ICMapper::ICPairs[] = {
101  {"ialluis",  IALLUIS},
102  {"iallu", IALLU},
103  {"ivau", IVAU}
104};
105
106AArch64IC::ICMapper::ICMapper()
107  : AArch64NamedImmMapper(ICPairs, 0) {}
108
109const AArch64NamedImmMapper::Mapping AArch64ISB::ISBMapper::ISBPairs[] = {
110  {"sy",  SY},
111};
112
113AArch64ISB::ISBMapper::ISBMapper()
114  : AArch64NamedImmMapper(ISBPairs, 16) {}
115
116const AArch64NamedImmMapper::Mapping AArch64PRFM::PRFMMapper::PRFMPairs[] = {
117  {"pldl1keep", PLDL1KEEP},
118  {"pldl1strm", PLDL1STRM},
119  {"pldl2keep", PLDL2KEEP},
120  {"pldl2strm", PLDL2STRM},
121  {"pldl3keep", PLDL3KEEP},
122  {"pldl3strm", PLDL3STRM},
123  {"plil1keep", PLIL1KEEP},
124  {"plil1strm", PLIL1STRM},
125  {"plil2keep", PLIL2KEEP},
126  {"plil2strm", PLIL2STRM},
127  {"plil3keep", PLIL3KEEP},
128  {"plil3strm", PLIL3STRM},
129  {"pstl1keep", PSTL1KEEP},
130  {"pstl1strm", PSTL1STRM},
131  {"pstl2keep", PSTL2KEEP},
132  {"pstl2strm", PSTL2STRM},
133  {"pstl3keep", PSTL3KEEP},
134  {"pstl3strm", PSTL3STRM}
135};
136
137AArch64PRFM::PRFMMapper::PRFMMapper()
138  : AArch64NamedImmMapper(PRFMPairs, 32) {}
139
140const AArch64NamedImmMapper::Mapping AArch64PState::PStateMapper::PStatePairs[] = {
141  {"spsel", SPSel},
142  {"daifset", DAIFSet},
143  {"daifclr", DAIFClr}
144};
145
146AArch64PState::PStateMapper::PStateMapper()
147  : AArch64NamedImmMapper(PStatePairs, 0) {}
148
149const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSPairs[] = {
150  {"mdccsr_el0", MDCCSR_EL0},
151  {"dbgdtrrx_el0", DBGDTRRX_EL0},
152  {"mdrar_el1", MDRAR_EL1},
153  {"oslsr_el1", OSLSR_EL1},
154  {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1},
155  {"pmceid0_el0", PMCEID0_EL0},
156  {"pmceid1_el0", PMCEID1_EL0},
157  {"midr_el1", MIDR_EL1},
158  {"ccsidr_el1", CCSIDR_EL1},
159  {"clidr_el1", CLIDR_EL1},
160  {"ctr_el0", CTR_EL0},
161  {"mpidr_el1", MPIDR_EL1},
162  {"revidr_el1", REVIDR_EL1},
163  {"aidr_el1", AIDR_EL1},
164  {"dczid_el0", DCZID_EL0},
165  {"id_pfr0_el1", ID_PFR0_EL1},
166  {"id_pfr1_el1", ID_PFR1_EL1},
167  {"id_dfr0_el1", ID_DFR0_EL1},
168  {"id_afr0_el1", ID_AFR0_EL1},
169  {"id_mmfr0_el1", ID_MMFR0_EL1},
170  {"id_mmfr1_el1", ID_MMFR1_EL1},
171  {"id_mmfr2_el1", ID_MMFR2_EL1},
172  {"id_mmfr3_el1", ID_MMFR3_EL1},
173  {"id_isar0_el1", ID_ISAR0_EL1},
174  {"id_isar1_el1", ID_ISAR1_EL1},
175  {"id_isar2_el1", ID_ISAR2_EL1},
176  {"id_isar3_el1", ID_ISAR3_EL1},
177  {"id_isar4_el1", ID_ISAR4_EL1},
178  {"id_isar5_el1", ID_ISAR5_EL1},
179  {"id_aa64pfr0_el1", ID_A64PFR0_EL1},
180  {"id_aa64pfr1_el1", ID_A64PFR1_EL1},
181  {"id_aa64dfr0_el1", ID_A64DFR0_EL1},
182  {"id_aa64dfr1_el1", ID_A64DFR1_EL1},
183  {"id_aa64afr0_el1", ID_A64AFR0_EL1},
184  {"id_aa64afr1_el1", ID_A64AFR1_EL1},
185  {"id_aa64isar0_el1", ID_A64ISAR0_EL1},
186  {"id_aa64isar1_el1", ID_A64ISAR1_EL1},
187  {"id_aa64mmfr0_el1", ID_A64MMFR0_EL1},
188  {"id_aa64mmfr1_el1", ID_A64MMFR1_EL1},
189  {"mvfr0_el1", MVFR0_EL1},
190  {"mvfr1_el1", MVFR1_EL1},
191  {"mvfr2_el1", MVFR2_EL1},
192  {"rvbar_el1", RVBAR_EL1},
193  {"rvbar_el2", RVBAR_EL2},
194  {"rvbar_el3", RVBAR_EL3},
195  {"isr_el1", ISR_EL1},
196  {"cntpct_el0", CNTPCT_EL0},
197  {"cntvct_el0", CNTVCT_EL0},
198
199  // Trace registers
200  {"trcstatr", TRCSTATR},
201  {"trcidr8", TRCIDR8},
202  {"trcidr9", TRCIDR9},
203  {"trcidr10", TRCIDR10},
204  {"trcidr11", TRCIDR11},
205  {"trcidr12", TRCIDR12},
206  {"trcidr13", TRCIDR13},
207  {"trcidr0", TRCIDR0},
208  {"trcidr1", TRCIDR1},
209  {"trcidr2", TRCIDR2},
210  {"trcidr3", TRCIDR3},
211  {"trcidr4", TRCIDR4},
212  {"trcidr5", TRCIDR5},
213  {"trcidr6", TRCIDR6},
214  {"trcidr7", TRCIDR7},
215  {"trcoslsr", TRCOSLSR},
216  {"trcpdsr", TRCPDSR},
217  {"trcdevaff0", TRCDEVAFF0},
218  {"trcdevaff1", TRCDEVAFF1},
219  {"trclsr", TRCLSR},
220  {"trcauthstatus", TRCAUTHSTATUS},
221  {"trcdevarch", TRCDEVARCH},
222  {"trcdevid", TRCDEVID},
223  {"trcdevtype", TRCDEVTYPE},
224  {"trcpidr4", TRCPIDR4},
225  {"trcpidr5", TRCPIDR5},
226  {"trcpidr6", TRCPIDR6},
227  {"trcpidr7", TRCPIDR7},
228  {"trcpidr0", TRCPIDR0},
229  {"trcpidr1", TRCPIDR1},
230  {"trcpidr2", TRCPIDR2},
231  {"trcpidr3", TRCPIDR3},
232  {"trccidr0", TRCCIDR0},
233  {"trccidr1", TRCCIDR1},
234  {"trccidr2", TRCCIDR2},
235  {"trccidr3", TRCCIDR3},
236
237  // GICv3 registers
238  {"icc_iar1_el1", ICC_IAR1_EL1},
239  {"icc_iar0_el1", ICC_IAR0_EL1},
240  {"icc_hppir1_el1", ICC_HPPIR1_EL1},
241  {"icc_hppir0_el1", ICC_HPPIR0_EL1},
242  {"icc_rpr_el1", ICC_RPR_EL1},
243  {"ich_vtr_el2", ICH_VTR_EL2},
244  {"ich_eisr_el2", ICH_EISR_EL2},
245  {"ich_elsr_el2", ICH_ELSR_EL2}
246};
247
248AArch64SysReg::MRSMapper::MRSMapper(uint64_t FeatureBits)
249  : SysRegMapper(FeatureBits) {
250    InstPairs = &MRSPairs[0];
251    NumInstPairs = llvm::array_lengthof(MRSPairs);
252}
253
254const AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRPairs[] = {
255  {"dbgdtrtx_el0", DBGDTRTX_EL0},
256  {"oslar_el1", OSLAR_EL1},
257  {"pmswinc_el0", PMSWINC_EL0},
258
259  // Trace registers
260  {"trcoslar", TRCOSLAR},
261  {"trclar", TRCLAR},
262
263  // GICv3 registers
264  {"icc_eoir1_el1", ICC_EOIR1_EL1},
265  {"icc_eoir0_el1", ICC_EOIR0_EL1},
266  {"icc_dir_el1", ICC_DIR_EL1},
267  {"icc_sgi1r_el1", ICC_SGI1R_EL1},
268  {"icc_asgi1r_el1", ICC_ASGI1R_EL1},
269  {"icc_sgi0r_el1", ICC_SGI0R_EL1}
270};
271
272AArch64SysReg::MSRMapper::MSRMapper(uint64_t FeatureBits)
273  : SysRegMapper(FeatureBits) {
274    InstPairs = &MSRPairs[0];
275    NumInstPairs = llvm::array_lengthof(MSRPairs);
276}
277
278
279const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegPairs[] = {
280  {"osdtrrx_el1", OSDTRRX_EL1},
281  {"osdtrtx_el1",  OSDTRTX_EL1},
282  {"teecr32_el1", TEECR32_EL1},
283  {"mdccint_el1", MDCCINT_EL1},
284  {"mdscr_el1", MDSCR_EL1},
285  {"dbgdtr_el0", DBGDTR_EL0},
286  {"oseccr_el1", OSECCR_EL1},
287  {"dbgvcr32_el2", DBGVCR32_EL2},
288  {"dbgbvr0_el1", DBGBVR0_EL1},
289  {"dbgbvr1_el1", DBGBVR1_EL1},
290  {"dbgbvr2_el1", DBGBVR2_EL1},
291  {"dbgbvr3_el1", DBGBVR3_EL1},
292  {"dbgbvr4_el1", DBGBVR4_EL1},
293  {"dbgbvr5_el1", DBGBVR5_EL1},
294  {"dbgbvr6_el1", DBGBVR6_EL1},
295  {"dbgbvr7_el1", DBGBVR7_EL1},
296  {"dbgbvr8_el1", DBGBVR8_EL1},
297  {"dbgbvr9_el1", DBGBVR9_EL1},
298  {"dbgbvr10_el1", DBGBVR10_EL1},
299  {"dbgbvr11_el1", DBGBVR11_EL1},
300  {"dbgbvr12_el1", DBGBVR12_EL1},
301  {"dbgbvr13_el1", DBGBVR13_EL1},
302  {"dbgbvr14_el1", DBGBVR14_EL1},
303  {"dbgbvr15_el1", DBGBVR15_EL1},
304  {"dbgbcr0_el1", DBGBCR0_EL1},
305  {"dbgbcr1_el1", DBGBCR1_EL1},
306  {"dbgbcr2_el1", DBGBCR2_EL1},
307  {"dbgbcr3_el1", DBGBCR3_EL1},
308  {"dbgbcr4_el1", DBGBCR4_EL1},
309  {"dbgbcr5_el1", DBGBCR5_EL1},
310  {"dbgbcr6_el1", DBGBCR6_EL1},
311  {"dbgbcr7_el1", DBGBCR7_EL1},
312  {"dbgbcr8_el1", DBGBCR8_EL1},
313  {"dbgbcr9_el1", DBGBCR9_EL1},
314  {"dbgbcr10_el1", DBGBCR10_EL1},
315  {"dbgbcr11_el1", DBGBCR11_EL1},
316  {"dbgbcr12_el1", DBGBCR12_EL1},
317  {"dbgbcr13_el1", DBGBCR13_EL1},
318  {"dbgbcr14_el1", DBGBCR14_EL1},
319  {"dbgbcr15_el1", DBGBCR15_EL1},
320  {"dbgwvr0_el1", DBGWVR0_EL1},
321  {"dbgwvr1_el1", DBGWVR1_EL1},
322  {"dbgwvr2_el1", DBGWVR2_EL1},
323  {"dbgwvr3_el1", DBGWVR3_EL1},
324  {"dbgwvr4_el1", DBGWVR4_EL1},
325  {"dbgwvr5_el1", DBGWVR5_EL1},
326  {"dbgwvr6_el1", DBGWVR6_EL1},
327  {"dbgwvr7_el1", DBGWVR7_EL1},
328  {"dbgwvr8_el1", DBGWVR8_EL1},
329  {"dbgwvr9_el1", DBGWVR9_EL1},
330  {"dbgwvr10_el1", DBGWVR10_EL1},
331  {"dbgwvr11_el1", DBGWVR11_EL1},
332  {"dbgwvr12_el1", DBGWVR12_EL1},
333  {"dbgwvr13_el1", DBGWVR13_EL1},
334  {"dbgwvr14_el1", DBGWVR14_EL1},
335  {"dbgwvr15_el1", DBGWVR15_EL1},
336  {"dbgwcr0_el1", DBGWCR0_EL1},
337  {"dbgwcr1_el1", DBGWCR1_EL1},
338  {"dbgwcr2_el1", DBGWCR2_EL1},
339  {"dbgwcr3_el1", DBGWCR3_EL1},
340  {"dbgwcr4_el1", DBGWCR4_EL1},
341  {"dbgwcr5_el1", DBGWCR5_EL1},
342  {"dbgwcr6_el1", DBGWCR6_EL1},
343  {"dbgwcr7_el1", DBGWCR7_EL1},
344  {"dbgwcr8_el1", DBGWCR8_EL1},
345  {"dbgwcr9_el1", DBGWCR9_EL1},
346  {"dbgwcr10_el1", DBGWCR10_EL1},
347  {"dbgwcr11_el1", DBGWCR11_EL1},
348  {"dbgwcr12_el1", DBGWCR12_EL1},
349  {"dbgwcr13_el1", DBGWCR13_EL1},
350  {"dbgwcr14_el1", DBGWCR14_EL1},
351  {"dbgwcr15_el1", DBGWCR15_EL1},
352  {"teehbr32_el1", TEEHBR32_EL1},
353  {"osdlr_el1", OSDLR_EL1},
354  {"dbgprcr_el1", DBGPRCR_EL1},
355  {"dbgclaimset_el1", DBGCLAIMSET_EL1},
356  {"dbgclaimclr_el1", DBGCLAIMCLR_EL1},
357  {"csselr_el1", CSSELR_EL1},
358  {"vpidr_el2", VPIDR_EL2},
359  {"vmpidr_el2", VMPIDR_EL2},
360  {"sctlr_el1", SCTLR_EL1},
361  {"sctlr_el2", SCTLR_EL2},
362  {"sctlr_el3", SCTLR_EL3},
363  {"actlr_el1", ACTLR_EL1},
364  {"actlr_el2", ACTLR_EL2},
365  {"actlr_el3", ACTLR_EL3},
366  {"cpacr_el1", CPACR_EL1},
367  {"hcr_el2", HCR_EL2},
368  {"scr_el3", SCR_EL3},
369  {"mdcr_el2", MDCR_EL2},
370  {"sder32_el3", SDER32_EL3},
371  {"cptr_el2", CPTR_EL2},
372  {"cptr_el3", CPTR_EL3},
373  {"hstr_el2", HSTR_EL2},
374  {"hacr_el2", HACR_EL2},
375  {"mdcr_el3", MDCR_EL3},
376  {"ttbr0_el1", TTBR0_EL1},
377  {"ttbr0_el2", TTBR0_EL2},
378  {"ttbr0_el3", TTBR0_EL3},
379  {"ttbr1_el1", TTBR1_EL1},
380  {"tcr_el1", TCR_EL1},
381  {"tcr_el2", TCR_EL2},
382  {"tcr_el3", TCR_EL3},
383  {"vttbr_el2", VTTBR_EL2},
384  {"vtcr_el2", VTCR_EL2},
385  {"dacr32_el2", DACR32_EL2},
386  {"spsr_el1", SPSR_EL1},
387  {"spsr_el2", SPSR_EL2},
388  {"spsr_el3", SPSR_EL3},
389  {"elr_el1", ELR_EL1},
390  {"elr_el2", ELR_EL2},
391  {"elr_el3", ELR_EL3},
392  {"sp_el0", SP_EL0},
393  {"sp_el1", SP_EL1},
394  {"sp_el2", SP_EL2},
395  {"spsel", SPSel},
396  {"nzcv", NZCV},
397  {"daif", DAIF},
398  {"currentel", CurrentEL},
399  {"spsr_irq", SPSR_irq},
400  {"spsr_abt", SPSR_abt},
401  {"spsr_und", SPSR_und},
402  {"spsr_fiq", SPSR_fiq},
403  {"fpcr", FPCR},
404  {"fpsr", FPSR},
405  {"dspsr_el0", DSPSR_EL0},
406  {"dlr_el0", DLR_EL0},
407  {"ifsr32_el2", IFSR32_EL2},
408  {"afsr0_el1", AFSR0_EL1},
409  {"afsr0_el2", AFSR0_EL2},
410  {"afsr0_el3", AFSR0_EL3},
411  {"afsr1_el1", AFSR1_EL1},
412  {"afsr1_el2", AFSR1_EL2},
413  {"afsr1_el3", AFSR1_EL3},
414  {"esr_el1", ESR_EL1},
415  {"esr_el2", ESR_EL2},
416  {"esr_el3", ESR_EL3},
417  {"fpexc32_el2", FPEXC32_EL2},
418  {"far_el1", FAR_EL1},
419  {"far_el2", FAR_EL2},
420  {"far_el3", FAR_EL3},
421  {"hpfar_el2", HPFAR_EL2},
422  {"par_el1", PAR_EL1},
423  {"pmcr_el0", PMCR_EL0},
424  {"pmcntenset_el0", PMCNTENSET_EL0},
425  {"pmcntenclr_el0", PMCNTENCLR_EL0},
426  {"pmovsclr_el0", PMOVSCLR_EL0},
427  {"pmselr_el0", PMSELR_EL0},
428  {"pmccntr_el0", PMCCNTR_EL0},
429  {"pmxevtyper_el0", PMXEVTYPER_EL0},
430  {"pmxevcntr_el0", PMXEVCNTR_EL0},
431  {"pmuserenr_el0", PMUSERENR_EL0},
432  {"pmintenset_el1", PMINTENSET_EL1},
433  {"pmintenclr_el1", PMINTENCLR_EL1},
434  {"pmovsset_el0", PMOVSSET_EL0},
435  {"mair_el1", MAIR_EL1},
436  {"mair_el2", MAIR_EL2},
437  {"mair_el3", MAIR_EL3},
438  {"amair_el1", AMAIR_EL1},
439  {"amair_el2", AMAIR_EL2},
440  {"amair_el3", AMAIR_EL3},
441  {"vbar_el1", VBAR_EL1},
442  {"vbar_el2", VBAR_EL2},
443  {"vbar_el3", VBAR_EL3},
444  {"rmr_el1", RMR_EL1},
445  {"rmr_el2", RMR_EL2},
446  {"rmr_el3", RMR_EL3},
447  {"contextidr_el1", CONTEXTIDR_EL1},
448  {"tpidr_el0", TPIDR_EL0},
449  {"tpidr_el2", TPIDR_EL2},
450  {"tpidr_el3", TPIDR_EL3},
451  {"tpidrro_el0", TPIDRRO_EL0},
452  {"tpidr_el1", TPIDR_EL1},
453  {"cntfrq_el0", CNTFRQ_EL0},
454  {"cntvoff_el2", CNTVOFF_EL2},
455  {"cntkctl_el1", CNTKCTL_EL1},
456  {"cnthctl_el2", CNTHCTL_EL2},
457  {"cntp_tval_el0", CNTP_TVAL_EL0},
458  {"cnthp_tval_el2", CNTHP_TVAL_EL2},
459  {"cntps_tval_el1", CNTPS_TVAL_EL1},
460  {"cntp_ctl_el0", CNTP_CTL_EL0},
461  {"cnthp_ctl_el2", CNTHP_CTL_EL2},
462  {"cntps_ctl_el1", CNTPS_CTL_EL1},
463  {"cntp_cval_el0", CNTP_CVAL_EL0},
464  {"cnthp_cval_el2", CNTHP_CVAL_EL2},
465  {"cntps_cval_el1", CNTPS_CVAL_EL1},
466  {"cntv_tval_el0", CNTV_TVAL_EL0},
467  {"cntv_ctl_el0", CNTV_CTL_EL0},
468  {"cntv_cval_el0", CNTV_CVAL_EL0},
469  {"pmevcntr0_el0", PMEVCNTR0_EL0},
470  {"pmevcntr1_el0", PMEVCNTR1_EL0},
471  {"pmevcntr2_el0", PMEVCNTR2_EL0},
472  {"pmevcntr3_el0", PMEVCNTR3_EL0},
473  {"pmevcntr4_el0", PMEVCNTR4_EL0},
474  {"pmevcntr5_el0", PMEVCNTR5_EL0},
475  {"pmevcntr6_el0", PMEVCNTR6_EL0},
476  {"pmevcntr7_el0", PMEVCNTR7_EL0},
477  {"pmevcntr8_el0", PMEVCNTR8_EL0},
478  {"pmevcntr9_el0", PMEVCNTR9_EL0},
479  {"pmevcntr10_el0", PMEVCNTR10_EL0},
480  {"pmevcntr11_el0", PMEVCNTR11_EL0},
481  {"pmevcntr12_el0", PMEVCNTR12_EL0},
482  {"pmevcntr13_el0", PMEVCNTR13_EL0},
483  {"pmevcntr14_el0", PMEVCNTR14_EL0},
484  {"pmevcntr15_el0", PMEVCNTR15_EL0},
485  {"pmevcntr16_el0", PMEVCNTR16_EL0},
486  {"pmevcntr17_el0", PMEVCNTR17_EL0},
487  {"pmevcntr18_el0", PMEVCNTR18_EL0},
488  {"pmevcntr19_el0", PMEVCNTR19_EL0},
489  {"pmevcntr20_el0", PMEVCNTR20_EL0},
490  {"pmevcntr21_el0", PMEVCNTR21_EL0},
491  {"pmevcntr22_el0", PMEVCNTR22_EL0},
492  {"pmevcntr23_el0", PMEVCNTR23_EL0},
493  {"pmevcntr24_el0", PMEVCNTR24_EL0},
494  {"pmevcntr25_el0", PMEVCNTR25_EL0},
495  {"pmevcntr26_el0", PMEVCNTR26_EL0},
496  {"pmevcntr27_el0", PMEVCNTR27_EL0},
497  {"pmevcntr28_el0", PMEVCNTR28_EL0},
498  {"pmevcntr29_el0", PMEVCNTR29_EL0},
499  {"pmevcntr30_el0", PMEVCNTR30_EL0},
500  {"pmccfiltr_el0", PMCCFILTR_EL0},
501  {"pmevtyper0_el0", PMEVTYPER0_EL0},
502  {"pmevtyper1_el0", PMEVTYPER1_EL0},
503  {"pmevtyper2_el0", PMEVTYPER2_EL0},
504  {"pmevtyper3_el0", PMEVTYPER3_EL0},
505  {"pmevtyper4_el0", PMEVTYPER4_EL0},
506  {"pmevtyper5_el0", PMEVTYPER5_EL0},
507  {"pmevtyper6_el0", PMEVTYPER6_EL0},
508  {"pmevtyper7_el0", PMEVTYPER7_EL0},
509  {"pmevtyper8_el0", PMEVTYPER8_EL0},
510  {"pmevtyper9_el0", PMEVTYPER9_EL0},
511  {"pmevtyper10_el0", PMEVTYPER10_EL0},
512  {"pmevtyper11_el0", PMEVTYPER11_EL0},
513  {"pmevtyper12_el0", PMEVTYPER12_EL0},
514  {"pmevtyper13_el0", PMEVTYPER13_EL0},
515  {"pmevtyper14_el0", PMEVTYPER14_EL0},
516  {"pmevtyper15_el0", PMEVTYPER15_EL0},
517  {"pmevtyper16_el0", PMEVTYPER16_EL0},
518  {"pmevtyper17_el0", PMEVTYPER17_EL0},
519  {"pmevtyper18_el0", PMEVTYPER18_EL0},
520  {"pmevtyper19_el0", PMEVTYPER19_EL0},
521  {"pmevtyper20_el0", PMEVTYPER20_EL0},
522  {"pmevtyper21_el0", PMEVTYPER21_EL0},
523  {"pmevtyper22_el0", PMEVTYPER22_EL0},
524  {"pmevtyper23_el0", PMEVTYPER23_EL0},
525  {"pmevtyper24_el0", PMEVTYPER24_EL0},
526  {"pmevtyper25_el0", PMEVTYPER25_EL0},
527  {"pmevtyper26_el0", PMEVTYPER26_EL0},
528  {"pmevtyper27_el0", PMEVTYPER27_EL0},
529  {"pmevtyper28_el0", PMEVTYPER28_EL0},
530  {"pmevtyper29_el0", PMEVTYPER29_EL0},
531  {"pmevtyper30_el0", PMEVTYPER30_EL0},
532
533  // Trace registers
534  {"trcprgctlr", TRCPRGCTLR},
535  {"trcprocselr", TRCPROCSELR},
536  {"trcconfigr", TRCCONFIGR},
537  {"trcauxctlr", TRCAUXCTLR},
538  {"trceventctl0r", TRCEVENTCTL0R},
539  {"trceventctl1r", TRCEVENTCTL1R},
540  {"trcstallctlr", TRCSTALLCTLR},
541  {"trctsctlr", TRCTSCTLR},
542  {"trcsyncpr", TRCSYNCPR},
543  {"trcccctlr", TRCCCCTLR},
544  {"trcbbctlr", TRCBBCTLR},
545  {"trctraceidr", TRCTRACEIDR},
546  {"trcqctlr", TRCQCTLR},
547  {"trcvictlr", TRCVICTLR},
548  {"trcviiectlr", TRCVIIECTLR},
549  {"trcvissctlr", TRCVISSCTLR},
550  {"trcvipcssctlr", TRCVIPCSSCTLR},
551  {"trcvdctlr", TRCVDCTLR},
552  {"trcvdsacctlr", TRCVDSACCTLR},
553  {"trcvdarcctlr", TRCVDARCCTLR},
554  {"trcseqevr0", TRCSEQEVR0},
555  {"trcseqevr1", TRCSEQEVR1},
556  {"trcseqevr2", TRCSEQEVR2},
557  {"trcseqrstevr", TRCSEQRSTEVR},
558  {"trcseqstr", TRCSEQSTR},
559  {"trcextinselr", TRCEXTINSELR},
560  {"trccntrldvr0", TRCCNTRLDVR0},
561  {"trccntrldvr1", TRCCNTRLDVR1},
562  {"trccntrldvr2", TRCCNTRLDVR2},
563  {"trccntrldvr3", TRCCNTRLDVR3},
564  {"trccntctlr0", TRCCNTCTLR0},
565  {"trccntctlr1", TRCCNTCTLR1},
566  {"trccntctlr2", TRCCNTCTLR2},
567  {"trccntctlr3", TRCCNTCTLR3},
568  {"trccntvr0", TRCCNTVR0},
569  {"trccntvr1", TRCCNTVR1},
570  {"trccntvr2", TRCCNTVR2},
571  {"trccntvr3", TRCCNTVR3},
572  {"trcimspec0", TRCIMSPEC0},
573  {"trcimspec1", TRCIMSPEC1},
574  {"trcimspec2", TRCIMSPEC2},
575  {"trcimspec3", TRCIMSPEC3},
576  {"trcimspec4", TRCIMSPEC4},
577  {"trcimspec5", TRCIMSPEC5},
578  {"trcimspec6", TRCIMSPEC6},
579  {"trcimspec7", TRCIMSPEC7},
580  {"trcrsctlr2", TRCRSCTLR2},
581  {"trcrsctlr3", TRCRSCTLR3},
582  {"trcrsctlr4", TRCRSCTLR4},
583  {"trcrsctlr5", TRCRSCTLR5},
584  {"trcrsctlr6", TRCRSCTLR6},
585  {"trcrsctlr7", TRCRSCTLR7},
586  {"trcrsctlr8", TRCRSCTLR8},
587  {"trcrsctlr9", TRCRSCTLR9},
588  {"trcrsctlr10", TRCRSCTLR10},
589  {"trcrsctlr11", TRCRSCTLR11},
590  {"trcrsctlr12", TRCRSCTLR12},
591  {"trcrsctlr13", TRCRSCTLR13},
592  {"trcrsctlr14", TRCRSCTLR14},
593  {"trcrsctlr15", TRCRSCTLR15},
594  {"trcrsctlr16", TRCRSCTLR16},
595  {"trcrsctlr17", TRCRSCTLR17},
596  {"trcrsctlr18", TRCRSCTLR18},
597  {"trcrsctlr19", TRCRSCTLR19},
598  {"trcrsctlr20", TRCRSCTLR20},
599  {"trcrsctlr21", TRCRSCTLR21},
600  {"trcrsctlr22", TRCRSCTLR22},
601  {"trcrsctlr23", TRCRSCTLR23},
602  {"trcrsctlr24", TRCRSCTLR24},
603  {"trcrsctlr25", TRCRSCTLR25},
604  {"trcrsctlr26", TRCRSCTLR26},
605  {"trcrsctlr27", TRCRSCTLR27},
606  {"trcrsctlr28", TRCRSCTLR28},
607  {"trcrsctlr29", TRCRSCTLR29},
608  {"trcrsctlr30", TRCRSCTLR30},
609  {"trcrsctlr31", TRCRSCTLR31},
610  {"trcssccr0", TRCSSCCR0},
611  {"trcssccr1", TRCSSCCR1},
612  {"trcssccr2", TRCSSCCR2},
613  {"trcssccr3", TRCSSCCR3},
614  {"trcssccr4", TRCSSCCR4},
615  {"trcssccr5", TRCSSCCR5},
616  {"trcssccr6", TRCSSCCR6},
617  {"trcssccr7", TRCSSCCR7},
618  {"trcsscsr0", TRCSSCSR0},
619  {"trcsscsr1", TRCSSCSR1},
620  {"trcsscsr2", TRCSSCSR2},
621  {"trcsscsr3", TRCSSCSR3},
622  {"trcsscsr4", TRCSSCSR4},
623  {"trcsscsr5", TRCSSCSR5},
624  {"trcsscsr6", TRCSSCSR6},
625  {"trcsscsr7", TRCSSCSR7},
626  {"trcsspcicr0", TRCSSPCICR0},
627  {"trcsspcicr1", TRCSSPCICR1},
628  {"trcsspcicr2", TRCSSPCICR2},
629  {"trcsspcicr3", TRCSSPCICR3},
630  {"trcsspcicr4", TRCSSPCICR4},
631  {"trcsspcicr5", TRCSSPCICR5},
632  {"trcsspcicr6", TRCSSPCICR6},
633  {"trcsspcicr7", TRCSSPCICR7},
634  {"trcpdcr", TRCPDCR},
635  {"trcacvr0", TRCACVR0},
636  {"trcacvr1", TRCACVR1},
637  {"trcacvr2", TRCACVR2},
638  {"trcacvr3", TRCACVR3},
639  {"trcacvr4", TRCACVR4},
640  {"trcacvr5", TRCACVR5},
641  {"trcacvr6", TRCACVR6},
642  {"trcacvr7", TRCACVR7},
643  {"trcacvr8", TRCACVR8},
644  {"trcacvr9", TRCACVR9},
645  {"trcacvr10", TRCACVR10},
646  {"trcacvr11", TRCACVR11},
647  {"trcacvr12", TRCACVR12},
648  {"trcacvr13", TRCACVR13},
649  {"trcacvr14", TRCACVR14},
650  {"trcacvr15", TRCACVR15},
651  {"trcacatr0", TRCACATR0},
652  {"trcacatr1", TRCACATR1},
653  {"trcacatr2", TRCACATR2},
654  {"trcacatr3", TRCACATR3},
655  {"trcacatr4", TRCACATR4},
656  {"trcacatr5", TRCACATR5},
657  {"trcacatr6", TRCACATR6},
658  {"trcacatr7", TRCACATR7},
659  {"trcacatr8", TRCACATR8},
660  {"trcacatr9", TRCACATR9},
661  {"trcacatr10", TRCACATR10},
662  {"trcacatr11", TRCACATR11},
663  {"trcacatr12", TRCACATR12},
664  {"trcacatr13", TRCACATR13},
665  {"trcacatr14", TRCACATR14},
666  {"trcacatr15", TRCACATR15},
667  {"trcdvcvr0", TRCDVCVR0},
668  {"trcdvcvr1", TRCDVCVR1},
669  {"trcdvcvr2", TRCDVCVR2},
670  {"trcdvcvr3", TRCDVCVR3},
671  {"trcdvcvr4", TRCDVCVR4},
672  {"trcdvcvr5", TRCDVCVR5},
673  {"trcdvcvr6", TRCDVCVR6},
674  {"trcdvcvr7", TRCDVCVR7},
675  {"trcdvcmr0", TRCDVCMR0},
676  {"trcdvcmr1", TRCDVCMR1},
677  {"trcdvcmr2", TRCDVCMR2},
678  {"trcdvcmr3", TRCDVCMR3},
679  {"trcdvcmr4", TRCDVCMR4},
680  {"trcdvcmr5", TRCDVCMR5},
681  {"trcdvcmr6", TRCDVCMR6},
682  {"trcdvcmr7", TRCDVCMR7},
683  {"trccidcvr0", TRCCIDCVR0},
684  {"trccidcvr1", TRCCIDCVR1},
685  {"trccidcvr2", TRCCIDCVR2},
686  {"trccidcvr3", TRCCIDCVR3},
687  {"trccidcvr4", TRCCIDCVR4},
688  {"trccidcvr5", TRCCIDCVR5},
689  {"trccidcvr6", TRCCIDCVR6},
690  {"trccidcvr7", TRCCIDCVR7},
691  {"trcvmidcvr0", TRCVMIDCVR0},
692  {"trcvmidcvr1", TRCVMIDCVR1},
693  {"trcvmidcvr2", TRCVMIDCVR2},
694  {"trcvmidcvr3", TRCVMIDCVR3},
695  {"trcvmidcvr4", TRCVMIDCVR4},
696  {"trcvmidcvr5", TRCVMIDCVR5},
697  {"trcvmidcvr6", TRCVMIDCVR6},
698  {"trcvmidcvr7", TRCVMIDCVR7},
699  {"trccidcctlr0", TRCCIDCCTLR0},
700  {"trccidcctlr1", TRCCIDCCTLR1},
701  {"trcvmidcctlr0", TRCVMIDCCTLR0},
702  {"trcvmidcctlr1", TRCVMIDCCTLR1},
703  {"trcitctrl", TRCITCTRL},
704  {"trcclaimset", TRCCLAIMSET},
705  {"trcclaimclr", TRCCLAIMCLR},
706
707  // GICv3 registers
708  {"icc_bpr1_el1", ICC_BPR1_EL1},
709  {"icc_bpr0_el1", ICC_BPR0_EL1},
710  {"icc_pmr_el1", ICC_PMR_EL1},
711  {"icc_ctlr_el1", ICC_CTLR_EL1},
712  {"icc_ctlr_el3", ICC_CTLR_EL3},
713  {"icc_sre_el1", ICC_SRE_EL1},
714  {"icc_sre_el2", ICC_SRE_EL2},
715  {"icc_sre_el3", ICC_SRE_EL3},
716  {"icc_igrpen0_el1", ICC_IGRPEN0_EL1},
717  {"icc_igrpen1_el1", ICC_IGRPEN1_EL1},
718  {"icc_igrpen1_el3", ICC_IGRPEN1_EL3},
719  {"icc_seien_el1", ICC_SEIEN_EL1},
720  {"icc_ap0r0_el1", ICC_AP0R0_EL1},
721  {"icc_ap0r1_el1", ICC_AP0R1_EL1},
722  {"icc_ap0r2_el1", ICC_AP0R2_EL1},
723  {"icc_ap0r3_el1", ICC_AP0R3_EL1},
724  {"icc_ap1r0_el1", ICC_AP1R0_EL1},
725  {"icc_ap1r1_el1", ICC_AP1R1_EL1},
726  {"icc_ap1r2_el1", ICC_AP1R2_EL1},
727  {"icc_ap1r3_el1", ICC_AP1R3_EL1},
728  {"ich_ap0r0_el2", ICH_AP0R0_EL2},
729  {"ich_ap0r1_el2", ICH_AP0R1_EL2},
730  {"ich_ap0r2_el2", ICH_AP0R2_EL2},
731  {"ich_ap0r3_el2", ICH_AP0R3_EL2},
732  {"ich_ap1r0_el2", ICH_AP1R0_EL2},
733  {"ich_ap1r1_el2", ICH_AP1R1_EL2},
734  {"ich_ap1r2_el2", ICH_AP1R2_EL2},
735  {"ich_ap1r3_el2", ICH_AP1R3_EL2},
736  {"ich_hcr_el2", ICH_HCR_EL2},
737  {"ich_misr_el2", ICH_MISR_EL2},
738  {"ich_vmcr_el2", ICH_VMCR_EL2},
739  {"ich_vseir_el2", ICH_VSEIR_EL2},
740  {"ich_lr0_el2", ICH_LR0_EL2},
741  {"ich_lr1_el2", ICH_LR1_EL2},
742  {"ich_lr2_el2", ICH_LR2_EL2},
743  {"ich_lr3_el2", ICH_LR3_EL2},
744  {"ich_lr4_el2", ICH_LR4_EL2},
745  {"ich_lr5_el2", ICH_LR5_EL2},
746  {"ich_lr6_el2", ICH_LR6_EL2},
747  {"ich_lr7_el2", ICH_LR7_EL2},
748  {"ich_lr8_el2", ICH_LR8_EL2},
749  {"ich_lr9_el2", ICH_LR9_EL2},
750  {"ich_lr10_el2", ICH_LR10_EL2},
751  {"ich_lr11_el2", ICH_LR11_EL2},
752  {"ich_lr12_el2", ICH_LR12_EL2},
753  {"ich_lr13_el2", ICH_LR13_EL2},
754  {"ich_lr14_el2", ICH_LR14_EL2},
755  {"ich_lr15_el2", ICH_LR15_EL2}
756};
757
758const AArch64NamedImmMapper::Mapping
759AArch64SysReg::SysRegMapper::CycloneSysRegPairs[] = {
760  {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3}
761};
762
763uint32_t
764AArch64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const {
765  std::string NameLower = Name.lower();
766
767  // First search the registers shared by all
768  for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) {
769    if (SysRegPairs[i].Name == NameLower) {
770      Valid = true;
771      return SysRegPairs[i].Value;
772    }
773  }
774
775  // Next search for target specific registers
776  if (FeatureBits & AArch64::ProcCyclone) {
777    for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
778      if (CycloneSysRegPairs[i].Name == NameLower) {
779        Valid = true;
780        return CycloneSysRegPairs[i].Value;
781      }
782    }
783  }
784
785  // Now try the instruction-specific registers (either read-only or
786  // write-only).
787  for (unsigned i = 0; i < NumInstPairs; ++i) {
788    if (InstPairs[i].Name == NameLower) {
789      Valid = true;
790      return InstPairs[i].Value;
791    }
792  }
793
794  // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name, where the bits
795  // are: 11 xxx 1x11 xxxx xxx
796  Regex GenericRegPattern("^s3_([0-7])_c(1[15])_c([0-9]|1[0-5])_([0-7])$");
797
798  SmallVector<StringRef, 4> Ops;
799  if (!GenericRegPattern.match(NameLower, &Ops)) {
800    Valid = false;
801    return -1;
802  }
803
804  uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
805  uint32_t Bits;
806  Ops[1].getAsInteger(10, Op1);
807  Ops[2].getAsInteger(10, CRn);
808  Ops[3].getAsInteger(10, CRm);
809  Ops[4].getAsInteger(10, Op2);
810  Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
811
812  Valid = true;
813  return Bits;
814}
815
816std::string
817AArch64SysReg::SysRegMapper::toString(uint32_t Bits, bool &Valid) const {
818  // First search the registers shared by all
819  for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) {
820    if (SysRegPairs[i].Value == Bits) {
821      Valid = true;
822      return SysRegPairs[i].Name;
823    }
824  }
825
826  // Next search for target specific registers
827  if (FeatureBits & AArch64::ProcCyclone) {
828    for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
829      if (CycloneSysRegPairs[i].Value == Bits) {
830        Valid = true;
831        return CycloneSysRegPairs[i].Name;
832      }
833    }
834  }
835
836  // Now try the instruction-specific registers (either read-only or
837  // write-only).
838  for (unsigned i = 0; i < NumInstPairs; ++i) {
839    if (InstPairs[i].Value == Bits) {
840      Valid = true;
841      return InstPairs[i].Name;
842    }
843  }
844
845  uint32_t Op0 = (Bits >> 14) & 0x3;
846  uint32_t Op1 = (Bits >> 11) & 0x7;
847  uint32_t CRn = (Bits >> 7) & 0xf;
848  uint32_t CRm = (Bits >> 3) & 0xf;
849  uint32_t Op2 = Bits & 0x7;
850
851  // Only combinations matching: 11 xxx 1x11 xxxx xxx are valid for a generic
852  // name.
853  if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
854      Valid = false;
855      return "";
856  }
857
858  assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
859
860  Valid = true;
861  return "s3_" + utostr(Op1) + "_c" + utostr(CRn)
862               + "_c" + utostr(CRm) + "_" + utostr(Op2);
863}
864
865const AArch64NamedImmMapper::Mapping AArch64TLBI::TLBIMapper::TLBIPairs[] = {
866  {"ipas2e1is", IPAS2E1IS},
867  {"ipas2le1is", IPAS2LE1IS},
868  {"vmalle1is", VMALLE1IS},
869  {"alle2is", ALLE2IS},
870  {"alle3is", ALLE3IS},
871  {"vae1is", VAE1IS},
872  {"vae2is", VAE2IS},
873  {"vae3is", VAE3IS},
874  {"aside1is", ASIDE1IS},
875  {"vaae1is", VAAE1IS},
876  {"alle1is", ALLE1IS},
877  {"vale1is", VALE1IS},
878  {"vale2is", VALE2IS},
879  {"vale3is", VALE3IS},
880  {"vmalls12e1is", VMALLS12E1IS},
881  {"vaale1is", VAALE1IS},
882  {"ipas2e1", IPAS2E1},
883  {"ipas2le1", IPAS2LE1},
884  {"vmalle1", VMALLE1},
885  {"alle2", ALLE2},
886  {"alle3", ALLE3},
887  {"vae1", VAE1},
888  {"vae2", VAE2},
889  {"vae3", VAE3},
890  {"aside1", ASIDE1},
891  {"vaae1", VAAE1},
892  {"alle1", ALLE1},
893  {"vale1", VALE1},
894  {"vale2", VALE2},
895  {"vale3", VALE3},
896  {"vmalls12e1", VMALLS12E1},
897  {"vaale1", VAALE1}
898};
899
900AArch64TLBI::TLBIMapper::TLBIMapper()
901  : AArch64NamedImmMapper(TLBIPairs, 0) {}
902